Analog Devices AD7490 a Datasheet

16-Channel, 1 MSPS, 12-Bit ADC

a

with Sequencer in 28-Lead TSSOP

FEATURES
Fast Throughput Rate: 1 MSPS
Specified for V

of 2.7 V to 5.25 V

DD

Low Power at Max Throughput Rates:

5.4 mW Max at 870 kSPS with 3 V Supplies

12.5 mW Max at 1 MSPS with 5 V Supplies
16 (Single-Ended) Inputs with Sequencer
Wide Input Bandwidth:

69.5 dB SNR at 50 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface SPI™/QSPI™/

MICROWIRE™/DSP Compatible
Full Shutdown Mode: 0.5 A Max
28-Lead TSSOP and 32-Lead LFCSP Packages

GENERAL DESCRIPTION

The AD7490 is a 12-bit high speed, low power, 16-channel,
successive-approximation ADC. The part operates from a single

2.7 V to 5.25 V power supply and features throughput rates up
to 1 MSPS. The part contains a low noise, wide bandwidth
track-and-hold amplifier that can handle input frequencies in
excess of 1 MHz.

The conversion process and data acquisition are controlled
using CS and the serial clock signal, allowing the device to
easily interface with microprocessors or DSPs. The input signal
is sampled on the falling edge of CS and conversion is also
initiated at this point. There are no pipeline delays associated
with the part.

The AD7490 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. For maximum
throughput rates, the AD7490 consumes just 1.8 mA with 3 V
supplies, and 2.5 mA with 5 V supplies.

By setting the relevant bits in the Control Register, the analog
input range for the part can be selected to be a 0 to REF
a 0 to 2  REF

with either straight binary or twos complement

IN

input or

IN

output coding. The AD7490 features 16 single-ended analog
inputs with a channel sequencer to allow a preprogrammed
selection of channels to be converted sequentially.

The conversion time is determined by the SCLK frequency as
this is also used as the master clock to control the conversion.

The AD7490 is available in a 28-lead thin shrink small outline
(TSSOP) package, and a 32-lead chip scale package.

SPI and QSPI are trademarks of Motorola Inc.
MICROWIRE is a trademark of National Semiconductor Corporation

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

AD7490

FUNCTIONAL BLOCK DIAGRAM

V

DD

REF

IN

VIN0

•

•

•

•

•

•

•

•

•

•

•

•

•
15

V

IN

MUX

AD7490

I/P

PRODUCT HIGHLIGHTS

1. High Throughput with Low Power Consumption
The AD7490 offers up to 1 MSPS throughput rates. At
maximum throughput with 3 V supplies, the AD7490
dissipates just 5.4 mW of power.

2. Sixteen Single-Ended Inputs with Channel Sequencer
A Sequence of channels can be selected, through which the
AD7490 will cycle and convert.

3. Single-Supply Operation with V
The AD7490 operates from a single 2.7 V to 5.25 V supply.
The V

function allows the serial interface to connect

DRIVE

directly to either 3 V or 5 V processor systems independent

.

of V

DD

4. Flexible Power/Serial Clock Speed Management
The conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. The part also features various shutdown
modes to maximize power efficiency at lower throughput
rates. Power consumption is 0.5 µA max when in full shutdown.

5. No Pipeline Delay
The part features a standard successive-approximation ADC
with accurate control of the sampling instant via a CS input
and once off conversion control.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

T/H

SEQUENCER

SUCCESSIVE

APPROXIMATION

CONTROL LOGIC

GND

DRIVE

12-BIT

ADC

Function

SCLK

DOUT

DIN

CS

V

DRIVE

AD7490–SPECIFICATIONS

(VDD = V

= 2.7 V to 5.25 V, REFIN = 2.5 V, f

DRIVE

otherwise noted.)

1

= 20 MHz, TA = T

SCLK

MIN

to T

MAX

, unless

Parameter B Version

DYNAMIC PERFORMANCE f

Signal to Noise +1 Distortion

Signal to Noise Ratio (SNR)
Total Harmonic Distortion (THD)

Peak Harmonic or Spurious Noise (SFDR)

Intermodulation Distortion (IMD)

(SINAD)

3

3

3

3

69 dB min @ 5 V, 70.5 dB typ
68 dB min @ 3 V, 69.5 dB typ

69.5 dB min

–74 dB max @ 5 V, –84 dB typ
–71 dB max @ 3 V, –77 dB typ

3

–75 dB max @ 5 V, –86 dB typ
–73 dB max @ 3 V, –80 dB typ

2

Unit Test Conditions/Comments

= 50 kHz Sine Wave, f

IN

fa = 40.1 kHz, fb = 41.5 kHz

= 20 MHz

SCLK

Second Order Terms –85 dB typ
Third Order Terms –85 dB typ
Aperture Delay 10 ns typ
Aperture Jitter 50 ps typ
Channel-to-Channel Isolation

3

–82 dB typ fIN = 400 kHz

Full Power Bandwidth 8.2 MHz typ @ 3 dB

1.6 MHz typ @ 0.1 dB

DC ACCURACY

3

Resolution 12 Bits
Integral Nonlinearity ±1 LSB max
Differential Nonlinearity –0.95/+1.5 LSB max Guaranteed No Missed Codes to 12 Bits
0V to V

Input Range Straight Binary Output Coding

REF IN

Offset Error ± 8 LSB max ±0.6 LSB typ
Offset Error Match ±0.5 LSB max
Gain Error ±2 LSB max
Gain Error Match ±0.6 LSB max

0V to 2  V

Input Range –V

REF IN

REF IN

to +V

Biased about V

REF IN

Twos Complement Output Coding Offset

Positive Gain Error ±2 LSB max
Positive Gain Error Match ±0.5 LSB max
Zero Code Error ±8 LSB max ± 0.6 LSB typ
Zero Code Error Match ±0.5 LSB max
Negative Gain Error ±1 LSB max
Negative Gain Error Match ±0.5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to REF

0 to 2  REF

V RANGE Bit Set to 1

IN

V RANGE Bit Set to 0,

IN

V

DD/VDRIVE

= 4.75 V to 5.25 V for 0 to 2  REF

DC Leakage Current ±1 µA max
Input Capacitance 20 pF typ

REFERENCE INPUT

REFIN Input Voltage 2.5 V ± 1% Specified Performance
DC Leakage Current ±1 µA max
REFIN Input Impedance 36 kΩ typ f

SAMPLE

= 1 MSPS

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

INL

IN

IN

INH

4

0.7  V

0.3  V

DRIVE

DRIVE

V min
V max

±1 µA max Typically 10 nA, VIN5 0 V or V
10 pF max

DRIVE

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current ±10 µA max Weak/Tri Bit Set to 0
Floating-State Output Capacitance

OH

OL

4

V

– 0.2 V min I

DRIVE

0.4 V max I

= 200 µA; VDD= 2.7 V to 5.25 V

SOURCE

= 200 µA

SINK

10 pF max Weak/Tri Bit Set to 0

Output Coding Straight (Natural) Binary Coding Bit Set to 1

Twos Complement Coding Bit Set to 0

REF

with

IN

–2–

REV. A

AD7490

Parameter B Version

2

Unit Test Conditions/Comments

CONVERSION RATE

Conversion Time 800 ns max 16 SCLK Cycles, SCLK = 20 MHz
Track-and-Hold Acquisition Time

3

300 ns max Sine Wave Input
300 ns max Full-Scale Step Input

Throughput Rate 1 MSPS max @ 5 V (See Serial Interface section.)

POWER REQUIREMENTS

V

DD

V

DRIVE

I

DD

5

2.7/5.25 V min/max

2.7/5.25 V min/max
Digital I/Ps = 0 V or V

DRIVE

Normal Mode (Static) 600 µA typ VDD= 2.7 V to 5.25 V, SCLK On or Off
Normal Mode (Operational) 2.5 mA max V
(f

= Max Throughput) 1.8 mA max VDD= 2.7 V to 3.6 V, f

S

Auto Standby Mode 1.55 mA typ f

= 4.75 V to 5.25 V, f

DD

= 500 kSPS

SAMPLE

SCLK

SCLK

= 20 MHz

= 20 MHz

92 µA max Static

Auto Shutdown Mode 960 µA typ f

SAMPLE

= 250 kSPS

0.5 µA max Static

Full Shutdown Mode 0.5 µA max SCLK On or Off (20 nA typ)

Power Dissipation

Normal Mode (Operational) 12.5 mW max VDD= 5 V, f

Auto Standby Mode (Static) 460 µW max V

Auto Shutdown Mode (Static) 2.5 µW max V

Full Shutdown Mode 2.5 µW max V

5

= 20 MHz

5.4 mW max V

276 µW max V

1.5 µW max V

DD

DD

DD

DD

DD

DD

= 3 V, f
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V

SCLK

SCLK

= 20 MHz

1.5 µW max VDD= 3 V

NOTES

1

Specifications apply for f

2

Temperature Ranges (B Version): –40°C to +85°C.

3

See Terminology section.

4

Sample tested at 25°C to ensure compliance.

5

See Power Versus Throughput Rate section.

Specifications subject to change without notice.

up to 20 MHz. However, for serial interfacing requirements, see Timing Specifications.

SCLK

–3–REV. A

AD7490

TIMING SPECIFICATIONS

1

(VDD = 2.7 V to 5.25 V, V

Limit at T

MIN

, T

MAX

DRIVE ≤ VDD

, REFIN = 2.5 V; TA = T

MIN

to T

, unless otherwise noted.)

MAX

Parameter VDD = 3 V VDD = 5 V Unit Description

f

SCLK

2

10 10 kHz min
16 20 MHz max

t

CONVERT

t

QUIET

16  t

SCLK

16  t

SCLK

50 50 ns min Minimum Quiet Time Required between Bus

Relinquish and Start of Next Conversion

t

2

3

t

3

4

t

b

3

3

t

4

t

5

t

6

t

7

5

t

8

t

9

t

10

t

11

t

12

12 10 ns min CS to SCLK Setup Time
20 14 ns max Delay from CS until DOUT Three-State Disabled
30 20 ns max Delay from CS to DOUT Valid
60 40 ns max Data Access Time after SCLK Falling Edge

0.4 t

0.4 t

SCLK

SCLK

0.4 t

0.4 t

SCLK

SCLK

ns min SCLK Low Pulsewidth

ns min SCLK High Pulsewidth
15 15 ns min SCLK to DOUT Valid Hold Time
15/50 15/50 ns min/max SCLK Falling Edge to DOUT High Impedance
20 20 ns min DIN Setup Time prior to SCLK Falling Edge
55ns min DIN Hold Time after SCLK Falling Edge
20 20 ns min Sixteenth SCLK Falling Edge to CS High
11µs max Power-Up Time from Full Power-Down/

Auto Shutdown/Auto Standby Modes

NOTES

1

Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
(See Figure 1.) The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.

2

Mark/Space ratio for the SCLK input is 40/60 to 60/40. The maximum SCLK frequency is 16 MHz with VDD = 3 V to give a throughput of 870 kSPS. Care must be
taken when interfacing to account for data access time t4, and the setup time required for the user’s processor. These two times will determine the maximum SCLK
frequency with which the user’s system can operate. (See Serial Interface section.)

3

Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 0.7 V

4

t3b represents a worst-case figure for having ADD3 available on the DOUT line, i.e., if the AD7490 went back into three-state at the end of a conversion and some
other device took control of the bus between conversions, the user would have to wait a maximum time of t3b before having ADD3 valid on DOUT line. If the DOUT
line is weakly driven to ADD3 between conversions, then the user would typically have to wait 17 ns at 3 V and 12 ns at 5 V after the CS falling edge before seeing
ADD3 valid on DOUT.

5

t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics, is the true bus relinquish
time of the part and is independent of the bus loading.

Specifications subject to change without notice.

DRIVE

V.

–4–

REV. A

AD7490

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted.)

1

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V

to GND . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

DRIVE

Analog Input Voltage to GND . . . . . . . –0.3 V to V

+ 0.3 V

DD

Digital Input Voltage to GND . . . . . . . . . . . . . –0.3 V to +7 V

Digital Output Voltage to GND . . . . . –0.3 V to V

REFIN to GND . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

Input Current to Any Pin Except Supplies

2

. . . . . . . . ±10 mA

+ 0.3 V

DD

Operating Temperature Ranges

Commercial (B Version) . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

TO

OUTPUT

PIN

C

L

25pF

Figure 1. Load Circuit for Digital Output Timing Specifications

LFCSP, TSSOP Package, Power Dissipation . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . 108.2°C/W (LFCSP)

θ

JA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 97.9°C/W (TSSOP)

Thermal Impedance . . . . . . . . . . . 32.71°C/W (LFCSP)

θ

JC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14°C/W (TSSOP)

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch up.

200A

200A

I

OL

1.6V

I

OH

ORDERING GUIDE

Temperature Linearity Package Package

Model Range Error (LSB)1Option Description

AD7490BCP –40°C to +85°C ± 1 CP-32 LFCSP
AD7490BRU –40°C to +85°C ± 1 RU-28 TSSOP
EVAL-AD7490CB

2

Evaluation Board

EVAL-CONTROL BRD23Controller Board

NOTES

1

Linearity error refers to integral linearity error.

2

This can be used as a stand-alone evaluation board or in conjunction with the Evaluation Controller Board for evaluation/
demonstration purposes.

3

This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in
the CB designators. To order a complete evaluation kit, you will need to order the particular ADC evaluation board, e.g.,
EVAL-AD7490CB, the EVAL-CONTROL-BRD2, and a 12 V ac transformer. See relevant evaluation board technical note for
more information.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7490 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–5–REV. A

AD7490

PIN CONFIGURATIONS*

28-Lead TSSOP

11

V

1

IN

V

10

2

IN

9

V

3

IN

NC

4

8

V

5

IN

7

V

6

IN

AD7490

V

6

7

IN

TOP VIEW

(Not to Scale)

5

V

8

IN

4

V

9

IN

3

V

10

IN

V

2

11

IN

1

V

12

IN

0

V

13

IN

AGND

14

NC = NO CONNECT

V

12

28

IN

13

V

27

IN

14

V

26

IN

V

15

25

IN

AGND

24

REF

23

IN

V

22

DD

AGND

21

20

CS

DIN

19

NC

18

V

17

DRIVE

SCLK

16

DOUT

15

*ALL NC PINS SHOULD BE CONNECTED STRAIGHT TO AGND

NC

8

V

IN

7

V

IN

6

V

IN

5

V

IN

4

V

IN

3

V

IN

NC

32-Lead LFCSP

10

12

13

IN

AGND

IN

V

DOUT

IN

V

SCLK

14

IN

V

DRIVE

V

NC

NC

24

23

22

21

20

19

18

17

V

NC

AGND

REF

V

AGND

CS

DIN

11

9

IN

IN

V

V

V

NC

32 31 30 29 2 8 27 26 25

1

2

3

4

5

6

7

8

EXPOSED PAD SHOULD BE TIED TO AGND

AD7490

TOP VIEW

TOP VIEW

(Not to Scale)

(Not to Scale)

9 10 11 12 1 3 14 15 16

2

1

0

IN

IN

IN

V

V

V

NC = NO CONNECT

15

IN

IN

DD

PIN FUNCTION DESCRIPTIONS

Mnemonic Function

CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the

AD7490 and also frames the serial data transfer.

REF

IN

Reference Input for the AD7490. An external reference must be applied to this input. The voltage range
for the external reference is 2.5 V ± 1% for specified performance.

V

DD

Power Supply Input. The VDD range for the AD7490 is from 2.7 V to 5.25 V. For the 0 to 2  REF

IN

range, VDD should be from 4.75 V to 5.25 V.

AGND Analog Ground. Ground reference point for all circuitry on the AD7490. All analog/digital input signals

and any external reference signal should be referred to this AGND voltage. All AGND pins should be
connected together.

V

0–VIN15 Analog Input 0 through Analog Input 15. Sixteen single-ended analog input channels that are multiplexed

IN

into the on-chip track-and-hold. The analog input channel to be converted is selected by using the address
bits ADD3 through ADD0 of the control register. The address bits in conjunction with the SEQ and
SHADOW bits allow the Sequence Register to be programmed. The input range for all input channels can
extend from 0 V to REF

or 0 V to 2  REFIN as selected via the RANGE bit in the Control Register.

IN

Any unused input channels should be connected to AGND to avoid noise pickup.

DIN Data In. Logic input. Data to be written to the AD7490’s Control Register is provided on this input and

is clocked into the register on the falling edge of SCLK (see Control Register section).

DOUT Data Out. Logic output. The conversion result from the AD7490 is provided on this output as a serial

data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists
of four address bits indicating which channel the conversion result corresponds to, followed by the 12 bits
of conversion data, which is provided MSB first. The output coding may be selected as straight binary or
twos complement via the CODING Bit in the Control Register.

SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock

input is also used as the clock source for the AD7490’s conversion process.

V

DRIVE

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface
of the AD7490 will operate.

–6–

REV. A

AD7490

TERMINOLOGY
Integral Nonlinearity

This is the maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. The endpoints of
the transfer function are zero scale, a point 1 LSB below the first
code transition, and full scale, a point 1 LSB above the last code
transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

Offset Error

This is the deviation of the first code transition (00…000) to
(00…001) from the ideal, i.e., AGND  1 LSB.

Offset Error Match

This is the difference in offset error between any two channels.

Gain Error

This is the deviation of the last code transition (111…110) to
(111…111) from the ideal (i.e., REFIN  1LSB) after the offset
error has been adjusted out.

Gain Error Match

This is the difference in gain error between any two channels.

Zero Code Error

This applies when using the twos complement output coding
option, in particular to the 2  REF
to +REFIN biased about the REF
midscale transition (all 0s to all 1s) from the ideal V
i.e., REF

Zero Code Error Match

– 1 LSB.

IN

input range with –REF

IN

point. It is the deviation of the

IN

voltage,

IN

IN

This is the difference in zero code error between any two channels.

Positive Gain Error

This applies when using the twos complement output coding
option, in particular to the 2  REF
to +REFIN biased about the REF

input range with –REF

IN

point. It is the deviation of

IN

IN

the last code transition (011…110) to (011…111) from the ideal
(i.e., +REF

 1 LSB) after the Zero Code Error has been

IN

adjusted out.

Positive Gain Error Match

This is the difference in Positive Gain Error between any two
channels.

Negative Gain Error

This applies when using the twos complement output coding
option, in particular to the 2  REF
to +REFIN biased about the REF

input range with –REF

IN

point. It is the deviation of

IN

IN

the first code transition (100…000) to (100…001) from the
ideal (i.e., –REF

+ 1 LSB) after the Zero Code Error has been

IN

adjusted out.

Negative Gain Error Match

This is the difference in negative gain error between any two
channels.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of cross­talk between channels. It is measured by applying a full-scale
400 kHz sine wave signal to all 15 nonselected input channels and
determining how much that signal is attenuated in the selected
channel with a 50 kHz signal. The figure is given worst case
across all 16 channels for the AD7490.

PSR (Power Supply Rejection)

Variations in power supply will affect the full scale transition, but not
the converter’s linearity. Power supply rejection is the maximum
change in full-scale transition point due to a change in power­supply voltage from the nominal value. (See Typical Performance
Characteristics.)

Track/Hold Acquisition Time

The track/hold amplifier returns into track on the 14th SCLK
falling edge. Track/hold acquisition time is the minimum time
required for the track and hold amplifier to remain in track
mode for its output to reach and settle to within ±1 LSB of the
applied input signal, given a step change to the input signal.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (f

/2), excluding dc. The ratio

S

is dependent on the number of quantization levels in the digitiza­tion process; the more levels, the smaller the quantization noise.
The theoretical signal to (noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by:

Signal to Noise Distortion N dB ()(..)+=+602 176

Thus for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7490, it is defined as:

2

THD dB

() log=×

20

VVVVV

++++

223242526

V

1

where V1 is the rms amplitude of the fundamental and V2, V3,

V

, V5, and V6 are the rms amplitudes of the second through the

4

sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the rms
value of the next largest component in the ADC output spectrum
(up to f

/2 and excluding dc) to the rms value of the fundamental.

S

Normally, the value of this specification is determined by the
largest harmonic in the spectrum, but for ADCs where the har­monics are buried in the noise floor, it will be a noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and fb,
any active device with nonlinearities will create distortion products
at sum and difference frequencies of mfa ± nfb, where m, n = 0,
1, 2, 3, and so on. Intermodulation distortion terms are those for
which neither m nor n are equal to zero. For example, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).

The AD7490 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second order terms are usually distanced in
frequency from the original sine waves while the third order terms
are usually at a frequency close to the input frequencies. As a
result, the second and third order terms are specified separately.
The calculation of the intermodulation distortion is as per the
THD specification, where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals expressed in dBs.

–7–REV. A

AD7490–Typical Performance Characteristics

TPC 1 shows a typical FFT plot for the AD7490 at 1 MSPS
sample rate and 50 kHz input frequency.

TPC 3 shows the power supply rejection ratio versus supply
ripple frequency for the AD7490. The power supply rejection
ratio is defined as the ratio of the power in the ADC output at
full-scale frequency f, to the power of a 200 mV p-p sine wave
applied to the ADC V

supply of frequency fS.

DD

PSRR dB

() log=×

10





Pf





Pf





S

Pf is equal to the power at frequency f in ADC output; PfS is equal

to power at frequency fS coupled onto the ADC VDD supply input.
Here, a 200 mV p-p sine wave is coupled onto the V

supply.

DD

10 nF decoupling was used on the supply and a 1 µF decoupling
cap on the REF

5

–15

–35

–55

SNR – dB

–75

–95

IN

pin.

8192 POINT FFT

f

 1MSPS

SAMPLE

f

 50kHz

IN

SINAD  70.697dB
THD  –79.171dB
SFDR  –79.93dB

–20

VDD  3V/5V, 10nF CAP
200mV p-p SINE WAVE ON V

–30

REFIN  2.5V, 1F CAP
TA  25 C

–40

–50

–60

PSRR – dB

–70

–80

–90

01M100k

200k 300k 400k 500k 600k 700k 800k 900k

DD

VDD  5V

 3V

V

DD

INPUT FREQUENCY – Hz

TPC 3. PSRR vs. Supply Ripple Frequency

–50

f

 MAX THROUGHPUT

S

 25 C

T

A

–55

RANGE  0 TO REF

–60

–65

–70

THD – dB

–75

–80

–85

IN

VDD  V

VDD  V

VDD  V

 V

V

DD

DRIVE

DRIVE

DRIVE

DRIVE

 2.7V

 3.6V

 4.75V
 5.25V

–115

0 50050 100 150 200 250 300 350 400

FREQUENCY – kHz

450

TPC 1. Dynamic Performance at 1 MSPS

75

70

65

SINAD – dB

60

f

 MAX THROUGHPUT

S

 25 C

T

A

RANGE  0 TO REF

55

10 1000100

IN

INPUT FREQUENCY – kHz

VDD  V
V

DD

VDD  V

VDD  V

 V

DRIVE

DRIVE

DRIVE

DRIVE

 5.25V
 4.75V

 3.6V

 2.7V

TPC 2. SINAD vs. Analog Input Frequency for
Various Supply Voltages at 1 MSPS

–90

10 1000100

INPUT FREQUENCY – kHz

TPC 4. THD vs. Analog Input Frequency for Various
Supply Voltages at 1 MSPS

–50

f

 1 MSPS

S

 25 C

T

A

–55

 5.25 V

V

DD

RANGE  0 TO REF

–60

–65

–70

THD – dB

–75

–80

–85

RIN  50

10 1000100

IN

RIN  100

RIN  1000RIN  10

INPUT FREQUENCY – kHz

RIN  1000

TPC 5. THD vs. Analog Input Frequency for Various
Analog Source Impedances

–8–

REV. A