ANALOG DEVICES AD7490 Service Manual

16-Channel, 1 MSPS, 12-Bit ADC

V

FEATURES

Fast throughput rate: 1 MSPS Specified for V Low power at maximum throughput rates

5.4 mW maximum at 870 kSPS with 3 V supplies

12.5 mW maximum at 1 MSPS with 5 V supplies 16 (single-ended) inputs with sequencer Wide input bandwidth

69.5 dB SNR at 50 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface, SPI/QSPI™/MICROWIRE™/

DSP compatible Full shutdown mode: 0.5 μA maximum 28-lead TSSOP and 32-lead LFCSP packages

GENERAL DESCRIPTION

The AD7490 is a 12-bit high speed, low power, 16-channel, successive approximation ADC. The part operates from a single

2.7 V to 5.25 V power supply and features throughput rates up to 1 MSPS. The part contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 1 MHz.

The conversion process and data acquisition are controlled

CS

using easily interface with microprocessors or DSPs. The input signal is sampled on the falling edge of initiated at this point. There are no pipeline delays associated with the part.

The AD7490 uses advanced design techniques to achieve very low power dissipation at high throughput rates. For maximum throughput rates, the AD7490 consumes just 1.8 mA with 3 V supplies, and 2.5 mA with 5 V supplies.

By setting the relevant bits in the control register, the analog input range for the part can be selected to be a 0 V to REF input or a 0 V to 2 × REF or twos complement output coding. The AD7490 features 16 single-ended analog inputs with a channel sequencer to allow a preprogrammed selection of channels to be converted sequentially. The conversion time is determined by the SCLK

and the serial clock signal, allowing the device to

of 2.7 V to 5.25 V

DD

input, with either straight binary

IN

CS

, and conversion is also

IN

with Sequencer in 28-Lead TSSOP

AD7490

FUNCTIONAL BLOCK DIAGRAM

DD

REF

IN

VIN0

VIN15

frequency because this is also used as the master clock to control the conversion.

The AD7490 is available in a 32-lead LFCSP and a 28-lead TSSOP package.

PRODUCT HIGHLIGHTS

1. The AD7490 offers up to 1 MSPS throughput rates. At

maximum throughput with 3 V supplies, the AD7490 dissipates just 5.4 mW of power.

2. A sequence of channels can be selected, through which the

AD7490 cycles and converts.

3. The AD7490 operates from a single 2.7 V to 5.25 V supply.

The V directly to either 3 V or 5 V processor systems independent of V

4. The conversion rate is determined by the serial clock,

allowing the conversion time to be reduced through the serial clock speed increase. The part also features various shutdown modes to maximize power efficiency at lower throughput rates. Power consumption is 0.5 µA, maximum, when in full shutdown.

5. The part features a standard successive approximation

ADC with accurate control of the sampling instant via a input and once off conversion control.

AD7490

12-BIT

T/H

INPUT

MUX

SEQUENCER

function allows the serial interface to connect

DRIVE

.

DD

SUCCESSIVE

APPROXIMATION

ADC

CONTROL

LOGIC

AGND

Figure 1.

SCLK

DOUT

DIN

CS

V

DRIVE

02691-001

CS

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD7490

REVISION HISTORY

6/09—Rev. B to Rev. C

Change to I

5/08—Rev. A to Rev. B

Updated Format .................................................................. Universal

Changes to Table 1 ............................................................................ 3

Changes to Figure 12 and Figure 13 ............................................. 14

Changes to Figure 14 ...................................................................... 15

Changes to Reference Section ....................................................... 19

Updated Outline Dimensions ....................................................... 26

Changes to Ordering Guide .......................................................... 27

Auto Standby Mode Parameter, Table 1 ............... 4

DD

10/02—Rev. 0 to Rev. A

Addition to General Description..................................................... 1

Changes to Timing Specification Notes ......................................... 4

Change to Absolute Maximum Ratings ......................................... 5

Addition to Ordering Guide ............................................................ 5

Changes to Typical Performance Characteristics .......................... 8

Added new Figure 9 .......................................................................... 8

Changes to Figure 12 and Figure 14............................................. 11

Changes to Figure 20 ...................................................................... 13

Changes to Figure 20 to Figure 26 ................................................ 14

Addition to Analog Input section ................................................ 14

Change to Figure 29 caption ......................................................... 18

Change to Figure 30 to Figure 32 ................................................. 18

Added Application Hints section ................................................. 20

1/02—Revision 0: Initial Version

Rev. C | Page 2 of 28

AD7490

SPECIFICATIONS

VDD = V

= 2.7 V to 5.25 V, REFIN = 2.5 V, f

DRIVE

−40°C to +85°C.

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

DYNAMIC PERFORMANCE fIN = 50 kHz sine wave, f

Signal-to-(Noise + Distortion) (SINAD)

2

V

Signal-to-Noise Ratio (SNR)2 69.5 dB

Total Harmonic Distortion (THD)

2

V

Peak Harmonic or Spurious Noise (SFDR)

2

V

Intermodulation Distortion (IMD)

2

fa = 40.1 kHz, fb = 41.5 kHz

Second-Order Terms −85 dB

Third-Order Terms −85 dB

Aperture Delay 10 ns

Aperture Jitter 50 ps

Channel-to-Channel Isolation

2

f

Full Power Bandwidth 3 dB 8.2 MHz

0.1 dB 1.6 MHz

DC ACCURACY

2

Resolution 12 Bits

Integral Nonlinearity ±1 LSB

Differential Nonlinearity Guaranteed no missed codes to 12 bits −0.95/+1.5 LSB

0 V to REF

Input Range Straight binary output coding

IN

Offset Error ±0.6 ±8 LSB Offset Error Match ±0.5 LSB Gain Error ±2 LSB Gain Error Match ±0.6 LSB

0 V to 2 × REFIN Input Range

Positive Gain Error ±2 LSB Positive Gain Error Match ±0.5 LSB Zero Code Error ±0.6 ±8 LSB Zero Code Error Match ±0.5 LSB Negative Gain Error ±1 LSB Negative Gain Error Match ±0.5 LSB

ANALOG INPUT

Input Voltage Range RANGE bit set to 1 0 REFIN V

DC Leakage Current ±1 μA

Input Capacitance 20 pF

REFERENCE INPUT

REFIN Input Voltage ±1% specified performance 2.5 V

DC Leakage Current ±1 μA

REFIN Input Impedance f

1

= 20 MHz, TA = T

SCLK

to T

MIN

= 20 MHz

SCLK

, unless otherwise noted. Temperature range (B Version):

MAX

VDD = 5 V 69 70.5 dB

= 3 V 68 69.5 dB

DD

= 5 V −84 −74 dB

DD

= 3 V −77 −71 dB

DD

= 5 V −86 −75 dB

DD

= 3 V −80 −73 dB

DD

= 400 kHz −82 dB

IN

to +REFIN biased about REFIN

−REF

IN

with twos complement output coding offset

RANGE bit set to 0, V for 0 V to 2 × REF

= 1 MSPS 36 kΩ

SAMPLE

= 4.75 V to 5.25 V

DD

IN

0 2 × REF

V

IN

Rev. C | Page 3 of 28

AD7490

Parameter Test Conditions/Comments Min Typ Max Unit

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, IIN VIN = 0 V or V Input Capacitance, CIN+

LOGIC OUTPUTS

Output High Voltage, VOH I Output Low Voltage, VOL I Floating State Leakage Current

Floating State Output Capacitance

Output Coding Coding bit set to 1 Straight (Natural) Binary Coding bit set to 0 Twos Complement CONVERSION RATE

Conversion Time 16 SCLK cycles, SCLK = 20 MHz 800 ns

Track-and-Hold Acquisition Time

Full-scale step input 300 ns

Throughput Rate

POWER REQUIREMENTS

VDD 2.7 5.25 V

V

2.7 5.25 V

DRIVE

4

I

DD

Normal Mode (Static) VDD = 2.7 V to 5.25 V, SCLK on or off 600 μA Normal Mode (Operational) VDD = 4.75 V to 5.25 V, f (fS = Maximum Throughput) VDD = 2.7 V to 3.6 V, f Auto Standby Mode f Static 100 μA Auto Shutdown Mode f Static 0.5 μA Full Shutdown Mode SCLK on or off 0.02 0.5 μA

Power Dissipation

Normal Mode (Operational) VDD = 5 V, f V Auto Standby Mode (Static) VDD = 5 V 460 μW V Auto Shutdown Mode (Static) VDD = 5 V 2.5 μW V Full Shutdown Mode VDD = 5 V 2.5 μW V

1

Specifications apply for f

2

See the Terminology section.

3

Guaranteed by characterization.

4

See the Power vs. Throughput Rate section.

0.7 × V

INH

0.3 × V

INL

±0.01 ±1 μA

3

10 pF

SOURCE

= 200 μA 0.4 V

SINK

WEAK/TRI

3

2

Sine wave input 300 ns

WEAK/TRI bit set to 0

= 5 V (see the Serial Interface

V

DD

DRIVE

= 200 μA; VDD = 2.7 V to 5.25 V V

bit set to 0

DRIVE

±10 μA 10 pF

1 MSPS

V

DRIVE

V

DRIVE

− 0.2 V

section)

Digital inputs = 0 V or V

= 500 kSPS 1.55 mA

SAMPLE

= 250 kSPS 960 μA

SAMPLE

4

= 20 MHz 12.5 mW

SCLK

= 3 V, f

DD

= 3 V 276 μW

DD

= 3 V 1.5 μW

DD

= 3 V 1.5 μW

DD

up to 20 MHz. However, for serial interfacing requirements, see the Timing Specifications section.

SCLK

= 20 MHz 5.4 mW

SCLK

DRIVE

= 20 MHz 2.5 mA

SCLK

= 20 MHz 1.8 mA

SCLK

Rev. C | Page 4 of 28

AD7490

T

TIMING SPECIFICATIONS

VDD = 2.7 V to 5.25 V, V

Table 2. Timing Specifications

Limit at T Parameter VDD = 3 V VDD = 5 V Unit Description

2

f

SCLK

10 10 kHz min 16 20 MHz max t

16 × t

CONVER T

t

50 50 ns min Minimum quiet time required between bus relinquish and start of next conversion

QUIET

SCLK

t2 12 10 ns min

3

t

3

20 14 ns max t3b4 30 20 ns max

3

t

60 40 ns max Data access time after SCLK falling edge

4

t5 0.4 × t t6 0.4 × t

SCLK

t7 15 15 ns min SCLK to DOUT valid hold time

5

t

15/50 15/50 ns min/max SCLK falling edge to DOUT high impedance

8

t9 20 20 ns min DIN setup time prior to SCLK falling edge t10 5 5 ns min DIN hold time after SCLK falling edge t11 20 20 ns min

t12 1 1 μs max Power-up time from full power-down/auto shutdown/auto standby modes

1

Guaranteed by characterization. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V (see Figure 2). The 3 V

operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.

2

The mark/space ratio for the SCLK input is 40/60 to 60/40. The maximum SCLK frequency is 16 MHz with VDD = 3 V to give a throughput of 870 kSPS. Care must be

taken when interfacing to account for data access time, t4, and the setup time required for the user’s processor. These two times determine the maximum SCLK frequency with which the user’s system can operate (see the Serial Interface section).

3

Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 V

4

t3b represents a worst-case figure for having ADD3 available on the DOUT line, that is, if the AD7490 goes back into three-state at the end of a conversion and some

other device takes control of the bus between conversions, the user has to wait a maximum time of t3b before having ADD3 valid on the DOUT line. If the DOUT line is weakly driven to ADD3 between conversions, the user typically has to wait 17 ns at 3 V and 12 ns at 5 V after the CS falling edge before seeing ADD3 valid on DOUT.

5

t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated

back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics, is the true bus relinquish time of the part and is independent of the bus loading.

≤ VDD, REFIN = 2.5 V; TA = T

DRIVE

1

, T

MIN

MAX

16 × t

0.4 × t

SCLK

ns min SCLK low pulse width

SCLK

ns min SCLK high pulse width

SCLK

to T

MIN

CS Delay from CS Delay from CS

16

, unless otherwise noted.

MAX

to SCLK setup time

until DOUT three-state disabled to DOUT valid

th

SCLK falling edge to CS high

DRIVE

.

O OUTPUT

25pF

C

200µA I

L

200µA I

OL

1.6V

OH

02691-002

Figure 2. Load Circuit for Digital Output Timing Specifications

Rev. C | Page 5 of 28

AD7490

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND −0.3 V to +7 V V

to GND −0.3 V to VDD + 0.3 V

DRIVE

Analog Input Voltage to GND −0.3 V to VDD + 0.3 V Digital Input Voltage to GND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to VDD + 0.3 V REFIN to GND −0.3 V to VDD + 0.3 V Input Current to Any Pin Except Supplies1±10 mA Operating Temperature Ranges

Commercial (B Version) −40°C to +85°C

Storage Temperature Range −65°C to +150°C Junction Temperature 150°C LFCSP, TSSOP Package, Power Dissipation 450 mW

θJA Thermal Impedance 108.2°C/W (LFCSP)

97.9°C/W (TSSOP)

θJC Thermal Impedance 32.71°C/W (LFCSP) 14°C/W (TSSOP) Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C ESD 1 kV

1

Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. C | Page 6 of 28

AD7490

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

9

10

11

12

13

14

IN

V

28

27

26NC25

24

VIN15

NC

23

AGND

22

REF

21

IN

20

V

DD

AGND

19

CS

18

DIN

17

13

14

15NC16

DRIVE

SCLK

DOUT

V

02691-032

or 0 V to 2 × REFIN as selected

IN

V

11

1

IN

VIN10

2

VIN9

3

NC

4

VIN8

5

VIN7

VIN6

VIN5

VIN4

VIN3

VIN2

VIN1

VIN0

AGND

NC = NO CONNECT ALL NC PINS SHOULD BE CONNECTED STRAI GHT TO AGND

AD7490

6

TOP VIEW

7

(Not to Scale)

8

9

10

11

12

13

14

VIN12

28

VIN13

27

VIN14

26

VIN15

25

AGND

24

REF

23

V

22

DD

AGND

21

CS

20

DIN

19

NC

18

V

17

DRIVE

SCLK

16

DOUT

15

Figure 3. 28-Lead TSSOP Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic Description TSSOP LFCSP

20 18

Chip Select. Active low logic input. This input provides the dual function of initiating

CS

23 21 REFIN

22 20 V

DD

14, 21, 24 12, 19, 22 AGND

V

13 to 5, 3 to 1, 28 to 25

11 to 9, 7 to 2, 31 to 26,

0 to VIN15

IN

24

19 17 DIN

15 13 DOUT

16 14 SCLK

17 15 V

DRIVE

IN

V

31

30

AD7490

TOP VIEW

(Not to Scale)

10

11

1

0

IN

V

IN

V

29

12

ANGD

NC32V

1

NC

VIN8

2

VIN7

IN

02691-003

3

VIN6

4

5

VIN5

VIN4

6

VIN3

7

NC

8

9

2

IN

V

NC = NO CONNECT ALL NC PINS SHOUL D BE CONNECTED STRAI GHT TO AGND

Figure 4. 32-Lead LFCSP Pin Configuration

conversions on the AD7490 and also frames the serial data transfer. Reference Input for the AD7490. An external reference must be applied to this input. The

voltage range for the external reference is 2.5 V ± 1% for specified performance. Power Supply Input. The V

range, V

should be from 4.75 V to 5.25 V.

DD

range for the AD7490 is from 2.7 V to 5.25 V. For the 0 V to 2 × REFIN

DD

Analog Ground. Ground reference point for all circuitry on the AD7490. All analog/digital input signals and any external reference signal should be referred to this AGND voltage. All AGND pins should be connected together.

Analog Input 0 through Analog Input 15. Sixteen single-ended analog input channels that are multiplexed into the on chip track-and-hold. The analog input channel to be converted is selected by using the address bits ADD3 through ADD0 of the control register. The address bits, in conjunction with the SEQ and SHADOW bits, allow the sequence register to be programmed. The input range for all input channels can extend from 0 V to REF via the RANGE bit in the control register. Any unused input channels should be connected to AGND to avoid noise pickup.

Data In. Logic input. Data to be written to the control register of the AD7490 is provided on this input and is clocked into the register on the falling edge of SCLK (see the Control Register section).

Data Out. Logic output. The conversion result from the AD7490 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists of four address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data, which is provided by MSB first. The output coding can be selected as straight binary or twos complement via the CODING bit in the control register.

Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process of the AD7490.

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface of the AD7490 operates.

Rev. C | Page 7 of 28

AD7490

–

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5 shows a typical FFT plot for the AD7490 at 1 MSPS sample rate and 50 kHz input frequency.

Figure 7 shows the power supply rejection ratio vs. supply ripple frequency for the AD7490. The power supply rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency f, to the power of a 200 mV p-p sine wave applied to the ADC V of frequency f

PSRR log10dB

.

S

()

⎛

⎞

Pf

⎜

×=

⎟

⎜

⎟

Pf

s

⎝

⎠

where:

Pf is equal to the power at frequency f in ADC output. Pf

is equal to power at frequency fS coupled onto the ADC VDD supply input.

S

Here, a 200 mV p-p sine wave is coupled onto the V was used on the REF

5

–15

–35

–55

SNR (dB)

–75

–95

0 50 100 150 200 250 300 350 400 500450

pin.

IN

8192 POINT FFT

f

SAMPLE

f

= 50kHZ

IN

SINAD = 70.697dB THD = –79.171dB SFDR = –79.93dB

FREQUENCY (kHz)

Figure 5. Dynamic Performance at 1 MSPS

supply. 10 nF decoupling was used on the supply, and a 1 µF decoupling capacitor

DD

20

V

= 3V/5V, 10nF CAP

= 1MSPS

02691-004

DD

200mV p-p SINE WAVE ON V

–30

REFIN = 2.5V, 1µF CAP T

= 25°C

A

–40

–50

–60

PSRR (dB)

–70

–80

–90

0 100k 200k 300k 400k 500k 600k 700k 800k 900k 1M

DD

VDD = 5V

V

= 3V

DD

INPUT FREQ UENCY (Hz)

Figure 7. PSRR vs. Supply Ripple Frequency

supply

DD

02691-006

75

VDD = V

70

65

SINAD (dB)

60

f

= MAX THROUGHPUT

S

T

= 25°C

A

RANGE = 0V TO REF

55

10 100 1000

IN

INPUT F REQUE NCY (kHz)

V

DD

V

DD

= 5.25V

DRIVE

= V

DD

DRIVE

= V

= 3.6V

DRIVE

= V

= 2.7V

DRIVE

Figure 6. SINAD vs. Analog Input Frequency

for Various Supply Voltages at 1 MSPS

= 4.75V

02691-005

Rev. C | Page 8 of 28

50

f

= MAX THROUGHPUT

S

= 25°C

T

A

–55

RANGE = 0V TO REF

–60

–65

–70

THD (dB)

–75

–80

–85

–90

10 100 1000

IN

INPUT F REQUE NCY (kHz)

VDD = V

V

V V

= 2.7V

DRIVE

= V

= V = V

DRIVE

= 3.6V

= 4.75V = 5.25V

DD

Figure 8. THD vs. Analog Input Frequency

for Various Supply Voltages at 1 MSPS

02691-007

AD7490

–

50

f

= 1MSPS

S

T

= 25°C

A

–55

V

= 5.25V

DD

RANGE = 0V TO REF

–60

–65

–70

THD (dB)

–75

= 5Ω

R

–80

–85

IN

10 100 1000

IN

= 100Ω

R

IN

R

= 10Ω

IN

INPUT FREQ UENCY (Hz)

RIN = 1000Ω

Figure 9. THD vs. Analog Input Frequency

for Various Analog Source Impedances

1.0 VDD = V

0.8

TEMPERATURE = 25°C

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 512 1024 1536 2048 2560 3072 3584 4096

DRIVE

= 5V

CODE

Figure 10. Typical INL

02691-008

02691-009

1.0 VDD = V

0.8

TEMPERATURE = 25°C

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 512 1024 1536 2048 2560 3072 3584 4096

DRIVE

= 5V

CODE

Figure 11. Typical DNL

02691-010

Rev. C | Page 9 of 28

ANALOG DEVICES AD7490 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS