ANALOG DEVICES AD7485 Service Manual

a

A

781/461-3113

2010

1 MSPS, Serial 14-Bit SAR ADC

AD7485

FEATURES
Fast Throughput Rate: 1 MSPS
Wide Input Bandwidth: 40 MHz
Excellent DC Accuracy Performance
Flexible Serial Interface
Low Power:

80 mW (Full Power) and 3 mW (NAP Mode)
STANDBY Mode: 2 A Max
Single 5 V Supply Operation
Internal 2.5 V Reference
Full-Scale Overrange Indication

GENERAL DESCRIPTION

The AD7485 is a 14-bit, high speed, low power, successive­approximation ADC. The part features a serial interface with
throughput rates up to 1 MSPS. The part contains a low noise,
wide bandwidth track-and-hold that can handle input frequencies
in excess of 40 MHz.

The conversion process is a proprietary algorithmic successive­approximation technique. The input signal is sampled and a
conversion is initiated on the falling edge of the CONVST signal.
The conversion process is controlled by an external master
clock. Interfacing is via standard serial signal lines, making the
part directly compatible with microcontrollers and DSPs.

The AD7485 provides excellent ac and dc performance specifi­cations. Factory trimming ensures high dc accuracy resulting in
very low INL, DNL, offset, and gain errors.

The part uses advanced design techniques to achieve very low
power dissipation at high throughput rates. Power consumption
in the normal mode of operation is 80 mW. There are two power­saving modes: a NAP mode keeps reference circuitry alive for
quick power-up and consumes 3 mW, while a STANDBY mode
reduces power consumption to a mere 10 µW.

FUNCTIONAL BLOCK DIAGRAM

REFSEL

VIN

NAP

STBY

RESET

CONVST

AVDDAGND C

2.5 V

REFERENCE

T/H

AD7485

LOGIC AND I/O

BIASDVDD

ALGORITHMIC

CONTROL

REGISTERS

BUF

14-BIT

SAR

V

DRIVE

DGND

REFOUT

REFIN

MCLK

TFS

SCO

SDO

SMODE

The AD7485 features an on-board 2.5 V reference, but the part can
also accommodate an externally provided 2.5 V reference source.
The nominal analog input range is 0 V to 2.5 V.

The AD7485 also provides the user with overrange indication via a
fifteenth bit. If the analog input range strays outside the 0 V to

2.5 V input range, the fifteenth data bit is set to a logic high.

The AD7485 is powered from a 4.75 V to 5.25 V supply. The
part also provides a V

pin that allows the user to set the

DRIVE

voltage levels for the digital interface lines. The range for this
V

pin is from 2.7 V to 5.25 V. The part is housed in a

DRIVE

48-lead LQFP package and is specified over a –40°C to +85°C
temperature range.

REV.

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: © Analog Devices, Inc.,

AD7485–SPECIFICATIONS

A

(VDD = 5 V  5%, AGND = DGND = 0 V, V

1

tions T

MIN

to T

MAX

and valid for V

DRIVE

= External, f

REF

= 1 MSPS; all specifica-

SAMPLE

= 2.7 V to 5.25 V, unless otherwise noted.)

Parameter Specification Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

2, 3

Signal to Noise + Distortion (SINAD)

4

76.5 dB min

fIN = 500 kHz Sine Wave

78 dB typ

Total Harmonic Distortion (THD)

4

77 dB typ Internal Reference

–90 dB max
–95 dB typ
–92 dB typ Internal Reference

Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)

4

Second-Order Terms –96 dB typ f

4

–88 dB max

= 95.053 kHz, f

IN1

= 105.329 kHz

IN2

Third-Order Terms –94 dB typ
Aperture Delay 10 ns typ
Full Power Bandwidth 40 MHz typ @ 3 dB

3.5 MHz typ @ 0.1 dB

DC ACCURACY

Resolution 14 Bits
Integral Nonlinearity

Differential Nonlinearity

Offset Error

Gain Error

4

4

4

4

± 1LSB max
± 0.5 LSB typ
± 0.75 LSB max Guaranteed No Missed Codes to 14 Bits
± 0.25 LSB typ
± 6LSB max

0.036 %FSR max
± 6LSB max

0.036 %FSR max

ANALOG INPUT

Input Voltage 0 V min

2.5 V max
DC Leakage Current ± 1 µA max
Input Capacitance

5

35 pF typ

REFERENCE INPUT/OUTPUT

V

Input Voltage 2.5 V ± 1% for Specified Performance

REFIN

V

Input DC Leakage Current ± 1 µA max

REFIN

V

Input Capacitance

REFIN

V

Input Current

REFIN

V
V
V
V

Output Voltage 2.5 V typ

REFOUT

Error @ 25°C ± 50 mV typ

REFOUT

Error T

REFOUT

Output Impedance 1 Ω typ

REFOUT

MIN

6

to T

5

MAX

25 pF typ
220 A typ External Reference

± 100 mV max

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current ± 10 µA max
Floating-State Output Capacitance

INH

INL

IN

5

IN

7

OH

7

OL

5

V

–1V min

DRIVE

0.4 V max

± 1 µA max
10 pF typ

0.7 × V

0.3 × V

DRIVE

DRIVE

V min
V max

10 pF max

Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 24 MCLKs
Track/Hold Acquisition Time 100 ns max Sine Wave Input

70 ns max Full-Scale Step Input

Throughput Rate 1 MSPS max

REV. –2–

Parameter Specification Unit Test Conditions/Comments

131785

A

POWER REQUIREMENTS

V

DD

V

DRIVE

5V± 5%

2.7 V min

5.25 V max

I

DD

Normal Mode (Static) mA max
Normal Mode (Operational) mA max
NAP Mode 0.6 mA max
STANDBY Mode

8

2 µA max

0.5 µA typ

Power Dissipation

Normal Mode (Operational) mW max
NAP Mode 3 mW max
STANDBY Mode

NOTES

1

Temperature ranges as follows: –40°C to +85°C.

2

SINAD figures quoted include external analog input circuit noise contribution of approximately 1 dB.

3

See Typical Performance Characteristics section for analog input circuits used.

4

See Terminology.

5

Sample tested @ 25°C to ensure compliance.

6

Current drawn from external reference during conversion.

7

I

= 200 µA.

LOAD

8

Digital input levels at GND or V

Specifications subject to change without notice.

8

.

DRIVE

10 µW max

AD7485

TIMING CHARACTERISTICS

(VDD = 5 V  5%, AGND = DGND = 0 V, V

1

valid for V

= 2.7 V to 5.25 V, unless otherwise noted.)

DRIVE

= External; all specifications T

REF

MIN

to T

MAX

and

Parameter Symbol Min Typ Max Unit

Master Clock Frequency f
MCLK Period t
Conversion Time t

CONVST Low Period (Mode 1)
CONVST High Period (Mode 1)

2

2

MCLK High Period t
MCLK Low Period t
CONVST Falling Edge to MCLK Rising Edge t
MCLK Rising Edge to MSB Valid t
Data Valid before SCO Falling Edge t
Data Valid after SCO Falling Edge t

CONVST Rising Edge to SDO Three-State t
CONVST Low Period (Mode 2)
CONVST High Period (Mode 2)

2

3

CONVST Falling Edge to TFS Falling Edge t
TFS Falling Edge to MSB Valid t
TFS Rising Edge to SDO Three-State t
TFS Low Period
TFS High Period

4

4

MCLK Fall Time t
MCLK Rise Time t
MCLK – SCO Delay t

NOTES

1

All timing specifications given above are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used.

2

CONVST idling high. See Serial Interface section for further details.

3

CONVST idling low. See Serial Interface section for further details.

4

TFS can also be tied low in this mode.

Specifications subject to change without notice.

MCLK

1

2

t

3

t

4

5

6

7

8

9

10

11

t

12

t

13

14

15

16

t

17

t

18

19

20

21

0.01 25 MHz
40 100000 ns
t1  24 ns
t1  22 ns
10 ns

0.4  t

0.4  t

1

1

0.6  t

0.6  t

1

1

ns
ns

7ns

15 ns
10 ns
20 ns

6ns
10 t1  2ns
10 ns
10 ns

30 ns

8ns
t1  22 ns
10 ns
525ns
525ns
625ns

REV.

–3–

AD7485

A

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C, unless otherwise noted.)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DRIVE

Analog Input Voltage to GND . . . . . . –0.3 V to AV

Digital Input Voltage to GND . . . . . –0.3 V to V

REFIN to GND . . . . . . . . . . . . . . . . –0.3 V to AV

DD

DRIVE

DD

+ 0.3 V
+ 0.3 V

+ 0.3 V

Input Current to Any Pin except Supplies . . . . . . . . . ±10 mA

Operating Temperature Range

Commercial . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 50°C/W



Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 10°C/W

JC

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although the AD7485
features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to
high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.

PIN CONFIGURATION

AGND

AGND

AVDDDVDDDGND

DGND

RESET

CONVST

SCO

DGND

DGND

SDO

DGND

DGND

DGND

36

35

34

33

32

31

30

29

28

27

26

25

DGND

SMODE

TFS

DGND

DGND

V

DRIVE

DGND

DGND

DV

DD

DGND

DGND

DGND

DGND

AV

C

BIAS

AGND

AGND

AV

AGND

VIN

REFOUT

REFIN

REFSEL

AGND

AGND

48 47 46 45 44 39 38 3743 42 41 40

1

DD

PIN 1

2

IDENTIFIER

3

4

5

DD

6

7

8

9

10

11

12

13 14 15 16 17 18 19 20 21 22 23 24

DD

AV

AGND

AGND

AD7485

TOP VIEW

(Not to Scale)

NAP

STBY

MCLK

DGND

DGND

WARNING!

ESD SENSITIVE DEVICE

REV. –4–

AD7485

A

PIN FUNCTION DESCRIPTIONS

Pin
No. Mnemonic Description

1, 5, 13, 46 AV
2C

DD

BIAS

3, 4, 6, 11, 12, AGND Power Supply Ground for Analog Circuitry
14, 15, 47, 48

7VIN Analog Input. Single-ended analog input channel.
8 REFOUT Reference Output. REFOUT connects to the output of the internal 2.5 V reference buffer. A 470 nF

9 REFIN Reference Input. A 470 nF capacitor must be placed between this pin and AGND. When using

10 REFSEL Reference Decoupling Pin. When using the internal reference, a 1 nF capacitor must be connected

16 STBY Standby Logic Input. When this pin is logic high, the device will be placed in STANDBY mode.

17 NAP Nap Logic Input. When this pin is logic high, the device will be placed in a very low power mode.

18 MCLK

19, 20, 22–28 DGND Ground Reference for Digital Circuitry
30, 31, 33, 34
37–39, 43, 44

21 SDO Serial Data Output. The conversion data is latched out on this pin on the rising edge of SCO. It

29, 45 DV
32 V

DD

DRIVE

35 TFS Transmit Frame Sync Input. In Serial Mode 2, this pin acts as a framing signal for the serial data

36 SMODE Serial Mode Input. A logic low on this pin selects Serial Mode 1 and a logic high selects Serial

40 SCO Serial Clock Output. This clock is derived from MCLK and is used to latch conversion data from

41 CONVST

42 RESET Reset Logic Input. A falling edge on this pin resets the internal state machine and terminates a

Positive Power Supply for Analog Circuitry
Decoupling Pin for Internal Bias Voltage. A 1 nF capacitor should be placed between this pin

and AGND.

capacitor must be placed between this pin and AGND.

an external voltage reference source, the reference voltage should be applied to this pin.

from this pin to AGND. When using an external reference source, this pin should be connected
directly to AGND.

See the Power Saving section for further details.

See the Power Saving section for further details.
Master Clock Input. This is the input for the master clock, which controls the conversion cycle. The fre-

quency of this clock may be up to 25 MHz. Twenty-four clock cycles are required for each conversion.

should be latched into the receiving serial port of the DSP on the falling edge of SCO. The over­range bit is latched out first, then 14 bits of data (MSB first) followed by a trailing zero.

Positive Power Supply for Digital Circuitry
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface

logic of the AD7485 will operate.

being clocked out on SDO. A falling edge on TFS brings SDO out of three-state and the data starts
to get clocked out on the next rising edge of SCO.

Mode 2. See the Serial Interface section for further details.

the device. See the Serial Interface section for further details.
Convert Start Logic Input. A conversion is initiated on the falling edge of the CONVST signal. The

input track/hold amplifier goes from track mode to hold mode and the conversion process commences.

conversion that may be in progress. Holding this pin low keeps the part in a reset state.

REV.

–5–