Analog Devices AD7482 Datasheet

a

3 MSPS, 12-Bit SAR ADC

AD7482

FEATURES
Fast Throughput Rate: 3 MSPS
Wide Input Bandwidth: 40 MHz
No Pipeline Delays with SAR ADC
Excellent DC Accuracy Performance
Two Parallel Interface Modes
Low Power:

90 mW (Full Power) and 2.5 mW (NAP Mode)
Standby Mode: 2 ␮A Max
Single 5 V Supply Operation
Internal 2.5 V Reference
Full-Scale Overrange Mode (using 13th Bit)
System Offset Removal via User Access Offset Register
Nominal 0 V to 2.5 V Input with Shifted Range

Capability
14-Bit Pin Compatible Upgrade AD7484 Available

GENERAL DESCRIPTION

The AD7482 is a 12-bit, high speed, low power, successive­approximation ADC. The part features a parallel interface with
throughput rates up to 3 MSPS. The part contains a low noise,
wide bandwidth track-and-hold that can handle input fre­quencies in excess of 40 MHz.

The conversion process is a proprietary algorithmic successive­approximation technique that results in no pipeline delays. The
input signal is sampled, and a conversion is initiated on the
falling edge of the CONVST signal. The conversion process is
controlled via an internally trimmed oscillator. Interfacing is via
standard parallel signal lines, making the part directly compat­ible with microcontrollers and DSPs.

The AD7482 provides excellent ac and dc performance specifi­cations. Factory trimming ensures high dc accuracy resulting in
very low INL, offset, and gain errors.

The part uses advanced design techniques to achieve very low
power dissipation at high throughput rates. Power consumption
in the normal mode of operation is 90 mW. There are two power­saving modes: a NAP Mode that keeps the reference circuitry alive
for a quick power-up while consuming 2.5 mW, and a STANDBY
Mode that reduces power consumption to a mere 10 µW.

FUNCTIONAL BLOCK DIAGRAM

AV

REFSEL

VIN

AGND C

DD

2.5 V

REFERENCE

T/H

BIASDVDD

BUF

12-BIT

ALGORITHMIC SAR

V

DRIVE

DGND

REFOUT

REFIN

AD7482

MODE1

MODE2

CLIP

NAP

STBY

RESET

CONVST

CONTROL

LOGIC AND I/O

REGISTERS

D0

CS

RD

BUSY

WRITE

D1

D2

D3

D4

D12

D11
D10
D9
D8
D7
D6
D5

The AD7482 features an on-board 2.5 V reference but can also
accommodate an externally provided 2.5 V reference source. The
nominal analog input range is 0 V to 2.5 V, but an offset shift
capability allows this nominal range to be offset by ±200 mV.
This allows the user considerable flexibility in setting the bottom
end reference point of the signal range, a useful feature when
using single-supply op amps.

The AD7482 also provides the user with an 8% overrange
capability via a 13th bit. Thus, if the analog input range strays
outside the nominal by up to 8%, the user can still accurately
resolve the signal by using the 13th bit.

The AD7482 is powered by a 4.75 V to 5.25 V supply. The part
also provides a V
levels for the digital interface lines. The range for this V

Pin that allows the user to set the voltage

DRIVE

DRIVE

Pin
is 2.7 V to 5.25 V. The part is housed in a 48-lead LQFP package
and is specified over a –40°C to +85°C temperature range.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

AD7482–SPECIFICATIONS

(VDD = 5 V ± 5%, AGND = DGND = 0 V, V

1

cations T

MIN

to T

MAX

and valid for V

DRIVE

= External, f

REF

= 3 MSPS; all specifi-

SAMPLE

= 2.7 V to 5.25 V, unless otherwise noted.)

Parameter Specification Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal-to-Noise + Distortion (SINAD)

2, 3

4

71 dB min FIN = 1 MHz
72 dB typ FIN = 1 MHz

Total Harmonic Distortion (THD)

4

71 dB typ F
–86 dB max

= 1 MHz, Internal Reference

IN

–90 dB typ
–88 dB typ Internal Reference

4

Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)

4

Second Order Terms –96 dB typ F

–87 dB max

= 95.053 kHz, F

IN1

= 105.329 kHz

IN2

Third Order Terms –94 dB typ
Aperture Delay 10 ns typ
Full-Power Bandwidth 40 MHz typ @ 3 dB

3.5 MHz typ @ 0.1 dB

DC ACCURACY

Resolution 12 Bits
Integral Nonlinearity

4

± 0.5 LSB max B Grade
± 1 LSB max A Grade
± 0.25 LSB typ
± 0.5 LSB max Guaranteed No Missed Codes to 12 Bits
± 0.25 LSB typ
± 1.5 LSB max

0.036 %FSR max
± 1.5 LSB max

Differential Nonlinearity

Offset Error

Gain Error

4

4

4

0.036 %FSR max

ANALOG INPUT

Input Voltage –200 mV min

+2.7 V max

DC Leakage Current ± 1 µA max V

± 2 µA typ V
35 pF typ

Input Capacitance

5

from 0 V to 2.7 V

IN

= –200 mV

IN

REFERENCE INPUT/OUTPUT

Input Voltage +2.5 V ± 1% for Specified Performance

V

REFIN

V

Input DC Leakage Current ± 1 µA max

REFIN

Input Capacitance

V

REFIN

Input Current 220 µA typ External Reference

V

REFIN

V
V
V
V

Output Voltage +2.5 V typ

REFOUT

Error @ 25°C ± 50 mV typ

REFOUT

Error T

REFOUT

Output Impedance 1 Ω typ

REFOUT

MIN

to T

5

MAX

25 pF typ

± 100 mV max

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

INL

IN

IN

INH

5

V

–1V min

DRIVE

0.4 V max
± 1 µA max
10 pF max

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current ±10 µA max
Floating-State Output Capacitance

OH

OL

5

0.7 × V

DRIVE

0.3 × V

DRIVE

10 pF max

V min
V max

Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 300 ns max
Track-and-Hold Acquisition Time(t

)70 ns max Sine Wave Input

ACQ

70 ns max Full-Scale Step Input

Throughput Rate 2.5 MSPS max Parallel Mode 1

3MSPS max Parallel Mode 2

REV. 0–2–

AD7482

SPECIFICATIONS

(continued)

(VDD = 5 V ± 5%, AGND = DGND = 0 V, V
to T

and valid for V

MAX

= 2.7 V to 5.25 V, unless otherwise noted.)

DRIVE

= External, f

REF

= 3 MSPS; all specifications T

SAMPLE

Parameter Specification Unit Test Conditions/Comments

POWER REQUIREMENTS

V

DD

V

DRIVE

5V± 5%

2.7 V min

5.25 V max

I

DD

Normal Mode (Static) 12 mA max CS and RD = Logic 1
Normal Mode (Operational) 18 mA max
NAP Mode 0.5 mA max
Standby Mode 2 µA max

0.5 µA typ

Power Dissipation

Normal Mode (Operational) 90 mW max
NAP Mode 2.5 mW max
Standby Mode

NOTES

1

Temperature range is as follows: –40°C to +85°C.

2

SNR and SINAD figures quoted include external analog input circuit noise contribution of approximately 1 dB.

3

See Typical Performance Characteristics section for analog input circuits used.

4

See Terminology section.

5

Sample tested @ 25°C to ensure compliance.

6

Digital input levels at GND or V

Specifications subject to change without notice.

6

.

DRIVE

10 µW max

MIN

TIMING CHARACTERISTICS

(VDD = 5 V ± 5%, AGND = DGND = 0 V, V

*

V

= 2.7 V to 5.25 V, unless otherwise noted.)

DRIVE

= External; all specifications T

REF

MIN

to T

and valid for

MAX

Parameter Symbol Min Typ Max Unit

DATA READ

Conversion Time t
Quiet Time before Conversion Start t

CONVST Pulsewidth t
CONVST Falling Edge to BUSY Falling Edge t
CS Falling Edge to RD Falling Edge t

Data Access Time t

CONVST Falling Edge to New Data Valid t
BUSY Rising Edge to New Data Valid t

Bus Relinquish Time t

RD Rising Edge to CS Rising Edge t
CS Pulsewidth t
RD Pulsewidth t

CONV

QUIET

1

2

3

4

5

6

7

8

14

15

100 ns
5ns

0ns

10 ns
0ns
30 ns
30 ns

300 ns

20 ns

25 ns
30 ns
5ns

DATA WRITE

WRITE Pulsewidth t
Data Setup Time t
Data Hold Time t
CS Falling Edge to WRITE Falling Edge t
WRITE Falling Edge to CS Rising Edge t

*All timing specifications given above are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used.

Specifications subject to change without notice.

9

10

11

12

13

5ns
2ns
6ns
5ns
0ns

REV. 0

–3–

AD7482

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C, unless otherwise noted.)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DRIVE

Analog Input Voltage to GND . . . . . –0.3 V to AV

Digital Input Voltage to GND . . . . . –0.3 V to V

REFIN to GND . . . . . . . . . . . . . . . . –0.3 V to AV

DD

DRIVE

DD

+ 0.3 V
+ 0.3 V

+ 0.3 V

Input Current to Any Pin except Supplies . . . . . . . . . ±10 mA

Operating Temperature Range

Commercial . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

PIN CONFIGURATION

AGND

AGND

AVDDCLIP

48 47 46 45 44 39 38 3743 42 41 40

1

AV

DD

PIN 1

2

C

BIAS

AGND

AGND

AV

AGND

VIN

REFOUT

REFIN

REFSEL

AGND

AGND

IDENTIFIER

3

4

5

DD

6

7

8

9

10

11

12

13 14 15 16 17 18 19 20 21 22 23 24

DD

AV

AGND

AGND

AD7482

TOP VIEW

(Not to Scale)

STBY

␪JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 50°C/W

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 10°C/W

␪

JC

Lead Temperature, Soldering

Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

MODE1

MODE2

RESET

CONVST

D12

D11

D10

D9

36

D8

35

D7

34

D6

33

D5

32

V

DRIVE

31

DGND

30

DGND

29

DV

DD

28

D4

27

D3

26

D2

25

D1

RD

BUSY

WRITE

R1R2D0

NAP

CS

ORDERING GUIDE

Model Temperature Range Integral Nonlinearity (INL) Package Options

AD7482AST –40°C to +85°C ±1 LSB Max ST-48 (LQFP)
AD7482BST –40°C to +85°C ±0.5 LSB Max ST-48 (LQFP)
EVAL-AD7482CB
EVAL-CONTROL BRD2

NOTES

1

This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.

2

This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

1

2

Evaluation Board
Controller Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the

WARNING!

AD7482 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

ESD SENSITIVE DEVICE

REV. 0–4–

AD7482

PIN FUNCTION DESCRIPTIONS

Pin
Number Mnemonic Description

1, 5, 13, 46 AV
2C

DD

BIAS

3, 4, 6, 11, 12, AGND Power Supply Ground for Analog Circuitry
14, 15, 47, 48
7VIN Analog Input. Single-ended analog input channel.
8 REFOUT Reference Output. REFOUT connects to the output of the internal 2.5 V reference buffer. A 470 nF

9 REFIN Reference Input. A 470 nF capacitor must be placed between this pin and AGND. When using an

10 REFSEL Reference Decoupling Pin. When using the internal reference, a 1 nF capacitor must be connected

16 STBY Standby Logic Input. When this pin is logic high, the device will be placed in Standby Mode.

17 NAP NAP Logic Input. When this pin is logic high, the device will be placed in a very low power mode.

18 CS Chip Select Logic Input. This pin is used in conjunction with RD to access the conversion result.

19 RD Read Logic Input. Used in conjunction with CS to access the conversion result.
20 WRITE Write Logic Input. Used in conjunction with CS to write data to the offset register. When the

21 BUSY Busy Logic Output. This pin indicates the status of the conversion process. The BUSY signal goes

22, 23 R1, R2 These pins should be pulled to ground via 100 kΩ resistors.
24–28, 33–39 D0–D11 Data I/O Bits (D11 is MSB). These are three-state pins that are controlled by CS, RD, and

29 DV

DD

30, 31 DGND Ground Reference for Digital Circuitry
32 V

DRIVE

40 D12 Data Output Bit for Overranging. If the overrange feature is not used, this pin should be pulled to

41 CONVST Convert Start Logic Input. A conversion is initiated on the falling edge of the CONVST signal.

42 RESET Reset Logic Input. A falling edge on this pin resets the internal state machine and terminates a

43 MODE2 Operating Mode Logic Input. See Table III for details.
44 MODE1 Operating Mode Logic Input. See Table III for details.
45 CLIP Logic Input. A logic high on this pin enables output clipping. In this mode, any input voltage that

Positive Power Supply for Analog Circuitry
Decoupling Pin for Internal Bias Voltage. A 1 nF capacitor should be placed between this pin

and AGND.

capacitor must be placed between this pin and AGND.

external voltage reference source, the reference voltage should be applied to this pin.

from this pin to AGND. When using an external reference source, this pin should be connected
directly to AGND.

See Power Saving section for further details.

See Power Saving section for further details.

The databus is brought out of three-state and the current contents of the output register driven
onto the data lines following the falling edge of both CS and RD. CS is also used in conjunction
with WRITE to perform a write to the offset register. CS can be hardwired permanently low.

desired offset word has been placed on the databus, the WRITE line should be pulsed high. It is
the falling edge of this pulse that latches the word into the offset register.

low after the falling edge of CONVST and stays low for the duration of the conversion. In Parallel
Mode 1, the BUSY signal returns high when the conversion result has been latched into the output
register. In Parallel Mode 2, the BUSY signal returns high as soon as the conversion has been
completed, but the conversion result does not get latched into the output register until the falling
edge of the next CONVST pulse.

WRITE. The operating voltage level for these pins is determined by the V

DRIVE

input.

Positive Power Supply for Digital Circuitry

Logic Power Supply Input. The voltage supplied at this pin will determine at what voltage the
interface logic of the device will operate.

DGND via a 100 kΩ resistor.

The input track-and-hold amplifier goes from track mode to hold mode and the conversion process
commences.

conversion that may be in progress. The contents of the offset register will also be cleared on this
edge. Holding this pin low keeps the part in a reset state.

is greater than positive full scale or less than negative full scale will be clipped to all “1s” or all “0s,”
respectively. Further details are given in the Offset/Overrange section.

REV. 0

–5–