ANALOG DEVICES AD7478 Service Manual

V

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1 MSPS, 12-/10-/8-Bit ADCs

FEATURES

Fast throughput rate: 1 MSPS Specified for V Low power

3.6 mW typical at 1 MSPS with 3 V supplies 15 mW typical at 1 MSPS with 5 V supplies

Wide input bandwidth

70 dB SNR at 100 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface

SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible Standby mode: 1 μA maximum 6-lead SOT-23 package

APPLICATIONS

Battery-powered systems

Personal digital assistants

Medical instruments

Mobile communications Instrumentation and control systems Data acquisition systems High speed modems Optical sensors

of 2.35 V to 5.25 V

DD

in 6-Lead SOT-23

AD7476/AD7477/AD7478

FUNCTIONAL BLOCK DIAGRAM

DD

12-/10-/8-BIT

IN

SUCCESSIVE-

APPROXIMATION

ADC

CONTROL

LOGIC

AD7476/AD7477/AD7478

GND

Figure 1.

SCLK

SDATA

CS

01024-001

GENERAL DESCRIPTION

The AD7476/AD7477/AD74781 are, respectively, 12-bit, 10-bit, and 8-bit, high speed, low power, successive approximation ADCs. The parts operate from a single 2.35 V to 5.25 V power supply and feature throughput rates up to 1 MSPS. Each part contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 6 MHz.

The conversion process and data acquisition are controlled

CS

usin with microprocessors or DSPs. The input signal is sampled on the falling edge of point. There are no pipeline delays associated with these parts.

The AD7476/AD7477/AD7478 use advanced design techniques

o achieve very low power dissipation at high throughput rates.

t The reference for the parts is taken internally from V allows the widest dynamic input range to the ADC. Thus, the analog input range for the parts are 0 V to V rate is determined by the SCLK.

1

Protected by U.S. Patent No. 6,681,332.

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

and the serial clock, allowing the devices to interface

g

CS

and the conversion is initiated at this

. The conversion

DD

. This

PRODUCT HIGHLIGHTS

1. First 12-/10-/8-Bit ADCs in SOT-23 Packages.

2. H

igh Throughput with Low Power Consumption.

lexible Power/Serial Clock Speed Management. The

3. F

conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. This allows the average power consumption to be reduced while not converting. The parts also feature a shutdown mode to maximize power efficiency at lower throughput rates. Current consumption is 1 A maximum when in shutdown mode.

4. Refer

5. N

ence Derived from the Power Supply.

o Pipeline Delay. The parts feature a standard successiveapproximation ADC with accurate control of the sampling instant via a

CS

input and once-off conversion control.

AD7476/AD7477/AD7478

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REVISION HISTORY

4/06—Rev. D to Rev. E

Updated Format..................................................................Universal

hanges to Table 1 Endnotes .......................................................... 3

C

Changes to Table 2 Endnotes .......................................................... 5

Changes to Table 3 Endnotes .......................................................... 7

Updated Outline Dimensions....................................................... 21

Changes to Ordering Guide.......................................................... 22

3/04—Rev. C to Rev. D

Added U.S. Patent Number ............................................................. 1

hanges to Specifications................................................................ 2

C

Changes to Absolute Maximum Ratings....................................... 6

Changes to AD7476/AD7477/AD7478 to ADSP-21xx

Interface section.............................................................................. 16

2/03—Rev. B to Rev. C

hanges to General Description .................................................... 1

C

Changes to Specifications................................................................ 2

Changes to Absolute Maximum Ratings....................................... 6

Changes to Ordering Guide............................................................ 6

Changes to Typical Connection Diagram section ..................... 10

Changes to Figure 8 caption.......................................................... 11

Changes to Figure 19...................................................................... 16

Changes to Figure 20...................................................................... 17

Updated Outline Dimensions....................................................... 18

Rev. E | Page 2 of 24

AD7476/AD7477/AD7478

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SPECIFICATIONS

AD7476 SPECIFICATIONS

A version: VDD = 2.7 V to 5.25 V, f f

= 12 MHz, f

SCLK

= 600 kSPS, unless otherwise noted; TA = T

SAMPLE

Table 1.

Parameter A Version

DYNAMIC PERFORMANCE fIN = 100 kHz sine wave

Signal-to-(Noise + Distortion) (SINAD)3 69 70 69 dB min B version, VDD = 2.4 V to 5.25 V

70 70 dB min TA = 25°C

71.5 dB typ Signal-to-Noise Ratio (SNR)3 70 71 70 dB min B version, VDD = 2.4 V to 5.25 V

72.5 dB typ Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR)3−82 −80 −80 dB typ Intermodulation Distortion (IMD)

Second-Order Terms −78 −78 −78 dB typ fa = 103.5 kHz, fb = 113.5 kHz

Third-Order Terms −78 −78 −78 dB typ fa = 103.5 kHz, fb = 113.5 kHz Aperture Delay 10 10 10 ns typ Aperture Jitter 30 30 30 ps typ Full Power Bandwidth 6.5 6.5 6.5 MHz typ @ 3 dB

DC ACCURACY S, B versions, VDD = (2.35 V to 3.6 V)4; A version, VDD = (2.7 V to 3.6 V)

Resolution 12 12 12 Bits Integral Nonlinearity3 ±1.5 ±1.5 LSB max ±1 ±0.6 ±0.6 LSB typ Differential Nonlinearity3 −0.9/+1.5 −0.9/+1.5 LSB max Guaranteed no missed codes to 12 bits ±0.75 ±0.75 ±0.75 LSB typ Offset Error3 ±1.5 ±2 LSB max ±0.5 LSB typ Gain Error3 ±1.5 ±2 LSB max

±0.5 LSB typ ANALOG INPUT

Input Voltage Ranges 0 to VDD 0 to VDD 0 to VDD V DC Leakage Current ±1 ±1 ±1 μA max Input Capacitance 30 30 30 pF typ

LOGIC INPUT

Input High Voltage, V

1.8 1.8 1.8 V min VDD = 2.35 V Input Low Voltage, V

0.8 0.8 0.8 V max VDD = 5 V Input Current, IIN, SCLK Pin ±1 ±1 ±1 μA max Typically 10 nA, VIN = 0 V or VDD Input Current, IIN, CS Pin Input Capacitance, C

2.4 2.4 2.4 V min

INH

0.4 0.4 0.4 V max VDD = 3 V

INL

5

10 10 10 pF max

IN

= 20 MHz, f

SCLK

3

= 1 MSPS, unless otherwise noted; S and B versions: VDD = 2.35 V to 5.25 V,

SAMPLE

to T

MIN

1, 2

B Version

−80 −78 −78 dB typ

±1 ±1 ±1 μA typ

1,2

, unless otherwise noted.

MAX

S Version

1,2

Unit Test Conditions/Comments

Rev. E | Page 3 of 24

AD7476/AD7477/AD7478

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Parameter A Version

1, 2

B Version

1,2

S Version

1,2

Unit Test Conditions/Comments

LOGIC OUTPUT

Output High Voltage, VOH VDD − 0.2 VDD − 0.2 VDD − 0.2 V min I Output Low Voltage, VOL 0.4 0.4 0.4 V max I

= 200 μA; VDD = 2.35 V to 5.25 V

SOURCE

= 200 μA

SINK

Floating-State Leakage Current ±10 ±10 ±10 μA max Floating-State Output Capacitance5 10 10 10 pF max Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 0.8 1.33 1.33 μs max 16 SCLK cycles Track-and-Hold Acquisition Time 500 500 500 ns max Full-scale step input 350 400 400 ns max Sine wave input ≤ 100 kHz Throughput Rate 1000 600 600 kSPS max See Serial Interface section

POWER REQUIREMENTS

VDD 2.35/5.25 2.35/5.25 2.35/5.25 V min/max IDD Digital I/Ps = 0 V or VDD

Normal Mode (Static) 2 2 2 mA typ VDD = 4.75 V to 5.25 V, SCLK on or off 1 1 1 mA typ VDD = 2.35 V to 3.6 V, SCLK on or off Normal Mode (Operational) 3.5 3 3 mA max

1.6 1.4 1.4 mA max

= 4.75 V to 5.25 V,

V

DD

f

= f

V

SAMPLE

DD

f

SAMPLE

= 2.35 V to 3.6 V,

= f

SAMPLE

MAX6

Full Power-Down Mode 1 1 1 μA max SCLK off

80 80 80 μA max SCLK on Power Dissipation7

Normal Mode (Operational) 17.5 15 15 mW max VDD = 5 V, f

4.8 4.2 4.2 mW max VDD = 3 V, f

SAMPLE

= f = f

SAMPLE

MAX6 MAX6

Full Power-Down 5 5 5 μW max VDD = 5 V, SCLK off

3 3 3 μW max VDD = 3 V, SCLK off

1

Temperature range for A and B versions is −40°C to +85°C; temperature range for S version is −55°C to +125°C.

2

Operational from VDD = 2.0 V.

3

See the Terminology section.

4

Maximum B and S version specifications apply as typical figures when VDD = 5.25 V.

5

Guaranteed by characterization.

6

For A version: f

7

See the Power vs. Throughput Rate section.

MAX = 1 MSPS; B and S versions: f

SAMPLE

MAX = 600 kSPS.

SAMPLE

Rev. E | Page 4 of 24

AD7476/AD7477/AD7478

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AD7477 SPECIFICATIONS

VDD = 2.7 V to 5.25 V, f

Table 2.

Parameter A Version

DYNAMIC PERFORMANCE fIN = 100 kHz sine wave, f

Signal-to-(Noise + Distortion) (SINAD) 61 61 dB min Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR)3 −74 −74 dB max Intermodulation Distortion (IMD)3

Second-Order Terms −78 −78 dB typ fa = 103.5 kHz, fb = 113.5 kHz

Third-Order Terms −78 −78 dB typ fa = 103.5 kHz, fb = 113.5 kHz Aperture Delay 10 10 ns typ Aperture Jitter 30 30 ps typ Full Power Bandwidth 6.5 6.5 MHz typ @ 3 dB

DC ACCURACY

Resolution 10 10 Bits Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error

3

ANALOG INPUT

Input Voltage Ranges 0 to VDD 0 to VDD V DC Leakage Current ±1 ±1 μA max Input Capacitance 30 30 pF typ

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V

0.4 0.4 V max VDD = 3 V Input Current, IIN, SCLK Pin ±1 ±1 μA max Typically 10 nA, VIN = 0 V or VDD Input Current, IIN, CS Pin Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, VOH VDD – 0.2 VDD – 0.2 V min I Output Low Voltage, VOL 0.4 0.4 V max I Floating-State Leakage Current ±10 ±10 μA max Floating-State Output Capacitance4 10 10 pF max Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 800 800 ns max 16 SCLK cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time 400 400 ns max Throughput Rate 1 1 MSPS max See Serial Interface section

= 20 MHz, TA = T

SCLK

3

MIN

to T

, unless otherwise noted.

MAX

1, 2

S Version

1,2

Unit Test Conditions/Comments

−73 −73 dB max

±1 ±1 LSB max ±0.9 ±0.9 LSB max Guaranteed no missed codes to 10 bits ±1 ±1 LSB max ±1 ±1 LSB max

2.4 2.4 V min

INH

0.8 0.8 V max VDD = 5 V

INL

±1 ±1 μA typ

4

IN

10 10 pF max

SOURCE

= 200 μA

SINK

= 1 MSPS

SAMPLE

= 200 μA, VDD = 2.7 V to 5.25 V

Rev. E | Page 5 of 24

AD7476/AD7477/AD7478

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Parameter A Version

1, 2

S Version

1,2

Unit Test Conditions/Comments

POWER REQUIREMENTS

VDD 2.7/5.25 2.7/5.25 V min/max IDD Digital I/Ps = 0 V or VDD

Normal Mode (Static) 2 2 mA typ VDD = 4.75 V to 5.25 V; SCLK on or off 1 1 mA typ VDD = 2.7 V to 3.6 V; SCLK on or off Normal Mode (Operational) 3.5 3.5 mA max VDD = 4.75 V to 5.25 V; f

1.6 1.6 mA max VDD = 2.7 V to 3.6 V; f

SAMPLE

= 1 MSPS Full Power-Down Mode 1 1 μA max SCLK off 80 80 μA max SCLK on Power Dissipation5

Normal Mode (Operational) 17.5 17.5 mW max VDD = 5 V; f

4.8 4.8 mW max VDD = 3 V; f

SAMPLE

= 1 MSPS = 1 MSPS

Full Power-Down 5 5 μW max VDD = 5 V; SCLK off

1

Temperature range for A version is −40°C to +85°C; temperature range for S version is −55°C to +125°C.

2

Operational from VDD = 2.0 V, with input high voltage, V

3

See the Terminology section.

4

Guaranteed by characterization.

5

See the Power vs. Throughput Rate section.

= 1.8 V minimum.

INH

= 1 MSPS

Rev. E | Page 6 of 24

AD7476/AD7477/AD7478

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AD7478 SPECIFICATIONS

VDD = 2.7 V to 5.25 V, f

Table 3.

Parameter A Version

DYNAMIC PERFORMANCE fIN = 100 kHz sine wave, f

Signal-to-(Noise + Distortion) (SINAD) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) Intermodulation Distortion (IMD)

Second-Order Terms −68 −68 dB typ fa = 498.7 kHz, fb = 508.7 kHz

Third-Order Terms −68 −68 dB typ fa = 498.7 kHz, fb = 508.7 kHz Aperture Delay 10 10 ns typ Aperture Jitter 30 30 ps typ Full Power Bandwidth 6.5 6.5 MHz typ @ 3 dB

DC ACCURACY

Resolution 8 8 Bits Integral Nonlinearity Differential Nonlinearity Offset Error ±0.5 ±0.5 LSB max Gain Error ±0.5 ±0.5 LSB max Total Unadjusted Error (TUE) ±0.5 ±0.5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to VDD 0 to VDD V DC Leakage Current ±1 ±1 μA max Input Capacitance 30 30 pF typ

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V

0.4 0.4 V max VDD = 3 V Input Current, IIN, SCLK Pin ±1 ±1 μA max Typically 10 nA, VIN = 0 V or VDD Input Current, IIN, CS Pin Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, VOH VDD − 0.2 VDD − 0.2 V min I Output Low Voltage, VOL 0.4 0.4 V max I Floating-State Leakage Current ±10 ±10 μA max Floating-State Output Capacitance4 10 10 pF max Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 800 800 ns max 16 SCLK cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time 400 400 ns max Throughput Rate 1 1 MSPS max See Serial Interface section

POWER REQUIREMENTS

VDD 2.7/5.25 2.7/5.25 V min/max IDD Digital I/Ps = 0 V or VDD

Normal Mode (Static) 2 2 mA typ VDD = 4.75 V to 5.25 V, SCLK on or off

1 1 mA typ VDD = 2.7 V to 3.6 V, SCLK on or off

Normal Mode (Operational) 3.5 3.5 mA max VDD = 4.75 V to 5.25 V, f

1.6 1.6 mA max VDD = 2.7 V to 3.6 V, f

Full Power-Down Mode 1 1 μA max SCLK off

80 80 μA max SCLK on

= 20 MHz, TA = T

SCLK

3

2.4 2.4 V min

INH

0.8 0.8 V max VDD = 5 V

INL

to T

MIN

3

, unless otherwise noted.

MAX

1, 2

S Version

1,2

Unit Test Conditions/Comments

49 49 dB min

−65 −65 dB max

3

−65 −65 dB max

±0.5 ±0.5 LSB max ±0.5 ±0.5 LSB max Guaranteed no missed codes to eight bits

±1 ±1 μA typ

4

10 10 pF max

IN

SOURCE

SINK

Rev. E | Page 7 of 24

= 1 MSPS

SAMPLE

= 200 μA, VDD = 2.7 V to 5.25 V

= 200 μA

= 1 MSPS

SAMPLE

= 1 MSPS

SAMPLE

AD7476/AD7477/AD7478

V

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Parameter A Version

Power Dissipation

5

1, 2

S Version

Normal Mode (Operational) 17.5 17.5 mW max VDD = 5 V, f

4.8 4.8 mW max VDD = 3 V, f

1,2

Unit Test Conditions/Comments

= 1 MSPS

SAMPLE

= 1 MSPS

SAMPLE

Full Power-Down 5 5 μW max VDD = 5 V, SCLK off

1

Temperature range for A version is −40°C to +85°C; temperature range for S version is −55°C to +125°C.

2

Operational from VDD = 2.0 V, with input high voltage, V

3

See the Terminology section.

4

Guaranteed by characterization.

5

See the Power vs. Throughput Rate section.

= 1.8 V minimum.

INH

TIMING SPECIFICATIONS

VDD = 2.35 V to 5.25 V, TA = T

Table 4.

Limit at T Parameter

f

SCLK

2, 3

4

3 V 5 V Unit Description

10 10 kHz min

20 20

12 12

t

16 × t

CONVER T

t

50 50 ns min Minimum quiet time required between bus relinquish and start of next conversion

QUIET

SCLK

t1 10 10 ns min t2 10 10 ns min

5

t

3

5

t

4

20 20 ns max

40 20 ns max Data access time after SCLK falling edge, A version 70 20 ns max Data access time after SCLK falling edge, B version t5

t6

0.4 ×

t

SCLK

0.4 ×

t

SCLK

t7 10 10 ns min SCLK to data valid hold time

6

t

10 10 ns min SCLK falling edge to SDATA high impedance

8

25 25 ns max SCLK falling edge to SDATA high impedance

7

t

1

3 V specifications apply from VDD = 2.7 V to 3.6 V for A version; 3 V specifications apply from VDD = 2.35 V to 3.6 V for B version; 5 V specifications apply from

2

Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

3

Version A timing specifications apply to the AD7477 and AD7478 S version; B version timing specifications apply to the AD7476 S version.

4

Mark/space ratio for the SCLK input is 40/60 to 60/40.

5

Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.

6

t8 is derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated to

7

See Power-Up Time section.

1 1 μs typ Power-up time from full power-down

POWER-UP

VDD = 4.75 V to 5.25 V.

remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t loading.

MIN

, T

MIN

16 × t

0.4 × t

SCLK

0.4 × t

SCLK

to T

MAX

, unless otherwise noted.

MAX

1

MHz max

SCLK

ns min SCLK low pulsewidth

ns min SCLK high pulsewidth

A version

B version

Minimum CS

to SCLK setup time

CS Delay from CS

pulsewidth

until SDATA three-state disabled

, is the true bus relinquish time of the part and is independent of the bus

8

200µA I

TO OUTPUT

C

L

50pF

200µA I

Figure 2. Load Circuit for Digital Out

Rev. E | Page 8 of 24

OL

1.6

OH

01024-002

put Timing Specifications

ANALOG DEVICES AD7478 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

AD7476 SPECIFICATIONS

AD7477 SPECIFICATIONS

AD7478 SPECIFICATIONS

TIMING SPECIFICATIONS