Analog Devices AD7477, AD7476, AD7478 Datasheet

1 MSPS, 12-/10-/8-Bit ADCs

FEATURES Fast Throughput Rate: 1 MSPS Speciﬁed for V Low Power:

3.6 mW Typ at 1 MSPS with 3 V Supplies 15 mW Typ at 1 MSPS with 5 V Supplies

Wide Input Bandwidth:

70 dB SNR at 100 kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High-Speed Serial Interface

SPI™/QSPI™/MICROWIRE™/DSP Compatible Standby Mode: 1 ␮A Max 6-Lead SOT-23 Package

APPLICATIONS Battery-Powered Systems

Personal Digital Assistants

Medical Instruments

Mobile Communications Instrumentation and Control Systems Data Acquisition Systems High-Speed Modems Optical Sensors

GENERAL DESCRIPTION

The AD7476/AD7477/AD7478 are, respectively, 12-bit, 10-bit, and 8-bit, high-speed, low-power, successive-approximation ADCs. The parts operate from a single 2.35 V to 5.25 V power supply and feature throughput rates up to 1 MSPS. The parts contain a low-noise, wide bandwidth track/hold ampliﬁer that can handle input frequencies in excess of 1 MHz.

The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and the conversion is also initiated at this point. There are no pipelined delays associated with the part.

The AD7476/AD7477/AD7478 use advanced design techniques to achieve very low-power dissipation at high throughput rates.

The reference for the part is taken internally from V allows the widest dynamic input range to the ADC. Thus the analog input range for the part is 0 to V is determined by the SCLK.

of 2.35 V to 5.25 V

This

DD.

. The conversion rate

in 6-Lead SOT-23

AD7476/AD7477/AD7478

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

T/H

AD7476/AD7477/AD7478

1. First 12-/10-/8-bit ADCs in an SOT-23 package.

2. High Throughput with Low Power Consumption.

3. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. This allows the average power consumption to be reduced while not converting. The part also features a shutdown mode to maximize power efﬁciency at lower throughput rates. Power consumption is 1 µA max when in shutdown.

4. Reference derived from the power supply.

5. No Pipeline Delay. The parts feature a standard successive-approximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control.

8-/10-/12-BIT

SUCCESSIVE

APPROXIMATION

ADC

CONTROL

LOGIC

GND

SCLK

SDATA

SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation.

REV. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000

AD7476/AD7477/AD7478

AD7476–SPECIFICATIONS

S and B Versions: VDD = 2.35 V to 5.25 V, f

Parameter A Version

DYNAMIC PERFORMANCE f

Signal-to-Noise + Distortion (SINAD)

Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR)3–82 –80 –80 dB typ Intermodulation Distortion (IMD)

= 12 MHz, f

SCLK

69 70 69 dB min 70 70 dB min TA = 25°C 70 71 70 dB min

–80 –78 –78 dB typ

(A Version: VDD = 2.7 V to 5.25 V, f

= 600 kSPS unless otherwise noted; TA = T

SAMPLE

1, 2

B Version

1, 2

S Version

1, 2

Second Order Terms –78 –78 –78 dB typ fa = 103.5 kHz, fb = 113.5 kHz

Third Order Terms –78 –78 –78 dB typ fa = 103.5 kHz, fb = 113.5 kHz Aperture Delay 10 10 10 ns max Aperture Jitter 30 30 30 ps typ Full Power Bandwidth 6.5 6.5 6.5 MHz typ @ 3 dB

DC ACCURACY S, B Versions, VDD = (2.35 V to 3.6 V)4;

Resolution 12 12 12 Bits Integral Nonlinearity

Differential Nonlinearity

Offset Error

Gain Error

± 1 ± 0.6 ± 0.6 LSB typ

± 0.75 ± 0.75 ± 0.75 LSB typ

± 1.5 ± 1.5 LSB max

–0.9/+1.5 –0.9/+1.5 LSB max Guaranteed No Missed Codes to 12 Bits

± 1.5 ± 2 LSB max

± 0.5 LSB typ

± 1.5 ± 2 LSB max

± 0.5 LSB typ

ANALOG INPUT

Input Voltage Ranges 0 to V

0 to V

DC Leakage Current ± 1 ± 1 ± 1 µA max Input Capacitance 30 30 30 pF typ

LOGIC INPUTS

Input High Voltage, V

INH

2.4 2.4 2.4 V min

1.8 1.8 1.8 V min VDD = 2.35 V

Input Low Voltage, V

INL

0.4 0.4 0.4 V max VDD = 3 V

0.8 0.8 0.8 V max VDD = 5 V Input Current, IIN, SCLK Pin ± 1 ± 1 ± 1 µA max Typically 10 nA, V Input Current, IIN, CS Pin ± 1 ± 1 ± 1 µA typ Input Capacitance, C

3, 5

10 10 10 pF max

LOGIC OUTPUTS

Output High Voltage, V Output Low Voltage, V

Floating-State Leakage Current ±10 ± 10 ±10 µA max Floating-State Output Capacitance

3, 5

VDD – 0.2 VDD – 0.2 VDD – 0.2 V min I

0.4 0.4 0.4 V max I

10 10 10 pF max

Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 0.8 1.33 1.33 µs max Sixteen SCLK Cycles Track/Hold Acquisition Time 500 500 500 ns max Full-Scale Step Input

350 400 400 ns max Sine Wave Input ≤100 kHz

Throughput Rate 1000 600 600 kSPS max See Serial Interface Section

POWER REQUIREMENTS

2.35/5.25 2.35/5.25 2.35/5.25 V min/max

Normal Mode (Static) 2 2 2 mA typ VDD = 4.75 V to 5.25 V. SCLK On or Off

1 1 1 mA typ VDD = 2.35 V to 3.6 V. SCLK On or Off

Normal Mode (Operational) 3.5 3 3 mA max VDD = 4.75 V to 5.25 V. f

1.6 1.4 1.4 mA max VDD = 2.35 V to 3.6 V. f Full Power-Down Mode 1 1 1 µA max SCLK Off

Power Dissipation

80 80 80 µA max SCLK On

Normal Mode (Operational) 17.5 15 15 mW max VDD = 5 V. f

4.8 4.2 4.2 mW max VDD = 3 V. f

Full Power-Down 5 5 5 µW max VDD = 5 V. SCLK Off

333µW max VDD = 3 V. SCLK Off

NOTES

Temperature ranges as follows: A, B Versions: –40°C to +85°C, S Version: –55°C to +125°C.

Operational from VDD = 2.0 V.

See Terminology.

Maximum B, S Versions specs apply as typical ﬁgures when VDD = 5.25 V.

Sample tested at 25°C to ensure compliance.

A Version: f

See Power Versus Throughput Rate section.

Speciﬁcations subject to change without notice.

–2–

= 20 MHz, f

SCLK

MIN

= 1 MSPS unless otherwise noted;

SAMPLE

to T

, unless otherwise noted.)

MAX

Unit Test Conditions/Comments

= 100 kHz Sine Wave

A Version, VDD = (2.7 V to 3.6 V)

= 0 V or V

= 200 µA; VDD = 2.35 V to 5.25 V

SOURCE

= 200 µA

SINK

Digital I/Ps = 0 V or V

MAX = 1 MSPS; B, S Versions: f

SAMPLE

= f

SAMPLE

= f

SAMPLE

MAX = 600 kSPS.

SAMPLE

= f

MAX MAX

SAMPLE

MAX

REV. A

AD7476/AD7477/AD7478

AD7477–SPECIFICATIONS

Parameter A Version

(VDD = 2.7 V to 5.25 V, f

1, 2

S Version

DYNAMIC PERFORMANCE f

Signal-to-Noise + Distortion (SINAD) 61 61 dB min Total Harmonic Distortion (THD) –73 –73 dB max Peak Harmonic or Spurious Noise (SFDR) –74 –74 dB max Intermodulation Distortion (IMD)

Second Order Terms –78 –78 dB typ fa = 103.5 kHz, fb = 113.5 kHz

Third Order Terms –78 –78 dB typ fa = 103.5 kHz, fb = 113.5 kHz Aperture Delay 10 10 ns max Aperture Jitter 30 30 ps typ Full Power Bandwidth 6.5 6.5 MHz typ @ 3 dB

DC ACCURACY

Resolution 10 10 Bits Integral Nonlinearity ± 1 ±1 LSB max Differential Nonlinearity ± 0.9 ±0.9 LSB max Guaranteed No Missed Codes to 10 Bits Offset Error ± 1 ±1 LSB max Gain Error ± 1 ±1 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to V

0 to V DC Leakage Current ± 1 ±1 µA max Input Capacitance 30 30 pF typ

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V

INH

INL

2.4 2.4 V min

0.8 0.8 V max VDD = 5 V

0.4 0.4 V max V Input Current, I Input Current, IIN, CS Pin ± 1 ±1 µA typ Input Capacitance, C

, SCLK Pin ± 1 ±1 µA max Typically 10 nA, V

3, 4

10 10 pF max

LOGIC OUTPUTS

Output High Voltage, V Output Low Voltage, V Floating-State Leakage Current ±10 ± 10 µA max Floating-State Output Capacitance

3, 4

VDD – 0.2 VDD – 0.2 V min I

0.4 0.4 V max I

10 10 pF max

Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 800 800 ns max 16 SCLK Cycles with SCLK at 20 MHz Track/Hold Acquisition Time 400 400 ns max Throughput Rate 1 1 MSPS max See Serial Interface Section

POWER REQUIREMENTS

2.7/5.25 2.7/5.25 V min/max

Normal Mode (Static) 2 2 mA typ VDD = 4.75 V to 5.25 V. SCLK On or Off

1 1 mA typ V

Normal Mode (Operational) 3.5 3.5 mA max V

1.6 1.6 mA max V

Full Power-Down Mode 1 1 µA max SCLK Off

80 80 µA max SCLK On

Power Dissipation

Normal Mode (Operational) 17.5 17.5 mW max VDD = 5 V. f

4.8 4.8 mW max V

Full Power-Down 5 5 µW max VDD = 5 V. SCLK Off

NOTES

Temperature ranges as follows: A Version: –40°C to +85°C,

Operational from VDD = 2.0 V, with input high voltage, V

See Terminology.

Sample tested at 25°C to ensure compliance.

See Power Versus Throughput Rate section.

Speciﬁcations subject to change without notice.

S Version: –55°C to +125°C.

= 1.8 V min.

INH

SCLK

1, 2

= 20 MHz, TA = T

MIN

to T

, unless otherwise noted.)

MAX

Unit Test Conditions/Comments

= 100 kHz Sine Wave, f

= 3 V

= 200 µA; VDD = 2.7 V to 5.25 V

SOURCE

= 200 µA

SINK

Digital I/Ps = 0 V or V

= 2.7 V to 3.6 V. SCLK On or Off

= 4.75 V to 5.25 V. f

= 2.7 V to 3.6 V. f

SAMPLE

= 3 V. f

SAMPLE

= 0 V or V

= 1 MSPS = 1 MSPS

SAMPLE

= 1 MSPS

REV. A

–3–

AD7476/AD7477/AD7478

AD7478–SPECIFICATIONS

Parameter A Version

DYNAMIC PERFORMANCE f

Signal-to-Noise + Distortion (SINAD) 49 dB min Total Harmonic Distortion (THD) –65 dB max Peak Harmonic or Spurious Noise (SFDR) –65 dB max Intermodulation Distortion (IMD)

Second Order Terms –68 dB typ fa = 498.7 kHz, fb = 508.7 kHz

Third Order Terms –68 dB typ fa = 498.7 kHz, fb = 508.7 kHz Aperture Delay 10 ns max Aperture Jitter 30 ps typ Full Power Bandwidth 6.5 MHz typ @ 3 dB

DC ACCURACY

Resolution 8 Bits Integral Nonlinearity ±0.5 LSB max Differential Nonlinearity ± 0.5 LSB max Guaranteed No Missed Codes to 8 Bits Offset Error ± 0.5 LSB max Gain Error ± 0.5 LSB max Total Unadjusted Error (TUE) ±0.5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to V DC Leakage Current ± 1 µA max Input Capacitance 30 pF typ

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V

Input Current, I Input Current, IIN, CS Pin ± 1 µA typ Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, V Output Low Voltage, V Floating-State Leakage Current ± 10 µA max Floating-State Output Capacitance Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 800 ns max 16 SCLK Cycles with SCLK at 20 MHz Track/Hold Acquisition Time 400 ns max Throughput Rate 1 MSPS max Conversion Time + Quiet Time

POWER REQUIREMENTS

Normal Mode (Static) 2 mA typ VDD = 4.75 V to 5.25 V. SCLK On or Off

Normal Mode (Operational) 3.5 mA max V

Full Power-Down Mode 1 µA max SCLK Off

Power Dissipation

Normal Mode (Operational) 17.5 mW max VDD = 5 V. f

Full Power-Down 5 µW max VDD = 5 V. SCLK Off

NOTES

Temperature ranges as follows: A Version: –40°C to +85°C.

Operational from VDD = 2.0 V, with input high voltage, V

See Terminology.

Sample tested at 25°C to ensure compliance.

See Power Versus Throughput Rate section.

Speciﬁcations subject to change without notice.

INH

INL

, SCLK Pin ± 1 µA max Typically 10 nA, V

3, 4

INH

(VDD = 2.7 V to 5.25 V, f

1, 2

Unit Test Conditions/Comments

2.4 V min

0.8 V max VDD = 5 V

0.4 V max V

10 pF max

VDD – 0.2 V min I

0.4 V max I

10 pF max

2.7/5.25 V min/max

1 mA typ V

1.6 mA max V

80 µA max SCLK On

4.8 mW max V

= 1.8 V min.

–4–

= 20 MHz, TA = T

SCLK

SOURCE

SINK

Digital I/Ps = 0 V or V

to T

MIN

= 100 kHz Sine Wave, f

= 3 V

, unless otherwise noted.)

MAX

SAMPLE

= 0 V or V

= 1 MSPS

= 200 µA; VDD = 2.7 V to 5.25 V

= 200 µA

= 2.7 V to 3.6 V. SCLK On or Off

= 4.75 V to 5.25 V. f

= 2.7 V to 3.6 V. f

= 1 MSPS

= 3 V. f

SAMPLE

= 1 MSPS

SAMPLE

= 1 MSPS

REV. A

AD7476/AD7477/AD7478

WARNING!

ESD SENSITIVE DEVICE

1, 2

TIMING SPECIFICATIONS

Limit at T AD7476/AD7477/AD7478

Parameter 3 V

SCLK

10 10 kHz min

MIN

(VDD = 2.35 V to 5.25 V; TA = T

, T

MAX

Unit Description

20 20 MHz max A Version 12 12 MHz max B Version

CONVERT

QUIET

16 × t

SCLK

16 × t

SCLK

50 50 ns min Minimum Quiet Time Required Between Bus Relinquish and

10 10 ns min Minimum CS Pulsewidth 10 10 ns min CS to SCLK Setup Time 20 20 ns max Delay from CS Until SDATA Three-State Disabled 40 20 ns max Data Access Time After SCLK Falling Edge. A Version 70 20 ns max Data Access Time After SCLK Falling Edge. B Version

POWER-UP

NOTES

Sample tested at 25°C to ensure compliance. All input signals are speciﬁed with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

A Version timing specifications apply to the AD7477 S Version; B Version timing specifications apply to the AD7476 S Version.

3 V specifications apply from VDD = 2.7 V to 3.6 V for A Version; 3 V specifications apply from VDD = 2.35 V to 3.6 V for B Version; 5 V specifications apply from VDD = 4.75 V to 5.25 V.

Mark/Space ratio for the SCLK input is 40/60 to 60/40.

Measured with the load circuit of Figure 1 and deﬁned as the time required for the output to cross 0.8 V or 2.0 V.

t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.

See Power-up Time section.

Speciﬁcations subject to change without notice.

0.4 t

SCLK

0.4 t

SCLK

ns min SCLK Low Pulsewidth

ns min SCLK High Pulsewidth 10 10 ns min SCLK to Data Valid Hold Time 10 10 ns min SCLK Falling Edge to SDATA High Impedance 25 25 ns max SCLK Falling Edge to SDATA High Impedance

11µs typ Power-Up Time from Full Power-Down

to T

MIN

, unless otherwise noted.)

MAX

Start of Next Conversion

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C unless otherwise noted)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Analog Input Voltage to GND . . . . . . . –0.3 V to V

+ 0.3 V

Digital Input Voltage to GND . . . . . . . . . . . . . –0.3 V to +7 V

Digital Output Voltage to GND . . . . . –0.3 V to V

Input Current to Any Pin Except Supplies

. . . . . . . ± 10 mA

+ 0.3 V

NOTES

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this speciﬁcation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Transient currents of up to 100 mA will not cause SCR latch-up.

Operating Temperature Range

Commercial (A, B Version) . . . . . . . . . . . . –40°C to +85°C

200␮A

Military (S Version) . . . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

SOT-23 Package, Power Dissipation . . . . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 230°C/W

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 92°C/W

TO OUTPUT

50pF

200␮A

Lead Temperature, Soldering

Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

Figure 1. Load Circuit for Digital Output Timing Speciﬁcations

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 kV

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7476/AD7477/AD7478 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

1.6V

REV. A

–5–

+ 11 hidden pages

Analog Devices AD7477, AD7476, AD7478 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual