ANALOG DEVICES AD7476-EP Service Manual

V

V

12-Bit ADC

FEATURES

Specified for VDD of 2.35 V to 5.25 V
Low power

3.6 mW at 600 kSPS with 3 V supplies
15 mW at 600 kSPS with 5 V supplies

Wide input bandwidth

70 dB SNR at 100 kHz input frequency

High speed serial interface

SPI/QSPI™/MICROWIRE™/DSP compatible
Standby mode: 1 μA maximum
6-lead SOT-23 package

ENHANCED PRODUCT FEATURES

Military temperature range (−55°C to +125°C)

Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available upon request

APPLICATIONS

Battery-powered systems

Personal digital assistants

Medical instruments

Mobile communications
Instrumentation and control systems
Data acquisition systems

GENERAL DESCRIPTION

The AD74761 is a 12-bit, high speed, low power, successive
approximation ADC. The part operates from a single 2.35 V
to 5.25 V power supply and features throughput rates up to
600 kSPS. The part contains a low noise, wide bandwidth, track­and-hold amplifier that can handle input frequencies in excess
of 6 MHz.

The conversion process and data acquisition are controlled

CS

using
with microprocessors or DSPs. The input signal is sampled on
the falling edge of
point. There are no pipeline delays associated with this part.

The AD7476 uses advanced design techniques to achieve very
low power dissipation at high throughput rates.

1

Protected by U.S. Patent No. 6,681,332.

and the serial clock, allowing the device to interface

CS

and the conversion is initiated at this

in 6-Lead SOT-23

AD7476-EP

FUNCTIONAL BLOCK DIAGRAM

DD

12-BIT

IN

The reference for the part is taken internally from V
allows the widest dynamic input range to the ADC. Thus, the
analog input range for the part is 0 V to V
rate is determined by the SCLK pin.

Additional application and technical information can be found
in the AD7476 data sheet.

PRODUCT HIGHLIGHTS

1. First 12-Bit ADC in a SOT-23 Package.

2. High Throughput with Low Power Consumption.

3. Flexible Power/Serial Clock Speed Management. The

conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. This allows the average power consumption
to be reduced while not converting. The part also features a
shutdown mode to maximize power efficiency at lower
throughput rates. Current consumption is 1 μA maximum
when in shutdown mode.

4. Reference Derived from the Power Supply.

5. No Pipeline Delay. The part features a standard successive-

approximation ADC with accurate control of the sampling
instant via a

SUCCESSIVE-

APPROXIMATION

ADC

CONTROL

LOGIC

AD7476-EP

GND

Figure 1.

CS

input and once-off conversion control.

SCLK
SDATA
CS

09224-001

DD

. The conversion

DD

. This

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2010 Analog Devices, Inc. All rights reserved.

AD7476-EP

TABLE OF CONTENTS

Features.............................................................................................. 1

Timing Specifications ...................................................................5

Enhanced Product Features ............................................................ 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

REVISION HISTORY

8/10—Revision 0: Initial Version

Absolute Maximum Ratings ............................................................6

ESD Caution...................................................................................6

Pin Configuration and Function Descriptions..............................7

Typical Performance Characteristics..............................................8

Outline Dimensions..........................................................................9

Ordering Guide .............................................................................9

Rev. 0 | Page 2 of 12

AD7476-EP

SPECIFICATIONS

VDD = 2.35 V to 5.25 V, f

Table 1.

Parameter S Version Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 100 kHz sine wave

Signal-to-(Noise + Distortion) (SINAD) 69 dB min

70 dB min TA = 25°C

Signal-to-Noise Ratio (SNR) 70 dB min
Total Harmonic Distortion (THD) −78 dB typ
Peak Harmonic or Spurious Noise (SFDR) −80 dB typ
Intermodulation Distortion (IMD)

Second-Order Terms −78 dB typ fa = 103.5 kHz, fb = 113.5 kHz

Third-Order Terms −78 dB typ fa = 103.5 kHz, fb = 113.5 kHz
Aperture Delay 10 ns typ
Aperture Jitter 30 ps typ
Full Power Bandwidth 6.5 MHz typ At 3 dB

DC ACCURACY VDD = (2.35 V to 3.6 V)1

Resolution 12 Bits
Integral Nonlinearity ±1.5 LSB max
±0.6 LSB typ
Differential Nonlinearity −0.9/+1.5 LSB max Guaranteed no missed codes to 12 bits
±0.75 LSB typ
Offset Error ±2 LSB max
LSB typ
Gain Error ±2 LSB max

LSB typ
ANALOG INPUT

Input Voltage Ranges 0 to VDD V
DC Leakage Current ±1 μA max
Input Capacitance 30 pF typ

LOGIC INPUT

Input High Voltage, V

1.8 V min VDD = 2.35 V
Input Low Voltage, V

0.8 V max VDD = 5 V
Input Current, IIN, SCLK Pin ±1 μA max Typically 10 nA, VIN = 0 V or VDD
Input Current, IIN, CS Pin
Input Capacitance, C

LOGIC OUTPUT

Output High Voltage, VOH VDD − 0.2 V min I
Output Low Voltage, VOL 0.4 V max I
Floating-State Leakage Current ±10 μA max
Floating-State Output Capacitance2 10 pF max
Output Coding Straight (natural) binary

CONVERSION RATE

Conversion Time 1.33 μs max 16 SCLK cycles
Track-and-Hold Acquisition Time 500 ns max Full-scale step input
400 ns max Sine wave input ≤ 100 kHz
Throughput Rate 600 kSPS max

= 12 MHz, f

SCLK

2.4 V min

INH

0.4 V max VDD = 3 V

INL

= 600 kSPS, unless otherwise noted; TA = T

SAMPLE

MIN

±1 μA typ

2

10 pF max

IN

SOURCE

= 200 μA

SINK

to T

, unless otherwise noted.

MAX

= 200 μA; VDD = 2.35 V to 5.25 V

Rev. 0 | Page 3 of 12

AD7476-EP

Parameter S Version Unit Test Conditions/Comments

POWER REQUIREMENTS

VDD 2.35/5.25 V min/max
IDD Digital I/Ps = 0 V or VDD

Normal Mode (Static) 2 mA typ VDD = 4.75 V to 5.25 V, SCLK on or off
1 mA typ VDD = 2.35 V to 3.6 V, SCLK on or off
Normal Mode (Operational) 3 mA max

1.4 mA max

Full Power-Down Mode 1 μA max SCLK off

80 μA max SCLK on
Power Dissipation

Normal Mode (Operational) 15 mW max VDD = 5 V, f

4.2 mW max VDD = 3 V, f
Full Power-Down 5 μW max VDD = 5 V, SCLK off

3 μW max VDD = 3 V, SCLK off

1

S version specifications apply as typical figures when VDD = 5.25 V.

2

Guaranteed by characterization.

3

f

MAX = 600 kSPS.

SAMPLE

= 4.75 V to 5.25 V,

V

DD

= f

f

V

SAMPLE

DD

f

SAMPLE

SAMPLE

= 2.35 V to 3.6 V,

= f

SAMPLE

SAMPLE

SAMPLE

MAX3

MAX4

= f

SAMPLE

= f

SAMPLE

MAX4
MAX4

Rev. 0 | Page 4 of 12