ANALOG DEVICES AD7476A, AD7477A, AD7478A Service Manual

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2.35 V to 5.25 V, 1 MSPS,

FEATURES Fast Throughput Rate: 1 MSPS Specified for V Low Power:

3.6 mW Typ at 1 MSPS with 3 V Supplies

12.5 mW Typ at 1 MSPS with 5 V Supplies

Wide Input Bandwidth:

71 dB SNR at 100 kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High Speed Serial Interface

/QSPI™/MICROWIRE™/DSP Compatible

SPI Standby Mode: 1 ␮A Max 6-Lead SC70 Package 8-Lead MSOP Package

APPLICATIONS Battery-Powered Systems

Personal Digital Assistants

Medical Instruments

Mobile Communications Instrumentation and Control Systems Data Acquisition Systems High Speed Modems Optical Sensors

of 2.35 V to 5.25 V

12-/10-/8-Bit ADCs in 6-Lead SC70

AD7476A/AD7477A/AD7478A

FUNCTIONAL BLOCK DIAGRAM

12-/10-/8-BIT

T/H

AD7476A/AD7477A/AD7478A

SUCCESSIVE-

APPROXIMATION

ADC

CONTROL

LOGIC

GND

SCLK

SDATA

GENERAL DESCRIPTION

The AD7476A/AD7477A/AD7478A are 12-bit, 10-bit, and 8-bit high speed, low power, successive-approximation ADCs, respectively. The parts operate from a single 2.35 V to 5.25 V power supply and feature throughput rates up to 1 MSPS. The parts contain a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 13 MHz.

The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS, and the conversion is also initiated at this point. There are no pipeline delays associated with the parts.

The AD7476A/AD7477A/AD7478A use advanced design techniques to achieve low power dissipation at high throughput rates.

The reference for the part is taken internally from V

DD,

which allows the widest dynamic input range to the ADC. Thus, the analog input range for the part is 0 to V

. The conversion rate is

determined by the SCLK.

*Protected by U.S.Patent No. 6,681,332.

REV. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

PRODUCT HIGHLIGHTS

1. First 8-/10-/12-bit ADCs in an SC70 package.

2. High throughput with low power consumption.

3. Flexible power/serial clock speed management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. This allows the average power consumption to be reduced when a power-down mode is used while not converting. The parts also feature a power-down mode to maximize power efficiency at lower throughput rates. Current consumption is 1 µA max and 50 nA typically when in power-down mode.

4. Reference derived from the power supply.

5. No pipeline delay. The parts feature a standard successiveapproximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control.

AD7476A/AD7477A/AD7478A

AD7476A–SPECIFICATIONS

= 2.35 V to 5.25 V, f

TA = T

MIN

to T

, unless otherwise noted.)

MAX

SCLK

= 20 MHz, f

= 1 MSPS, unless otherwise noted;

SAMPLE

Parameter

DYNAMIC PERFORMANCE f

Signal-to-Noise + Distortion (SINAD)

Signal-to-Noise Ratio (SNR)

Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR)3–82 –82 –82 dB typ Intermodulation Distortion (IMD)

A Grade2B Grade2Y Grade2Unit Test Conditions/Comments

= 100 kHz Sine Wave

70 70 70 dB min V 69 69 69 dB min V

71.5 71.5 71.5 dB typ V 69 69 69 dB min V 68 68 68 dB min V 71 71 71 dB min V 70 70 70 dB min V 70 70 70 dB min V 69 69 69 dB min V

–80 –80 –80 dB typ

= 2.35 V to 3.6 V, TA = 25ⴗC

= 2.4 V to 3.6 V

= 2.35 V to 3.6 V

= 4.75 V to 5.25 V, TA = 25ⴗC

= 4.75 V to 5.25 V

= 2.35 V to 3.6 V, TA = 25ⴗC

= 2.4 V to 3.6 V

= 4.75 V to 5.25 V, TA = 25ⴗC

= 4.75 V to 5.25 V

Second-Order Terms –84 –84 –84 dB typ fa = 100.73 kHz, fb = 90.72 kHz

Third-Order Terms –84 –84 –84 dB typ fa = 100.73 kHz, fb = 90.72 kHz Aperture Delay 10 10 10 ns typ Aperture Jitter 30 30 30 ps typ Full Power Bandwidth 13.5 13.5 13.5 MHz typ @ 3 dB

222 MHz typ @ 0.1 dB

DC ACCURACY B and Y Grades

Resolution 12 12 12 Bits Integral Nonlinearity

± 1.5 ± 1.5 LSB max

± 0.75 LSB typ

Differential Nonlinearity

Offset Error

Gain Error

Total Unadjusted Error (TUE)

3, 5

–0.9/+1.5 –0.9/+1.5

± 0.75 LSB typ

± 1.5 ± 1.5 LSB max

± 1.5 ± 0.2 ± 0.2 LSB typ

± 1.5 ± 1.5 LSB max

± 1.5 ± 0.5 ± 0.5 LSB typ

± 2 ± 2 LSB max

LSB max

Guaranteed No Missed Codes to 12 Bits

ANALOG INPUT

Input Voltage Range 0 to V

0 to V

V DC Leakage Current ± 0.5 ± 0.5 ± 0.5 µA max Input Capacitance 20 20 20 pF typ

Track-and-Hold in Track; 6 pF typ when in Hold

LOGIC INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, I Input Current, IIN, CS Pin ± 10 ± 10 ± 10 nA typ Input Capacitance, C

INH

INL

, SCLK Pin ± 0.5 ± 0.5 ± 0.5 µA max Typically 10 nA, V

2.4 2.4 2.4 V min

1.8 1.8 1.8 V min V

0.8 0.8 0.8 V max V

0.4 0.4 0.4 V max V

555 pF max

= 2.35 V = 5 V = 3 V

= 0 V or V

LOGIC OUTPUTS

Output High Voltage, V Output Low Voltage, V Floating-State Leakage Current ± 1 ± 1 ± 1 µA max Floating-State Output Capacitance

Output Coding

– 0.2 V

0.4 0.4 0.4 V max I

555 pF max

Straight (Natural) Binary

– 0.2 V

– 0.2 V min

SOURCE

SINK

= 200 µA; V

= 200 µA

= 2.35 V to 5.25 V

CONVERSION RATE

Conversion Time 800 800 800 ns max 16 SCLK Cycles Track-and-Hold Acquisition Time

250 250 250 ns max

Throughput Rate 1 1 1 MSPS max See Serial Interface Section

REV. C–2–

AD7476A/AD7477A/AD7478A

Parameter

A Grade2B Grade2Y Grade2Unit Test Conditions/Comments

POWER REQUIREMENTS

Normal Mode (Static) 2.5 2.5 2.5 mA typ V

Normal Mode (Operational) 3.5 3.5 3.5 mA max V

2.35/5.25 2.35/5.25 2.35/5.25 V min/max

1.2 1.2 1.2 mA typ V

1.7 1.7 1.7 mA max V

Digital I/Ps = 0 V or V

= 4.75 V to 5.25 V, SCLK ON or OFF

= 2.35 V to 3.6 V, SCLK ON or OFF

= 4.75 V to 5.25 V, f

= 2.35 V to 3.6 V, f

Full Power-Down Mode (Static) 1 1 1 µA max Typically 50 nA Full Power-Down Mode (Dynamic)

Power Dissipation

Normal Mode (Operational) 17.5 17.5 17.5 mW max V

Full Power-Down Mode 5 5 5 µW max V

NOTES

Temperature ranges as follows: A, B Grades: –40°C to +85°C, Y Grade: –40°C to +125°C.

Operational from V

See Terminology section.

B and Y Grades, maximum specifications apply as typical figures when VDD = 4.75 V to 5.25 V.

SC70 values guaranteed by characterization.

Guaranteed by characterization.

See Power vs. Throughput Rate section.

Specifications subject to change without notice.

= 2.0 V, with input low voltage (V

0.6 0.6 0.6 mA typ VDD = 5 V, f

0.3 0.3 0.3 mA typ V

5.1 5.1 5.1 mW max V

333µW max V

) 0.35 V max.

INL

= 3 V, f

= 5 V, f

= 3 V, f

= 5 V

= 3 V

SAMPLE

= 100 kSPS

= 1 MSPS = 1 MSPS

= 1 MSPS

= 2.35 V to 5.25 V, f

AD7477A–SPECIFICATIONS

TA = T

Parameter A Grade

DYNAMIC PERFORMANCE f

Signal-to-Noise + Distortion (SINAD) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) Intermodulation Distortion (IMD)

61 dB min –72 dB max

–73 dB max

to T

MIN

, unless otherwise noted.)

MAX

Unit Test Conditions/Comments

= 20 MHz, f

SCLK

= 1 MSPS, unless otherwise noted;

SAMPLE

= 100 kHz Sine Wave

Second-Order Terms –82 dB typ fa = 100.73 kHz, fb = 90.7 kHz

Third-Order Terms –82 dB typ fa = 100.73 kHz, fb = 90.7 kHz Aperture Delay 10 ns typ Aperture Jitter 30 ps typ Full Power Bandwidth 13.5 MHz typ @ 3 dB

2 MHz typ @ 0.1 dB

DC ACCURACY

Resolution 10 Bits Integral Nonlinearity ± 0.5 LSB max Differential Nonlinearity ± 0.5 LSB max Guaranteed No Missed Codes to 10 Bits Offset Error Gain Error Total Unadjusted Error (TUE)

3, 4

± 1LSB max ± 1LSB max ± 1.2 LSB max

ANALOG INPUT

Input Voltage Range 0 to V

V DC Leakage Current ± 0.5 µA max Input Capacitance 20 pF typ Track-and-Hold in Track; 6 pF typ when

in Hold

REV. C

–3–

AD7476A/AD7477A/AD7478A

Parameter A Grade

Unit Test Conditions/Comments

LOGIC INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, I Input Current, IIN, CS Pin ± 10 nA typ Input Capacitance, C

INH

INL

, SCLK Pin ± 0.5 µA max Typically 10 nA, V

2.4 V min

1.8 V min V

0.8 V max V

0.4 V max V

5 pF max

= 2.35 V

= 5 V

= 3 V

= 0 V or V

LOGIC OUTPUTS

Output High Voltage, V Output Low Voltage, V Floating-State Leakage Current ± 1 µA max Floating-State Output Capacitance

– 0.2 V min I

0.4 V max I

5 pF max

SOURCE

= 200 µA

SINK

= 200 µA, V

= 2.35 V to 5.25 V

Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 700 ns max 14 SCLK Cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time

250 ns max

Throughput Rate 1 MSPS max

POWER REQUIREMENTS

Normal Mode (Static) 2.5 mA typ V

Normal Mode (Operational) 3.5 mA max V

2.35/5.25 V min/max

1.2 mA typ V

1.7 mA max V

Digital I/Ps = 0 V or V

= 4.75 V to 5.25 V, SCLK ON or OFF

= 2.35 V to 3.6 V, SCLK ON or OFF

= 4.75 V to 5.25 V, f

= 2.35 V to 3.6 V, f

SAMPLE

= 1 MSPS

= 1 MSPS Full Power-Down Mode (Static) 1 µA max Typically 50 nA Full Power-Down Mode (Dynamic) 0.6 mA typ V

0.3 mA typ V

Power Dissipation

Normal Mode (Operational) 17.5 mW max V

5.1 mW max V

Full Power-Down Mode 5 µW max V

NOTES

Temperature range from –40°C to +85°C.

Operational from V

See Terminology section.

SC70 values guaranteed by characterization.

Guaranteed by characterization.

See Power vs. Throughput Rate section.

Specifications subject to change without notice.

= 2.0 V, with input high voltage (V

) 1.8 V min.

INH

= 5 V, f

= 3 V, f

= 5 V, f

= 3 V, f

= 5 V

SAMPLE

= 100 kSPS = 100 kSPS

= 1 MSPS = 1 MSPS

= 2.35 V to 5.25 V, f

TA = T

to T

AD7478A–SPECIFICATIONS

Parameter A Grade

DYNAMIC PERFORMANCE f

Signal-to-Noise + Distortion (SINAD) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) Intermodulation Distortion (IMD)

49 dB min –65 dB max

–65 dB max

MIN

, unless otherwise noted.)

MAX

Unit Test Conditions/Comments

= 20 MHz, f

SCLK

= 1 MSPS, unless otherwise noted;

SAMPLE

= 100 kHz Sine Wave

Second-Order Terms –76 dB typ fa = 100.73 kHz, fb = 90.7 kHz Third-Order Terms –76 dB typ fa = 100.73 kHz, fb = 90.7 kHz

Aperture Delay 10 ns typ Aperture Jitter 30 ps typ Full Power Bandwidth 13.5 MHz typ @ 3 dB

2 MHz typ @ 0.1 dB

REV. C–4–

AD7476A/AD7477A/AD7478A

Parameter A Grade

Unit Test Conditions/Comments

DC ACCURACY

Resolution 8 Bits Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error

3, 4

Total Unadjusted Error (TUE)

± 0.3 LSB max ± 0.3 LSB max Guaranteed No Missed Codes to Eight Bits ± 0.3 LSB max

3, 4

± 0.3 LSB max ± 0.5 LSB max

ANALOG INPUT

Input Voltage Range 0 to V

V DC Leakage Current ± 0.5 µA max Input Capacitance 20 pF typ Track-and-Hold in Track; 6 pF typ when

in Hold

LOGIC INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, I Input Current, IIN, CS Pin ± 10 nA typ Input Capacitance, C

INH

INL

, SCLK Pin ±0.5 µA max Typically 10 nA, V

2.4 V min

1.8 V min V

0.8 V max V

0.4 V max V

5 pF max

= 2.35 V

= 5 V

= 3 V

= 0 V or V

LOGIC OUTPUTS

Output High Voltage, V Output Low Voltage, V Floating-State Leakage Current ±1 µA max Floating-State Output Capacitance

– 0.2 V min I

0.4 V max I

5 pF max

SOURCE

= 200 µA

SINK

= 200 µA, V

= 2.35 V to 5.25 V

Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 600 ns max 12 SCLK Cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time

225 ns max

Throughput Rate 1.2 MSPS max

POWER REQUIREMENTS

Normal Mode (Static) 2.5 mA typ V

Normal Mode (Operational) 3.5 mA max V

2.35/5.25 V min/max

1.2 mA typ V

1.7 mA max V

Digital I/Ps = 0 V or V

= 4.75 V to 5.25 V, SCLK ON or OFF

= 2.35 V to 3.6 V, SCLK ON or OFF

= 4.75 V to 5.25 V

= 2.35 V to 3.6 V

Full Power-Down Mode (Static) 1 µA max Typically 50 nA Full Power-Down Mode (Dynamic) 0.6 mA typ V

0.3 mA typ V

Power Dissipation

Normal Mode (Operational) 17.5 mW max V

5.1 mW max V

Full Power-Down Mode 5 µW max V

NOTES

Temperature range from –40°C to +85°C.

Operational from V

See Terminology section.

SC70 values guaranteed by characterization.

Guaranteed by characterization.

See Power vs. Throughput Rate section.

Specifications subject to change without notice.

= 2.0 V, with input high voltage (V

) 1.8 V min.

INH

= 5 V, f

= 3 V, f

= 5 V

= 3 V

= 5 V

SAMPLE

= 100 kSPS = 100 kSPS

REV. C

–5–

AD7476A/AD7477A/AD7478A

TIMING SPECIFICATIONS

= 2.35 V to 5.25 V; TA = T

MIN

to T

, unless otherwise noted.)

MAX

Limit at T

MIN

, T

MAX

Parameter AD7476A/AD7477A/AD7478A Unit Description

SCLK

10 kHz min 20 kHz min

A, B Grades Y Grade

20 MHz max

CONVERT

QUIET

16 ⫻ t

SCLK

14 ⫻ t

SCLK

12 ⫻ t

SCLK

50 ns min Minimum Quiet Time Required between Bus Relinquish

AD7476A AD7477A AD7478A

and Start of Next Conversion

POWER-UP

NOTES

Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

Mark/space ratio for the SCLK input is 40/60 to 60/40.

Minimum f

Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 1.8 V when VDD = 2.35 V and 0.8 V or 2.0 V for V

Measured with 50 pF load capacitor.

t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.

t7 values also apply to t8 minimum values.

See Power-Up Time section.

Specifications subject to change without notice.

SCLK

10 ns min Minimum CS Pulse Width 10 ns min CS to SCLK Setup Time 22 ns max Delay from CS until SDATA Three-State Disabled 40 ns max Data Access Time after SCLK Falling Edge

0.4 t

SCLK

ns min SCLK Low Pulse Width ns min SCLK High Pulse Width

SCLK to Data Valid Hold Time

10 ns min V

9.5 ns min 3.3 V < V 7 ns min V

≤ 3.3 V

> 3.6 V

≤ 3.6 V

36 ns max SCLK Falling Edge to SDATA High Impedance See Note 7 ns min SCLK Falling Edge to SDATA High Impedance 1 µs max Power-Up Time from Full Power-Down

at which specifications are guaranteed.

> 2.35 V.

1.6V

TO OUTPUT

50pF

200␮A

Figure 1. Load Circuit for Digital Output Timing Specifications

REV. C–6–

AD7476A/AD7477A/AD7478A

Timing Example 1

Having f cycle time of t this leaves t of 250 ns for t

+ t

for t

QUIET,

= 20 MHz and a throughput of 1 MSPS gives a

SCLK

+ 12.5 (1/f

to be 365 ns. This 365 ns satisfies the requirement

ACQ

. From Figure 3, t

ACQ

, where t8 = 36 ns max. This allows a value of 204 ns

QUIET

satisfying the minimum requirement of 50 ns.

SCLK

SDATA

STATE

SCLK

Timing Example 2

SCLK

) + t

= 1 µs. With t2 = 10 ns min,

ACQ

Having f cycle time of t

= 5 MHz and a throughput of 315 kSPS gives a

SCLK

+ 12.5 (1/f

10 ns min, this leaves t

is comprised of 2.5 (1/f

ACQ

SCLK

the requirement of 250 ns for t

)

comprised of 2.5 (1/f

SCLK

allows a value of 128 ns for t requirement of 50 ns. As in this example and with other slower clock values, the signal may already be acquired before the conversion is complete, but it is still necessary to leave 50 ns minimum t

between conversions. In Example 2, the

QUIET

signal should be fully acquired at approximately Point C in Figure 3.

CONVERT

12 345 1314 15 16

ZERO ZERO ZERO DB11 DB10 DB2 DB1 DB0

4 LEADING ZEROS

Figure 2. AD7476A Serial Interface Timing Diagram

SCLK

CONVERT

)

1/THROUGHPUT

ACQ

1 2345 13141516

12.5(1/f

) + t

SCLK

to be 664 ns. This 664 ns satisfies

ACQ

) + t8 + t

QUIET,

THREE-STATETHREE-

= 3.174 µs. With t2 =

ACQ

. From Figure 3, t

, t8 = 36 ns max. This

QUIET

ACQ

satisfying the minimum

QUIET

Figure 3. Serial Interface Timing Example

REV. C

–7–

AD7476A/AD7477A/AD7478A

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted.)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Analog Input Voltage to GND . . . . . . . –0.3 V to V

+ 0.3 V

Digital Input Voltage to GND . . . . . . . . . . . . –0.3 V to +7 V

Digital Output Voltage to GND . . . . . –0.3 V to V

Input Current to Any Pin except Supplies

. . . . . . . . ± 10 mA

+ 0.3 V

Operating Temperature Range

Commercial (A and B Grades) . . . . . . . . . –40°C to +85°C

Industrial (Y Grade) . . . . . . . . . . . . . . . . –40°C to +125°C

Storage Temperature Range . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

MSOP Package

␪

Thermal Impedance . . . . . . . . . . . . . . . . . . 205.9°C/W

␪

Thermal Impedance . . . . . . . . . . . . . . . . . . 43.74°C/W

SC70 Package

␪

Thermal Impedance . . . . . . . . . . . . . . . . . . 340.2°C/W

␪

Thermal Impedance . . . . . . . . . . . . . . . . . . 228.9°C/W

Lead Temperature, Soldering

Reflow (10 sec to 30 sec) . . . . . . . . . . . . . . . . 235 (0/+5)°C

Pb-free Temperature Soldering

Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 (0/+5)°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 kV

NOTES

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Transient currents of up to 100 mA will not cause SCR latch-up.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment, and can discharge without detection. Although the AD7476A/AD7477A/AD7478A feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. C–8–

+ 16 hidden pages

ANALOG DEVICES AD7476A, AD7477A, AD7478A Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual