ANALOG DEVICES AD7475, AD7495 Service Manual

FEATURES AND APPLICATIONS

Fast throughput rate: 1 MSPS
Specified for V
Low power:

4.5 mW max at 1 MSPS with 3 V supplies

10.5 mW max at 1 MSPS with 5 V supplies

Wide input bandwidth:

68 dB SNR at 300 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface:

SPI™-/QSPI™-/MICROWIRE™-/DSP-compatible
On-board reference: 2.5 V (AD7495 only)
Standby mode: 1 μA max
8-lead MSOP and SOIC packages

Battery-powered systems
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
Optical sensors

GENERAL DESCRIPTION

The AD7475/AD74951 are 12-bit, high speed, low power,
successive-approximation ADCs that operate from a single

2.7 V to 5.25 V power supply with throughput rates up to
1 MSPS. They contain a low noise, wide bandwidth track-and­hold amplifier that can handle input frequencies above 1 MHz.

The conversion process and data acquisition are controlled
using

with microprocessors or DSPs. The input signal is sampled on
the falling edge of

The conversion time is determined by the SCLK frequency.
There are no pipeline delays associated with the part.

The AD7475/AD7495 use advanced design techniques to
achieve very low power dissipation at high throughput rates.
With 3 V supplies and a 1 MSPS throughput rate, the AD7475
consumes just 1.5 mA, while the AD7495 consumes 2 mA.
With 5 V supplies and 1 MSPS, the current consumption is

2.1 mA for the AD7475 and 2.6 mA for the AD7495.

The analog input range for the parts is 0 V to REF IN. The 2.5 V
reference for the AD7475 is applied externally to the REF IN
pin, while the AD7495 has an on-board 2.5 V reference.

1

Protected by U.S. Patent No. 6,681,332

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

and the serial clock, allowing the devices to interface

CS

of 2.7 V to 5.25 V

DD

and conversion is initiated at this point.

CS

1 MSPS,12-Bit ADCs

AD7475/AD7495

FUNCTIONAL BLOCK DIAGRAMS

V

DD

T/H

AD7475

V

DD

T/H

BUF

2.5V

REFERENCE

AD7495

REF IN

REF OUT

V

IN

V

IN

PRODUCT HIGHLIGHTS

1. The AD7475 offers 1 MSPS throughput rates with 4.5 mW

power consumption.

2. Single-supply operation with V

AD7475/AD7495 operate from a single 2.7 V to 5.25 V
supply. The V
to connect directly to either 3 V or 5 V processor systems
independent of V

3. Flexible power/serial clock speed management. The con-

version rate is determined by the serial clock, allowing the
conversion time to be reduced through the serial clock
speed increase. The parts also feature shutdown modes to
maximize power efficiency at lower throughput rates. This
allows the average power consumption to be reduced while
not converting. Power consumption is 1 μA when in full
shutdown.

4. No pipeline delay. The parts feature a standard successive

approximation ADC with accurate control of the sampling
instant via a

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

function allows the serial interface

DRIVE

.

DD

input and once-off conversion control.

CS

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

CONTROL

LOGIC

GND

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

CONTROL

LOGIC

GND

Figure 1.

DRIVE

function. The

SCLK
SDATA
CS

V

DRIVE

SCLK
SDATA
CS

V

DRIVE

01684-B-001

AD7475/AD7495

TABLE OF CONTENTS

AD7475 Specifications..................................................................... 3

AD7495 Specifications..................................................................... 5

Timing Specifications....................................................................... 7

Timing Example 1 ........................................................................ 8

Timing Example 2 ........................................................................ 8

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Te r mi n ol o g y .................................................................................... 11

Typical Performance Curves......................................................... 12

Theory of Operation ...................................................................... 13

Converter Operation.................................................................. 13

ADC Transfer Function............................................................. 13

Operating Modes............................................................................ 16

Normal Mode.............................................................................. 16

Partial Power-Down Mode ....................................................... 16

Full Power-Down Mode ............................................................ 17

Power vs. Throughput Rate....................................................... 19

Serial Interface................................................................................ 20

Microprocessor Interfacing ........................................................... 21

AD7475/AD7495 to TMS320C5X/C54X................................. 21

AD7475/AD7495 to ADSP-21XX............................................. 21

AD7475/AD7495 to DSP56XXX ............................................... 22

AD7475/AD7495 to MC68HC16............................................. 22

Outline Dimensions ....................................................................... 23

Ordering Guide .......................................................................... 24

Typical C o n ne ction D i a g ram ................................................... 14

REVISION HISTORY

5/05—Rev. A to Rev. B

Updated Format..................................................................Universal

Added Patent Information .............................................................. 1

Updated Outline Dimensions....................................................... 23

Changes to Ordering Guide.......................................................... 24

Rev. B | Page 2 of 24

AD7475/AD7495

AD7475 SPECIFICATIONS

VDD = 2.7 V to 5.25 V, V

Table 1.

Parameter A Version1B Version

DYNAMIC PERFORMANCE

Signal-to-Noise and Distortion

Ratio (SINAD)
Total Harmonic Distortion (THD) −75 −75 dB max fIN = 300 kHz sine wave, f
Peak Harmonic or Spurious Noise

(SFDR)
Intermodulation Distortion (IMD)

Second-Order Terms −78 −78 dB typ

Third-Order Terms −78 −78 dB typ
Aperture Delay 10 10 ns typ
Aperture Jitter 50 50 ps typ
Full Power Bandwidth 8.3 8.3 MHz typ @ 3 dB
Full Power Bandwidth 1.3 1.3 MHz typ @ 0.1 dB

DC ACCURACY

Resolution 12 12 Bits
Integral Nonlinearity ±1.5 ±1 LSB max @ 5 V (typ @ 3 V)
±0.5 ±0.5 LSB typ @ 25°C
Differential Nonlinearity +1.5/−0.9 +1.5/−0.9 LSB max

±0.5 ±0.5 LSB typ @ 25°C
Offset Error ±8 ±8 LSB max Typically ±2.5 LSB
Gain Error ±3 ±3 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to REF IN V
DC Leakage Current ±1 ±1 μA max
Input Capacitance 20 20 pF typ

REFERENCE INPUT

REF IN Input Voltage Range 2.5 2.5 V ±1% for specified performance
DC Leakage Current ±1 ±1 μA max
Input Capacitance 20 20 pF typ

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

IN

Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V

= 2.7 V to 5.25 V, REF IN = 2.5 V, f

DRIVE

68 68 dB min f

−76 −76 dB max f

V

INH

INL

− 1 V

DRIVE

0.4 0.4 V max
±1 ±1 μA max Typically 10 nA, VIN = 0 V or V

2

IN

OH

OL

10 10 pF max

V

DRIVE

0.4 0.4 V max I

= 20 MHz, TA = T

SCLK

1

Unit Test Conditions/Comments

− 1 V min

DRIVE

MIN

to T

MAX

− 0.2 V min I

, unless otherwise noted.

= 300 kHz sine wave, f

IN

= 300 kHz sine wave, f

IN

SAMPLE

SAMPLE

SAMPLE

= 1 MSPS

= 1 MSPS
= 1 MSPS

@ 5 V guaranteed no missed codes to

12 bits (typ @ 3 V)

DRIVE

SOURCE

SINK

= 200 μA; V

= 2.7 V to 5.25 V

DRIVE

Rev. B | Page 3 of 24

AD7475/AD7495

Parameter A Version1B Version

1

Unit Test Conditions/Comments

POWER REQUIREMENTS

V
V
I

DD

DD

DRIVE

3

2.7/5.25 2.7/5.25 V min/max

2.7/5.25 2.7/5.25 V min/max
Digital inputs = 0 V or V

DRIVE

Normal Mode (Static) 750 750 μA typ VDD = 2.7 V to 5.25 V, SCLK on or off
Normal Mode (Operational) 2.1 2.1 mA max VDD = 4.75 V to 5.25 V, f

1.5 1.5 mA max VDD = 2.7 V to 3.6 V, f
Partial Power-Down Mode 450 450 μA typ f

SAMPLE

= 100 kSPS

SAMPLE

SAMPLE

Partial Power-Down Mode 100 100 μA max Static
Full Power-Down Mode 1 1 μA max SCLK on or off
Power Dissipation

Normal Mode (Operational) 10.5 10.5 mW max VDD = 5 V, f

4.5 4.5 mW max VDD = 3 V, f

SAMPLE

SAMPLE

= 1 MSPS

= 1 MSPS
Partial Power-Down (Static) 500 500 μW max VDD = 5 V
300 300 μW max VDD = 3 V
Full Power-Down 5 5 μW max VDD = 5 V

3 3 μW max VDD = 3 V

1

Temperature ranges for A, B versions: −40°C to +85°C.

2

Guaranteed by initial characterization.

3

See the Power vs. Throughput Rate section.

= 1 MSPS

= 1 MSPS

Rev. B | Page 4 of 24

AD7475/AD7495

AD7495 SPECIFICATIONS

VDD = 2.7 V to 5.25 V, V

Table 2.

Parameter A Version

DYNAMIC PERFORMANCE

Signal-to-Noise and Distortion (SINAD) 68 68 dB min fIN = 300 kHz sine wave, f
Total Harmonic Distortion (THD) −75 −75 dB max fIN = 300 kHz sine wave, f
Peak Harmonic or Spurious Noise

(SFDR)

Intermodulation Distortion (IMD)

Second-Order Terms −78 −78 dB typ

Third-Order Terms −78 −78 dB typ
Aperture Delay 10 10 ns typ
Aperture Jitter 50 50 ps typ
Full Power Bandwidth 8.3 8.3 MHz typ @ 3 dB
Full Power Bandwidth 1.3 1.3 MHz typ @ 0.1 dB

DC ACCURACY

Resolution 12 12 Bits
Integral Nonlinearity ±1.5 ±1 LSB max @ 5 V (typ @ 3 V)
±0.5 ±0.5 LSB typ @ 25°C
Differential Nonlinearity +1.5/−0.9 +1.5/−0.9 LSB max

±0.6 ±0.6 LSB typ @ 25°C
Offset Error ±8 ±8 LSB max Typically ±2.5 LSB
Gain Error ±7 ±7 LSB max Typically ±2.5 LSB

ANALOG INPUT

Input Voltage Ranges 0 to 2.5 0 to 2.5 V
DC Leakage Current ±1 ±1 μA max
Input Capacitance 20 20 pF typ

REFERENCE OUTPUT

REF OUT Output Voltage 2.4625/2.5375 2.4625/2.5375 V min/max
REF OUT Impedance 10 10 Ω typ
REF OUT Temperature Coefficient 50 50 ppm/°C typ

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

IN

Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V

= 2.7 V to 5.25 V, f

DRIVE

INH

INL

2

IN

OH

OL

= 20 MHz, TA = T

SCLK

1

B Version

−76 −76 dB max f

MIN

to T

1

unless otherwise noted.

MAX,

Unit Test Conditions/Comments

SAMPLE

SAMPLE

= 300 kHz sine wave, f

IN

SAMPLE

@ 5 V guaranteed no missed codes to

12 bits (typ @ 3 V)

V

− 1 V

DRIVE

− 1 V min

DRIVE

0.4 0.4 V max
±1 ±1 μA max Typically 10 nA, VIN = 0 V or V
10 10 pF max

V

− 0.2 V min I

DRIVE

0.4 0.4 V max I

= 200 μA; VDD = 2.7 V to 5.25 V

SOURCE

SINK

= 1 MSPS
= 1 MSPS
= 1 MSPS

DRIVE

Rev. B | Page 5 of 24

AD7475/AD7495

Parameter A Version

1

B Version

1

Unit Test Conditions/Comments

POWER REQUIREMENTS

V
V
I

DD

DRIVE

DD

2.7/5.25 2.7/5.25 V min/max

2.7/5.25 2.7/5.25 V min/max
Digital inputs = 0 V or V

DRIVE

Normal Mode (Static) 1 1 mA typ VDD = 2.7 V to 5.25 V, SCLK on or off
Normal Mode (Operational) 2.6 2.6 mA max VDD = 4.75 V to 5.25 V, f
2 2 mA max VDD = 2.7 V to 3.6 V, f
Partial Power-Down Mode 650 650 μA typ f

SAMPLE

= 100 kSPS

SAMPLE

SAMPLE

Partial Power-Down Mode 230 230 μA max Static
Full Power-Down Mode 1 1 μA max Static, SCLK on or off

Power Dissipation

Normal Mode (Operational) 13 13 mW max VDD = 5 V, f
6 6 mW max VDD = 3 V, f

3

SAMPLE

SAMPLE

= 1 MSPS

= 1 MSPS
Partial Power-Down (Static) 1.15 1.15 mW max VDD = 5 V
690 690 μW max VDD = 3 V
Full Power-Down 5 5 μW max VDD = 5 V

3 3 μW max VDD = 3 V

1

Temperature ranges for A, B versions: −40°C to +85°C.

2

Guaranteed by initial characterization.

3

See the Power vs. Throughput Rate section.

= 1 MSPS

= 1 MSPS

Rev. B | Page 6 of 24

AD7475/AD7495

MIN

1

, T

Unit Description

MAX

t

ns min SCLK low pulse width
ns min SCLK high pulse width

= 1/f

SCLK

= 20 MHz

SCLK

CS to SCLK setup time
Delay from

CS rising edge to SDATA high impedance

MIN

to T

SCLK

, unless otherwise noted.

MAX

CS until SDATA three-state disabled

) and timed from a voltage level of 1.6 V.

DRIVE

TIMING SPECIFICATIONS

VDD = 2.7 V to 5.25 V, V

Table 3.

Parameter Limit at T

2

f

SCLK

20 MHz max
t

CONVERT

800 ns max f
t

QUIET

t

2

3

t

3

t

4

t

5

t

6

t

7

4

t

8

45 ns max SCLK falling edge to SDATA high impedance
t

9

t

POWER-UP

650 μs max Power-up time from full power-down (AD7495)

1

Guaranteed by initial characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V

2

Mark/space ratio for the SCLK input is 40/60 to 60/40.

3

Measured with the load circuit of Figure 4 and defined as the time required for the output to cross 0.8 V or 2.0 V.

4

t8 and t9 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times, t8 and t9, quoted in the timing characteristics are
the true bus relinquish times of the part and are independent of the bus loading.

= 2.7 V to 5.25 V, REF IN = 2.5 V (AD7475), TA = T

DRIVE

10 kHz min

16 × t

SCLK

100 ns min Minimum quiet time required between conversions
10 ns min

22 ns max
40 ns max Data access time after SCLK falling edge

0.4 t

SCLK

0.4 t

SCLK

10 ns min SCLK to data valid hold time
10 ns min SCLK falling edge to SDATA high impedance

20 ns max
20 μs max Power-up time from full power-down (AD7475)

Rev. B | Page 7 of 24

AD7475/AD7495

TIMING EXAMPLE 1

With f
time is t
is 365 ns. The 365 ns satisfies the requirement of 300 ns for t
In
45 ns. This allows a value of 195 ns for t
minimum requirement of 100 ns.

= 20 MHz and a throughput of 1 MSPS, the cycle

SCLK

+ 12.5(1/f

2

Figure 3, t

ACQ

) + t

SCLK

= 1 μs. With t2 = 10 ns min, t

ACQ

comprises 2.5(1/f

SCLK

) + t8 + t

QUIET

, where t8 =

QUIET

, satisfying the

ACQ

ACQ

TIMING EXAMPLE 2

With f

.

time is t
t

ACQ

t

ACQ

t8 = 45 ns. This allows a value of 119 ns for t
minimum requirement of 100 ns. As in this example and with
other slower clock values, the signal may already be acquired
before the conversion is complete, but it is still necessary
to leave 100 ns minimum t
Example 2, the signal should be fully acquired at approximately
Point C in

= 5 MHz and a throughput of 315 KSPS, the cycle

SCLK

+ 12.5(1/f

2

SCLK

) + t

= 3.174 μs. With t2 = 10 ns min,

ACQ

is 664 ns. The 664 ns satisfies the requirement of 300 ns for
. In Figure 3, t

comprises 2.5(1/f

ACQ

QUIET

) + t8 + t

SCLK

QUIET

, satisfying the

QUIET

between conversions. In

, where

Figure 3.

CS

SCLK

SDATA

THREE-STATE

CS

SCLK

t

CONVERT

t

2

1

t

3

00

FOUR LEADING ZEROS

3

2

0

0

t

6

4

5

t

t

4

DB11 DB10

B

13

7

14

t

DB2

15

16

5

DB1

t

8

DB0

THREE-STATE

t

QUIET

01684-B-002

Figure 2. Serial Interface Timing Diagram

t

CONVERT

4

12.5 (1/f

t

SCLK

6

5

)

B

13

1/THROUGHPUT

C

14

15

16

t

5

t

8

45ns

t

ACQUISITION

t

QUIET

01684-B-003

t

2

10ns

1

3

2

Figure 3. Serial Interface Timing Example

200μA

I

OL

TO OUTPUT

PIN

50pF

C

L

200μA

I

OH

1.6V

01684-B-004

Figure 4. Load Circuit for Digital Output Timing Specifications

Rev. B | Page 8 of 24