Analog Devices AD7472, AD7470 Datasheet

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
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a

AD7470/AD7472

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

1.75 MSPS, 4 mW

10-Bit/12-Bit Parallel ADCs

FUNCTIONAL BLOCK DIAGRAM

T/H

10-/12-BIT

SUCCESSIVE

APPROXIMATION

ADC

OUTPUT

DRIVERS

AD7470/AD7472

V

IN

CONVST

AGND DGND

AV

DDDVDD

REF IN

V

DRIVE

DB9 (DB11)

DB0

CLK IN

CS

RD

BUSY

CONTROL

LOGIC

AD7470 IS A 10-BIT PART WITH DB0 TO DB9 AS OUTPUTS.
AD7472 IS A 12-BIT PART WITH DB0 TO DB11 AS OUTPUTS.

FEATURES
Specified for V

DD

of 2.7 V to 5.25 V

1.75 MSPS for AD7470 (10-Bit)

1.5 MSPS for AD7472 (12-Bit)
Low Power

AD7470: 3.34 mW Typ at 1.5 MSPS with 3 V Supplies

7.97 mW Typ at 1.75 MSPS with 5 V Supplies

AD7472: 3.54 mW Typ at 1.2 MSPS with 3 V Supplies

8.7 mW Typ at 1.5 MSPS with 5 V Supplies
Wide Input Bandwidth
70 dB Typ SNR at 500 kHz Input Frequency
Flexible Power/Throughput Rate Management
No Pipeline Delays
High Speed Parallel Interface
Sleep Mode: 50 nA Typ
24-Lead SOIC and TSSOP Packages

GENERAL DESCRIPTION

The AD7470/AD7472 are 10-bit/12-bit high speed, low power,
successive-approximation ADCs. The parts operate from a
single 2.7 V to 5.25 V power supply and feature throughput rates
up to 1.5 MSPS for the 12-bit AD7472 and up to 1.75 MSPS for
the 10-bit AD7470. The parts contain a low noise, wide band­width track/hold amplifier that can handle input frequencies in
excess of 1 MHz.

The conversion process and data acquisition are controlled
using standard control inputs allowing easy interfacing to
microprocessors or DSPs. The input signal is sampled on the
falling edge of CONVST and conversion is also initiated at
this point. The BUSY goes high at the start of conversion and
goes low 531.66 ns after falling edge of CONVST (AD7472 with
a clock frequency of 26 MHz) to indicate that the conversion is
complete. There are no pipelined delays associated with the part.
The conversion result is accessed via standard CS and RD sig-
nals over a high speed parallel interface.

The AD7470/AD7472 uses advanced design techniques to
achieve very low power dissipation at high throughput rates. With
3 V supplies and 1.5 MSPS throughput rate, the AD7470 typi­cally consumes, on average, just 1.1 mA. With 5 V supplies and

1.75 MSPS, the average current consumption is typically

1.6 mA. The part also offers flexible power/throughput rate
management. Operating the AD7470 with 3 V supplies and
500 kSPS throughput reduces the current consumption to 713 µA.
At 5 V supplies and 500 kSPS, the part consumes 944 µA.

It is also possible to operate the parts in an auto sleep mode,
where the part wakes up to do a conversion and automatically
enters sleep mode at the end of conversion. Using this method
allows very low power dissipation numbers at lower throughput
rates. In this mode, the AD7472 can be operated with 3 V sup­plies at 100 kSPS, and consume an average current of just 124 µA.
At 5 V supplies and 100 kSPS, the average current consumption
is 171 µA.

The analog input range for the part is 0 to REF IN. The +2.5 V
reference is applied externally to the REF IN pin. The conver­sion rate is determined by the externally-applied clock.

PRODUCT HIGHLIGHTS

1. High Throughput with Low Power Consumption. The
AD7470 offers 1.75 MSPS throughput and the AD7472
offers 1.5 MSPS throughput rates with 4 mW power
consumption.

2. Flexible Power/Throughput Rate Management. The conver­sion rate is determined by an externally-applied clock allow­ing the power to be reduced as the conversion rate is reduced.
The part also features an auto sleep mode to maximize power
efficiency at lower throughput rates.

3. No Pipeline Delay. The part features a standard successive­approximation ADC with accurate control of the sampling
instant via a CONVST input and once off conversion
control.

REV. A

AD7470/AD7472

–2–

AD7470–SPECIFICATIONS

1

(VDD = +2.7 V to +5.25 V2, REF IN = 2.5 V, f

CLK IN

= 30 MHz @ 5 V and 24 MHz @ 3 V;

TA = T

MIN

to T

MAX

3

, unless otherwise noted.)

Parameter A Version

1

Units Test Conditions/Comments

DYNAMIC PERFORMANCE 5 V 3 V f

S

= 1.75 MSPS @ 5 V, fS = 1.5 MSPS @ 3 V

Signal to Noise + Distortion (SINAD) 60 60 dB min fIN = 500 kHz Sine Wave

60 60 fIN = 100 kHz Sine Wave

Signal-to-Noise Ratio (SNR) 60 60 dB min fIN = 500 kHz Sine Wave

60 60 fIN = 100 kHz Sine Wave

Total Harmonic Distortion (THD) –83 –83 dB typ f

IN

= 500 kHz Sine Wave

–75 –75 dB max fIN = 100 kHz Sine Wave

Peak Harmonic or Spurious Noise (SFDR) –85 –85 dB typ fIN = 500 kHz Sine Wave

–75 –75 dB max f

IN

= 100 kHz Sine Wave

Intermodulation Distortion (IMD)

Second Order Terms –79 –75 dB typ fIN = 500 kHz Sine Wave

–75 –75 dB max fIN = 100 kHz Sine Wave

Third Order Terms –77 –75 dB typ fIN = 500 kHz Sine Wave

–75 –75 dB max fIN = 100 kHz Sine Wave
Aperture Delay 5 5 ns typ
Aperture Jitter 15 15 ps typ
Full Power Bandwidth 20 20 MHz typ

DC ACCURACY fS = 1.75 MSPS @ 5 V; fS = 1.5 MSPS @ 3 V

Resolution 10 10 Bits
Integral Nonlinearity ± 1 ±1 LSB max
Differential Nonlinearity ± 0.9 ±0.9 LSB max Guaranteed No Missed Codes to 10 Bits
Offset Error ± 2.5 ±2.5 LSB max
Gain Error ± 1 ±1 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to REF IN 0 to REF IN V
DC Leakage Current ±1 ±1 µA max
Input Capacitance 33 33 pF typ

REFERENCE INPUT

REF IN Input Voltage Range 2.5 2.5 V ± 1% for Specified Performance
DC Leakage Current ±1 ±1 µA max
Input Capacitance 10/20 10/20 pF typ Track/Hold Mode

LOGIC INPUTS

Input High Voltage, V

INH

2.4 2.4 V min

Input Low Voltage, V

INL

0.4 0.4 V max

Input Current, I

IN

± 1 ±1 µA max Typically 10 nA, VIN = 0 V or V

DD

Input Capacitance, C

IN

4

10 10 pF max

LOGIC OUTPUTS

Output High Voltage, V

OH

V

DRIVE

– 0.2 V

DRIVE

– 0.2 V min I

SOURCE

= 200 µA

Output Low Voltage, V

OL

0.4 0.4 V max I

SINK

= 200 µA
Floating-State Leakage Current ± 10 ± 10 µA max VDD = 2.7 V to 5.25 V
Floating-State Output Capacitance 10 10 pF max
Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 12 12 CLK IN Cycles (max)
Track/Hold Acquisition Time 135 135 ns min
Throughput Rate 1.75 1.5 MSPS max Conversion Time + Acquisition Time

CLK IN of 30 MHz @ 5 V and 24 MHz @ 3 V

POWER REQUIREMENTS

V

DD

+2.7/+5.25 V min/max

I

DD

5

Digital I/Ps = 0 V or DV

DD

Normal Mode 2.4 mA max VDD = 4.75 V to 5.25 V; fS = 1.75 MSPS; Typ 2 mA
Quiescent Current 900 µA max VDD = 4.75 V to 5.25 V; fS = 1.75 MSPS
Normal Mode 1.5 mA max VDD = 2.7 V to 3.3 V; fS = 1.5 MSPS; Typ 1.3 mA
Quiescent Current 800 µA max VDD = 2.7 V to 3.3 V; fS = 1.5 MSPS
Sleep Mode 1 µA max CLK IN = 0 V or DV

DD

Power Dissipation

5

Digital I/Ps = 0 V or DV

DD

Normal Mode 12 mW max VDD = 5 V

4.5 mW max VDD = 3 V

Sleep Mode 5 µW max VDD = 5 V; CLK IN = 0 V or DV

DD

3 µW max VDD = 3 V; CLK IN = 0 V or DV

DD

NOTES

1

Temperature ranges as follows: A Version: -40°C to +85°C.

2

The AD7470 functionally works at 2.35 V. Typical specifications @ +25°C for SNR (100 kHz) = 59 dB; THD (100 kHz) = –84 dB; INL ± 0.8 LSB.

3

The AD7470 will typically maintain A-grade performance up to +125°C, with a reduced CLK of 20 MHz @ 5 V and 16 MHz @ 3 V. Typical Sleep Mode current @ +125°C is 700 nA.

4

Sample tested @ +25°C to ensure compliance.

5

See Power vs. Throughput Rate section.

Specifications subject to change without notice.

REV. A –3–

AD7470/AD7472

AD7472–SPECIFICATIONS

1

(VDD = +2.7 V to +5.25 V2, REF IN = 2.5 V, f

CLK IN

= 26 MHz @ 5 V and 20 MHz @ 3 V;

TA = T

MIN

to T

MAX

3

, unless otherwise noted.)

Parameter A Version

1

B Version

1

Units Test Conditions/Comments

DYNAMIC PERFORMANCE 5 V3 V 5 V3 V f

S

= 1.5 MSPS @ 5 V, fS = 1.2 MSPS @ 3 V

Signal to Noise + Distortion (SINAD) 69 69 69 69 dB typ fIN = 500 kHz Sine Wave

68 68 68 68 dB min f

IN

= 100 kHz Sine Wave

Signal-to-Noise Ratio (SNR) 70 70 70 70 dB typ f

IN

= 500 kHz Sine Wave

68 68 68 68 dB min fIN = 100 kHz Sine Wave

Total Harmonic Distortion (THD) –83 –78 –83 –78 dB typ fIN = 500 kHz Sine Wave

–83 –84 –83 –84 dB typ f

IN

= 100 kHz Sine Wave

–75 –75 –75 –75 dB max f

IN

= 100 kHz Sine Wave

Peak Harmonic or Spurious Noise

(SFDR) –86 –81 –86 –81 dB typ fIN = 500 kHz Sine Wave

–86 –86 –86 –86 dB typ fIN = 100 kHz Sine Wave
–76 –76 –76 –76 dB max fIN = 100 kHz Sine Wave

Intermodulation Distortion (IMD)

Second Order Terms –77 –77 –77 –77 dB typ fIN = 500 kHz Sine Wave

–86 –86 –86 –86 dB typ fIN = 100 kHz Sine Wave

Third Order Terms –77 –77 –77 –77 dB typ fIN = 500 kHz Sine Wave

–86 –86 –86 –86 dB typ fIN = 100 kHz Sine Wave
Aperture Delay 5 5 5 5 ns typ
Aperture Jitter 15 15 15 15 ps typ
Full Power Bandwidth 20 20 20 20 MHz typ

DC ACCURACY fS = 1.5 MSPS @ 5 V; fS = 1.2 MSPS @ 3 V

Resolution 12 12 12 12 Bits
Integral Nonlinearity ± 2 ± 2 ± 1 ± 1 LSB max Guaranteed No Missed Codes to 11 Bits

(A Version)

Differential Nonlinearity ± 1.8 ±1.8 ± 0.9 ± 0.9 LSB max Guaranteed No Missed Codes to 12 Bits

(B Version)
Offset Error ± 10 ±10 ± 10 ±10 LSB max
Gain Error ± 2 ± 2 ± 2 ± 2 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to REF IN 0 to REF IN 0 to REF IN 0 to REF IN V
DC Leakage Current ±1 ± 1 ±1 ±1 µA max
Input Capacitance 33 33 33 33 pF typ

REFERENCE INPUT

REF IN Input Voltage Range 2.5 2.5 2.5 2.5 V ± 1% for Specified Performance
DC Leakage Current ± 1 ± 1 ±1 ±1 µA max
Input Capacitance 10/20 10/20 10/20 10/20 pF typ Track/Hold Mode

LOGIC INPUTS

Input High Voltage, V

INH

2.4 2.4 2.4 2.4 V min

Input Low Voltage, V

INL

0.4 0.4 0.4 0.4 V max

Input Current, I

IN

±1 ±1 ± 1 ±1 µA max Typically 10 nA, VIN = 0 V or V

DD

Input Capacitance, C

IN

4

10 10 10 10 pF max

LOGIC OUTPUTS

Output High Voltage, V

OH

V

DRIVE

– 0.2 V

DRIVE

– 0.2 V

DRIVE

– 0.2 V

DRIVE

– 0.2 V min I

SOURCE

= 200 µA

Output Low Voltage, V

OL

0.4 0.4 0.4 0.4 V max I

SINK

= 200 µA
Floating-State Leakage Current ±10 ±10 ±10 ± 10 µA max VDD = 2.7 V to 5.25 V
Floating-State Output Capacitance 10 10 10 10 pF max
Output Coding Straight (Natural) Binary Straight (Natural) Binary

CONVERSION RATE

Conversion Time 14 14 14 14 CLK IN

Cycles (max)
Track/Hold Acquisition Time 135 135 135 135 ns min
Throughput Rate 1.5 1.2 1.5 1.2 MSPS max Conversion Time + Acquisition Time

CLK IN Is 26 MHz @ 5 V and 20 MHz @ 3 V

POWER REQUIREMENTS

V

DD

+2.7/+5.25 +2.7/+5.25 V min/max

I

DD

5

Digital I/Ps = 0 V or DV

DD

Normal Mode 2.4 2.4 mA max VDD = 4.75 V to 5.25 V; fS = 1.5 MSPS; Typ 2 mA
Quiescent Current 900 900 µA max VDD = 4.75 V to 5.25 V; fS = 1.5 MSPS
Normal Mode 1.5 1.5 mA max VDD = 2.7 V to 3.3 V; fS = 1.2 MSPS; Typ 1.3 mA
Quiescent Current 800 800 µAV

DD

= 2.7 V to 3.3 V; fS = 1.2 MSPS

Sleep Mode 1 1 µA max CLK IN = 0 V or DV

DD

Power Dissipation

5

Digital I/Ps = 0 V or DV

DD

Normal Mode 12 12 mW max VDD = 5 V

4.5 4.5 mW max VDD = 3 V

Sleep Mode 5 5 µW max VDD = 5 V; CLK IN = 0 V or DV

DD

33µW max VDD = 3 V; CLK IN = 0 V or DV

DD

NOTES

1

Temperature ranges as follows: A and B Versions: –40°C to +85°C.

2

The AD7472 functionally works at 2.35 V. Typical specifications @ +25°C for SNR (100 kHz) = 68 dB; THD (100 kHz) = –84 dB; INL ± 0.8 LSB.

3

The AD7472 will typically maintain A-grade performance up to +125°C, with a reduced CLK of 18 MHz @ 5 V and 14 MHz @ 3 V. Typical Sleep Mode current @ +125°C is 700 nA.

4

Sample tested @ +25°C to ensure compliance.

5

See Power vs. Throughput Rate section.

Specifications subject to change without notice.

REV. A

AD7470/AD7472

–4–

Limit at T

MIN

, T

MAX

Parameter AD7470 AD7472 Units Description

f

CLK

2

10 10 kHz min
30 26 MHz max

t

CONVERT

436.42 531.66 ns min t

CLK

= 1/f

CLK IN

t

WAKEUP

11µs max Wake-Up Time

t

1

10 10 ns min CONVST Pulsewidth

t

2

3

10 10 ns max CONVST to BUSY Delay, VDD = 5 V
30 30 ns max CONVST to BUSY Delay, V

DD

= 3 V

t

3

0 0 ns max BUSY to CS Setup Time

t

4

4

0 0 ns max CS to RD Setup Time

t

5

20 20 ns min RD Pulsewidth

t

6

4

15 15 ns min Data Access Time After Falling Edge of RD

t

7

5

8 8 ns max Bus Relinquish Time After Rising Edge of RD

t

8

0 0 ns max CS to RD Hold Time

t

9

135 135 ns min Acquisition Time

t

10

100 100 ns min Quiet Time

NOTES

1

Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See
Figure 1.

2

Mark/Space ratio for the CLK input is 40/60 to 60/40. First CLK pulse should be 10 ns min from falling edge of CONVST.

3

t2 is 35 ns max @ +125°C.

4

Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.

5

t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t

7

, quoted in the timing characteristics is the true bus relinquish

time of the part and is independent of the bus loading.

Specifications subject to change without notice.

TIMING SPECIFICATIONS

1

(VDD = +2.7 V to +5.25 V, REF IN = 2.5 V; TA = T

MIN

to T

MAX

, unless otherwise noted.)

200␮A

I

OL

200␮A

I

OH

C

L

50pF

TO OUTPUT

PIN

+1.6V

Figure 1. Load Circuit for Digital Output Timing Specifications

REV. A

AD7470/AD7472

–5–

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7470/AD7472 features proprietary ESD protection circuitry, permanent dam­age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

1

(TA = +25°C unless otherwise noted)

AV

DD

to AGND/DGND . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV

DD

to AGND/DGND . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V

DRIVE

to AGND/DGND . . . . . . . . . . . . . . . . –0.3 V to +7 V

AV

DD

to DVDD . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V

V

DRIVE

to DVDD . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V

AGND TO DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Analog Input Voltage to AGND . . . –0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . . –0.3 V to DVDD + 0.3 V

REF IN to AGND . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V

Input Current to Any Pin Except Supplies

2

. . . . . . . . ± 10 mA

Operating Temperature Range

Commercial (A and B Version) . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

SOIC, TSSOP Package Dissipation . . . . . . . . . . . . . +450 mW

θ

JA

Thermal Impedance . . . . . . . . . . . . . . . 75°C/W (SOIC)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115°C/W (TSSOP)

θ

JC

Thermal Impedance . . . . . . . . . . . . . . . 25°C/W (SOIC)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35°C/W (TSSOP)

Lead Temperature, Soldering

Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . .+215°C

Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

ORDERING GUIDE

Temperature Resolution Package

Model Range (Bits) Options

1

AD7470ARU –40°C to +85°C 10 RU-24
AD7472AR –40°C to +85°C 12 R-24
AD7472BR –40°C to +85°C 12 R-24
AD7472ARU –40°C to +85°C 12 RU-24
AD7472BRU –40°C to +85°C 12 RU-24
EVAL-AD7470CB

2

Evaluation Board

EVAL-AD7472CB

2

Evaluation Board

EVAL-CONTROL BOARD

3

Controller Board

HSC-INTERFACE BOARD Evaluation High Speed Interface Board

NOTES

1

R = SOIC; RU = TSSOP.

2

This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.

3

This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

PIN CONFIGURATIONS

TOP VIEW

(Not to Scale)

24

23

22

21

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

9

10

11

12

AD7470

NC = NO CONNECT

DB7 DB6

DB8 DB5

(MSB) DB9 DB4

AV

DD

V

DRIVE

REF IN DV

DD

V

IN

DGND

AGND DB3

CS

DB2

RD

DB1

CONVST

DB0 (LSB)

CLKIN NC

BUSY NC

TOP VIEW

(Not to Scale)

24

23

22

21

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

9

10

11

12

AD7472

DB9 DB8

DB10 DB7

(MSB) DB11 DB6

AV

DD

V

DRIVE

REF IN DV

DD

V

IN

DGND

AGND DB5

CS

DB4

RD

DB3

CONVST

DB2

CLKIN DB1

BUSY DB0 (LSB)