ANALOG DEVICES AD7468 Service Manual

V

www.BDTIC.com/ADI

1.6 V, Micropower 12-/10-/8-Bit ADCs

FEATURES

Specified for V
Low power:

0.62 mW typical at 100 kSPS with 3 V supplies

0.48 mW typical at 50 kSPS with 3.6 V supplies

0.12 mW typical at 100 kSPS with 1.6 V supplies
Fast throughput rate: 200 kSPS
Wide input bandwidth:
71 dB SNR at 30 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface:
SPI/QSPI™/MICROWIRE™/DSP compatible
Automatic power-down
Power-down mode: 8 nA typical
6-lead SOT-23 package
8-lead MSOP package

APPLICATIONS

Battery-powered systems
Medical instruments
Remote data acquisition
Isolated data acquisition

of 1.6 V to 3.6 V

DD

AD7466/AD7467/AD7468

FUNCTIONAL BLOCK DIAGRAM

V

DD

12-/10-/8-BIT

T/H

IN

SUCCESSIVE

APPROXIMATION

ADC

CONTROL

LOGIC

AD7466/AD7467/AD7468

GND

Figure 1.

SCLK
SDATA
CS

02643-001

GENERAL DESCRIPTION

The AD7466/AD7467/AD74681 are 12-/10-/8-bit, high speed,
low power, successive approximation analog-to-digital
converters (ADCs), respectively. The parts operate from a single

1.6 V to 3.6 V power supply and feature throughput rates up to
200 kSPS with low power dissipation. The parts contain a low
noise, wide bandwidth track-and-hold amplifier, which can
handle input frequencies in excess of 3 MHz.

The conversion process and data acquisition are controlled

CS

usin

g

and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of
point. There are no pipeline delays associated with the part.

The reference for the part is taken internally from V
allows the widest dynamic input range to the ADC. Thus, the
analog input range for the part is 0 V to V
rate is determined by the SCLK.

1

Protected by U.S. Patent No. 6,681,332.

CS

, and the conversion is also initiated at this

. This

DD

. The conversion

DD

PRODUCT HIGHLIGHTS

1. Specified for supply voltages of 1.6 V to 3.6 V.

2. 12-, 10-, an

igh throughput rate with low power consumption.

3. H

Power consumption in normal mode of operation at
100 kSPS and 3 V is 0.9 mW maximum.

4. Flexi

The conversion rate is determined by the serial clock,
allowing the conversion time to be reduced through
increases in the serial clock speed. Automatic power-down
after conversion allows the average power consumption to
be reduced when in power-down. Current consumption is

0.1 μA maximum and 8 nA typically when in power-down.

5. Refer

6. No

pipeline delay.

he part features a standard successive approximation

7. T

ADC with accurate control of conversions via a

d 8-bit ADCs in SOT-23 and MSOP packages.

ble power/serial clock speed management.

ence derived from the power supply.

CS

input.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2003–2007 Analog Devices, Inc. All rights reserved.

AD7466/AD7467/AD7468

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TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram ..............................................................1

General Description......................................................................... 1

Product Highlights........................................................................... 1

Revision History ...............................................................................2

Specifications..................................................................................... 3

AD7466.......................................................................................... 3

AD7467.......................................................................................... 5

AD7468.......................................................................................... 7

Timing Specifications ..................................................................9

Timing Examples........................................................................ 10

Absolute Maximum Ratings.......................................................... 11

ESD Caution................................................................................ 11

Pin Configurations and Function Descriptions......................... 12

Typical Performance Characteristics........................................... 13

Dynamic Performance Curves .................................................13

DC Accuracy Curves ................................................................. 13

Power Requirement Curves ......................................................13

Terminology.................................................................................... 16

Theory of Operation ......................................................................17

Circuit Information.................................................................... 17

Converter Operation.................................................................. 17

ADC Transfer Function............................................................. 17

Typical Connection Diagram ...................................................17

Analog Input............................................................................... 18

Digital Inputs.............................................................................. 18

Normal Mode.............................................................................. 19

Power Consumption.................................................................. 20

Serial Interface ................................................................................ 22

Microprocessor Interfacing....................................................... 23

Application Hints ...........................................................................25

Grounding and Layout.............................................................. 25

Evaluating the Performance of the AD7466 and AD7467.... 25

Outline Dimensions....................................................................... 26

Ordering Guide .......................................................................... 27

REVISION HISTORY

5/07—Rev. B to Rev. C

Deleted Figure 3.............................................................................. 10

Updated Outline Dimensions....................................................... 26

Changes to Ordering Guide.......................................................... 27

4/05—Rev. A to Rev. B

Moved Terminology Section......................................................... 16

C

hanges to Ordering Guide.......................................................... 27

11/04—Rev. 0 to Rev. A

Updated Format..................................................................Universal

hanges to General Description .................................................... 1

C

Added Patent Number..................................................................... 1

Updated Outline Dimensions....................................................... 26

Changes to Ordering Guide.......................................................... 27

5/03—Revision 0: Initial Version

Rev. C | Page 2 of 28

AD7466/AD7467/AD7468

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SPECIFICATIONS

AD7466

VDD = 1.6 V to 3.6 V, f
The temperature range for the B version is −40°C to +85°C.

Table 1.

Parameter B Version Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 30 kHz sine wave

Signal-to-Noise and Distortion (SINAD) 69 dB min 1.8 V ≤ VDD ≤ 2 V; see the Terminology section
70 dB min 2.5 V ≤ VDD ≤ 3.6 V
70 dB typ VDD = 1.6 V
Signal-to-Noise Ratio (SNR) 70 dB min 1.8 V ≤ VDD ≤ 2 V; see the Terminology section
71 dB typ 1.8 V ≤ VDD ≤ 2 V
71 dB min 2.5 V ≤ VDD ≤ 3.6 V

70.5 dB typ VDD = 1.6 V
Total Harmonic Distortion (THD) −83 dB typ See the Terminology section
Peak Harmonic or Spurious Noise (SFDR) −85 dB typ See the Terminology section
Intermodulation Distortion (IMD)

Second-Order Terms −84 dB typ

Third-Order Terms −86 dB typ
Aperture Delay 10 ns typ
Aperture Jitter 40 ps typ
Full Power Bandwidth 3.2 MHz typ @ 3 dB, 2.5 V ≤ VDD ≤ 3.6 V

1.9 MHz typ @ 3 dB, 1.6 V ≤ VDD ≤ 2.2 V
750 kHz typ @ 0.1 dB, 2.5 V ≤ VDD ≤ 3.6 V

450 kHz typ @ 0.1 dB, 1.6 V ≤ VDD ≤ 2.2 V
DC ACCURACY

Resolution 12 Bits
Integral Nonlinearity ±1.5 LSB max See the Terminology section
Differential Nonlinearity −0.9/+1.5 LSB max

Offset Error ±1 LSB max See the Terminology section
Gain Error ±1 LSB max See the Terminology section
Total Unadjusted Error (TUE) ±2 LSB max See the Terminology section

ANALOG INPUT

Input Voltage Ranges 0 to VDD V
DC Leakage Current ±1 μA max
Input Capacitance 20 pF typ

LOGIC INPUTS

Input High Voltage, V
2 V min 2.7 V ≤ VDD ≤ 3.6 V
Input Low Voltage, V

0.3 × VDD V max 1.8 V ≤ VDD < 2.7 V

0.8 V max 2.7 V ≤ VDD ≤ 3.6 V
Input Current, IIN, SCLK Pin ±1 μA max Typically 20 nA, VIN = 0 V or VDD
Input Current, IIN, CS Pin
Input Capacitance, CIN 10 pF max Sample tested at 25°C to ensure compliance

= 3.4 MHz, f

SCLK

0.7 × VDD V min 1.6 V ≤ VDD < 2.7 V

INH

0.2 × VDD V max 1.6 V ≤ VDD < 1.8 V

INL

= 100 kSPS, unless otherwise noted. TA = T

SAMPLE

±1 μA t

yp

to T

MIN

fa = 29.1 kHz, fb = 29.9 kHz; see the Terminology

tion

sec

Maximum specifications apply as typical figures when

= 1.6 V

V

DD

Guaranteed no missed codes to 12 bits; see the
Terminology section

, unless otherwise noted.

MAX

Rev. C | Page 3 of 28

AD7466/AD7467/AD7468

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Parameter B Version Unit Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage, VOH V
Output Low Voltage, VOL 0.2 V max I
Floating-State Leakage Current ±1 μA max
Floating-State Output Capacitance 10 pF max
Output Coding

CONVERSION RATE

Conversion Time 4.70 μs max 16 SCLK cycles with SCLK at 3.4 MHz
Throughput Rate 200 kSPS max See the Serial Interface section

POWER REQUIREMENTS

VDD 1.6/3.6 V min/max
IDD Digital inputs = 0 V or VDD

Normal Mode (Operational) 300 μA max VDD = 3 V, f
110 μA typ VDD = 3 V, f
20 μA typ VDD = 3 V, f
240 μA max VDD = 2.5 V, f
80 μA typ VDD = 2.5 V, f
16 μA typ VDD = 2.5 V, f
165 μA max VDD = 1.8 V, f
50 μA typ VDD = 1.8 V, f
10 μA typ VDD = 1.8 V, f

Power-Down Mode 0.1 μA max SCLK on or off, typically 8 nA
Power Dissipation See the Power Consumption section

Normal Mode (Operational) 0.9 mW max VDD = 3 V, f

0.6 mW max VDD = 2.5 V, f

0.3 mW max VDD = 1.8 V, f

Power-Down Mode 0.3 μW max VDD = 3 V

− 0.2 V min I

DD

Straight (natural)

y

binar

= 200 μA, VDD = 1.6 V to 3.6 V

SOURCE

= 200 μA

SINK

= 100 kSPS

SAMPLE

= 50 kSPS

SAMPLE

= 10 kSPS

SAMPLE

= 100 kSPS

SAMPLE

= 50 kSPS

SAMPLE

= 10 kSPS

SAMPLE

= 100 kSPS

SAMPLE

= 50 kSPS

SAMPLE

= 10 kSPS

SAMPLE

= 100 kSPS

SAMPLE

= 100 kSPS

SAMPLE

= 100 kSPS

SAMPLE

Rev. C | Page 4 of 28

AD7466/AD7467/AD7468

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AD7467

VDD = 1.6 V to 3.6 V, f

The temperature range for the B version is −40°C to +85°C.

Table 2.

Parameter B Version Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal-to-Noise and Distortion (SINAD) 61 dB min See the Terminology section
Total Harmonic Distortion (THD) −72 dB max See the Terminology section
Peak Harmonic or Spurious Noise (SFDR) −74 dB max See the Terminology section

Intermodulation Distortion (IMD) fa = 29.1 kHz, fb = 29.9 kHz; see the Terminology section
Second-Order Terms −83 dB typ
Third-Order Terms −83 dB typ

Aperture Delay 10 ns typ

Aperture Jitter 40 ps typ

Full Power Bandwidth 3.2 MHz typ @ 3 dB, 2.5 V ≤ VDD ≤ 3.6 V

1.9 MHz typ @ 3 dB, 1.6 V ≤ VDD ≤ 2.2 V

750 kHz typ @ 0.1 dB, 2.5 V ≤ VDD ≤ 3.6 V
450 kHz typ @ 0.1 dB, 1.6 V ≤ VDD ≤ 2.2 V
DC ACCURACY

Resolution 10 Bits

Integral Nonlinearity ±0.5 LSB max See the Terminology section

Differential Nonlinearity ±0.5 LSB max

Offset Error ±0.2 LSB max See the Terminology section

Gain Error ±0.2 LSB max See the Terminology section

Total Unadjusted Error (TUE) ±1 LSB max See the Terminology section
ANALOG INPUT

Input Voltage Ranges 0 to VDD V

DC Leakage Current ±1 μA max

Input Capacitance 20 pF typ
LOGIC INPUTS

Input High Voltage, V

2 V min 2.7 V ≤ VDD ≤ 3.6 V

Input Low Voltage, V

0.3 × VDD V max 1.8 V ≤V DD < 2.7 V

0.8 V max 2.7 V ≤ VDD ≤ 3.6 V

Input Current, IIN, SCLK Pin ±1 μA max Typically 20 nA, VIN = 0 V or VDD

Input Current, IIN, CS Pin

Input Capacitance, CIN 10 pF max Sample tested at 25°C to ensure compliance
LOGIC OUTPUTS

Output High Voltage, VOH V

Output Low Voltage, VOL 0.2 V max I

Floating-State Leakage Current ±1 μA max

Floating-State Output Capacitance 10 pF max Sample tested at 25°C to ensure compliance

Output Coding

CONVERSION RATE

Conversion Time 3.52 μs max 12 SCLK cycles with SCLK at 3.4 MHz

Throughput Rate 275 kSPS max See the Serial Interface section

= 3.4 MHz, f

SCLK

0.7 × VDD V min 1.6 V ≤ VDD < 2.7 V

INH

0.2 × VDD V max 1.6 V ≤ VDD < 1.8 V

INL

= 100 kSPS, unless otherwise noted. TA = T

SAMPLE

±1 μA t

− 0.2 V min I

DD

Straight (natural)

y

binar

yp

MIN

Maximum/minimum specifications apply as typical figures
when V

Maximum specifications apply as typical figures when
V

DD

Guaranteed no missed codes to 10 bits; see the
Terminology section

SOURCE

SINK

= 1.6 V, fIN = 30 kHz sine wave

DD

= 1.6 V

= 200 μA, VDD = 1.6 V to 3.6 V

= 200 μA

to T

, unless otherwise noted.

MAX

Rev. C | Page 5 of 28

AD7466/AD7467/AD7468

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Parameter B Version Unit Test Conditions/Comments

POWER REQUIREMENTS

VDD 1.6/3.6 V min/max
IDD Digital inputs = 0 V or VDD

Normal Mode (Operational) 210 μA max VDD = 3 V, f
170 μA max VDD = 2.5 V, f
140 μA max VDD = 1.8 V, f

Power-Down Mode 0.1 μA max SCLK on or off, typically 8 nA
Power Dissipation See the Power Consumption section

Normal Mode (Operational) 0.63 mW max VDD = 3 V, f

0.42 mW max VDD = 2.5 V, f

0.25 mW max VDD = 1.8 V, f

Power-Down Mode 0.3 μW max VDD = 3 V

= 100 kSPS

SAMPLE

SAMPLE

SAMPLE

= 100 kSPS

SAMPLE

SAMPLE

SAMPLE

= 100 kSPS
= 100 kSPS

= 100 kSPS
= 100 kSPS

Rev. C | Page 6 of 28

AD7466/AD7467/AD7468

www.BDTIC.com/ADI

AD7468

VDD = 1.6 V to 3.6 V, f
The temperature range for the B version is −40°C to +85°C.

Table 3.

Parameter B Version Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal-to-Noise and Distortion (SINAD) 49 dB min See the Terminology section
Total Harmonic Distortion (THD) −66 dB max See the Terminology section
Peak Harmonic or Spurious Noise

(SFDR)

Intermodulation Distortion (IMD) fa = 29.1 kHz, fb = 29.9 kHz; see the Terminology section
Second-Order Terms −77 dB typ
Third-Order Terms −77 dB typ

Aperture Delay 10 ns typ

Aperture Jitter 40 ps typ

Full Power Bandwidth 3.2 MHz typ @ 3 dB, 2.5 V ≤ VDD ≤ 3.6 V

1.9 MHz typ @ 3 dB, 1.6 V ≤ VDD ≤ 2.2 V
750 kHz typ @ 0.1 dB, 2.5 V ≤ VDD ≤ 3.6 V
450 kHz typ @ 0.1 dB, 1.6 V ≤ VDD ≤ 2.2 V

DC ACCURACY

Resolution 8 Bits

Integral Nonlinearity ±0.2 LSB max See the Terminology section

Differential Nonlinearity ±0.2 LSB max

Offset Error ±0.1 LSB max See the Terminology section

Gain Error ±0.1 LSB max See the Terminology section

Total Unadjusted Error (TUE) ±0.3 LSB max See the Terminology section
ANALOG INPUT

Input Voltage Ranges 0 to VDD V

DC Leakage Current ±1 μA max

Input Capacitance 20 pF typ
LOGIC INPUTS

Input High Voltage, V

2 V min 2.7 V ≤ VDD ≤ 3.6 V

Input Low Voltage, V

0.3 × VDD V max 1.8 V ≤ VDD < 2.7 V

0.8 V max 2.7 V ≤ VDD ≤ 3.6 V

Input Current, IIN, SCLK Pin ±1 μA max Typically 20 nA, VIN = 0 V or VDD

Input Current, IIN, CS Pin

Input Capacitance, CIN 10 pF max Sample tested at 25°C to ensure compliance
LOGIC OUTPUTS

Output High Voltage, VOH V

Output Low Voltage, VOL 0.2 V max I

Floating-State Leakage Current ±1 μA max

Floating-State Output Capacitance 10 pF max Sample tested at 25°C to ensure compliance

Output Coding

CONVERSION RATE

Conversion Time 2.94 μs max 10 SCLK cycles with SCLK at 3.4 MHz

Throughput Rate 320 kSPS max See the Serial Interface section

= 3.4 MHz, f

SCLK

0.7 × VDD V min 1.6 V ≤ VDD < 2.7 V

INH

0.2 × VDD V max 1.6 V ≤ VDD < 1.8 V

INL

= 100 kSPS, unless otherwise noted. TA = T

SAMPLE

Maximum/minimum specifications apply as typical figures
when V

−66 dB max See the Terminology section

Maximum specifications apply as typical figures when
V

Guaranteed no missed codes to 8 bits; see the Terminology
sec

±1 μA t

− 0.2 V min I

DD

Straight (natural)

y

binar

yp

SOURCE

SINK

= 1.6 V, fIN = 30 kHz sine wave

DD

= 1.6 V

DD

tion

= 200 μA; VDD = 1.6 V to 3.6 V

= 200 μA

MIN

to T

, unless otherwise noted.

MAX

Rev. C | Page 7 of 28

AD7466/AD7467/AD7468

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Parameter B Version Unit Test Conditions/Comments

POWER REQUIREMENTS

VDD 1.6/3.6 V min/max
IDD Digital inputs = 0 V or VDD

Normal Mode (Operational) 190 μA max VDD = 3 V, f
155 μA max VDD = 2.5 V, f
120 μA max VDD = 1.8 V, f
Power-Down Mode 0.1 μA max SCLK on or off, typically 8 nA

Power Dissipation See the Power Consumption section

Normal Mode (Operational) 0.57 mW max VDD = 3 V, f

0.4 mW max VDD = 2.5 V, f

0.2 mW max VDD = 1.8 V, f
Power-Down Mode 0.3 μW max VDD = 3 V

SAMPLE

SAMPLE

SAMPLE

SAMPLE

SAMPLE

SAMPLE

= 100 kSPS

= 100 kSPS
= 100 kSPS

= 100 kSPS

= 100 kSPS
= 100 kSPS

Rev. C | Page 8 of 28

AD7466/AD7467/AD7468

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TIMING SPECIFICATIONS

For all devices, VDD = 1.6 V to 3.6 V; TA = T
signals are specified with tr = tf = 5 ns (10% to 90% of V

Table 4.

Parameter Limit at T

f

3.4 MHz max Mark/space ratio for the SCLK input is 40/60 to 60/40.

SCLK

MIN

, T

Unit Description

MAX

10 kHz min 1.6 V ≤ VDD ≤ 3 V; minimum f
20 kHz min VDD = 3.3 V; minimum f
150 kHz min VDD = 3.6 V; minimum f
t

16 × t

CONVER T

12 × t
10 × t

AD7466.

SCLK

AD7467.

SCLK

AD7468.

SCLK

Acquisition Time

780 ns max VDD = 1.6 V.
640 ns max 1.8 V ≤ VDD ≤ 3.6 V.
t

10 ns min

QUIET

t1 10 ns min
t2 55 ns min

t3 55 ns max

t4 140 ns max

t5 0.4 t
t6 0.4 t

ns min SCLK low pulse width.

SCLK

ns min SCLK high pulse width.

SCLK

t7 10 ns min

t8 60 ns max

7 ns min SCLK falling edge to SDATA three-state.

MIN

to T

, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input

MAX

) and timed from a voltage level of 1.4 V.

DD

at which specifications are guaranteed.

SCLK

at which specifications are guaranteed.

SCLK

at which specifications are guaranteed.

SCLK

Acquisition time/power-up time from power-down. See the Terminology section.

quisition time is the time required for the part to acquire a full-scale step

The ac
input value within ±1 LSB or a 30 kHz ac input value within ±0.5 LSB.

Minimum quiet time required between bus relinquish and the start of the next

nversion.

co
Minimum CS

to SCLK setup time. If VDD = 1.6 V and f

CS

pulse width.

= 3.4 MHz, t2 has to be 192 ns

SCLK

minimum in order to meet the maximum figure for the acquisition time.
Delay from CS

until SDATA is three-state disabled. Measured with the load circuit
in Figure 2 and defined as the time required for the output to cross the VIH or VIL
voltage.

Data access time after SCLK falling edge. M
and defined as t

he time required for the output to cross the V

SCLK to data valid hold time. Measur
defined as the ti

me required for the output to cross the V

SCLK falling edge to SDATA three-state. t

easured with the load circuit in Figure 2

ed with the load circuit in Figure 2 and

or VIL voltage.

IH

is derived from the measured time taken

8

by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The

ed number is then extrapolated back to remove the effects of charging or

measur
discharging the 50 pF capacitor. This means that the time, t

, quoted in the timing

8

characteristics, is the true bus relinquish time of the part, and is independent of
the bus loading.

or VIL voltage.

IH

200μAI

TO OUTPUT

PIN

C

L

50pF

200μAI

Figure 2. Load Circuit for Digital Out

Rev. C | Page 9 of 28

OL

1.4V

OH

put Timing Specifications

02643-002