ANALOG DEVICES AD7466, AD7467, AD7468 Service Manual

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1.8 V, Micro-Power ,

a

Preliminary Technical Data

FEATURES
Specified for V
Low Power:

0.9 mW max at 60 kSPS with 3.6 V Supplies

0.4 mW max at 100 kSPS with 1.8 V Supplies

Fast Throughput Rate: 100 kSPS
Wide Input Bandwidth:

70dB SNR at 30 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface

SPI/QSPI/

Standby Mode: 0.5
6-Lead SOT-23 Package and 8 lead

APPLICATIONS
Battery Powered Systems

Medical Instruments

of 1.8 V to 3.6 V

DD

µµ

µWire/DSP Compatible

µµ

µA max

µµ

µSOIC

µµ

8/10/12-Bit ADCs in 6 Lead SOT-23

AD7466/AD7467/AD7468

FUNCTIONAL BLOCK DIAGRAM

V

DD

IN

AD7466/67/68

T/HV

GND

12/10/8-BIT

SUCCESSIVE

APPROXIMATION

ADC

SCLK

CONTROL LOGIC SDAT A

CS

Ramote Data Acquisition
Isolated Data Acquisition

GENERAL DESCRIPTION

The AD7466/AD7467/AD7468 are 12/10/8-bit, high
speed, low power, successive-approximation ADCs re­spectively. The parts operate from a single 1.8 V to 3.6 V
power supply and feature throughput rates up to 100
kSPS. The parts contain a low-noise, wide bandwidth
track/hold amplifier which can handle input frequencies in
excess of 100 kHz.

The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to
interface with microprocessors or DSPs. The input signal
is sampled on the falling edge of CS and the conversion is
also initiated at this point. There are no pipelined delays
associated with the part.

The AD7466/AD7467/AD7468 use advanced design tech­niques to achieve very low power dissipation at high
throughput rates.

The reference for the part is taken internally from V
This allows the widest dynamic input range to the ADC.
Thus the analog input range for the part is 0 to V
conversion rate is determined by the SCLK.

DD

DD.

. The

PRODUCT HIGHLIGHTS

1. Specified for Supply voltages of 1.8 V to 3.6 V

2. 8/10/12-Bit ADCs in a SOT-23 package.

3. High Throughput with Low Power Consumption

4. Flexible Power/Serial Clock Speed Management
The conversion rate is determined by the serial clock
allowing the conversion time to be reduced through the
serial clock speed increase. Automatic power down after
conversion, which allows the average power cunsumption
to be reduced when in powerdown. Power consumption
is 0.5 µA max when in powerdown.

5. Reference derived from the power supply.

6. No Pipeline Delay
The part features a standard successive-approximation
ADC with accurate control of the conversions via a CS
input.

REV. PrC 07/01

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One T ec hnology Wa y , P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] Analog Devices, Inc., 2001

AD7466–SPECIFICATIONS

1

(VDD = 1.8 V to 3.6 V, f
T

to T

MIN

, unless otherwise noted.)

MAX

= 2.4 MHz, f

SCLK

= 100 kSPS unless otherwise noted; TA =

SAMPLE

Parameter B Version

DYNAMIC PERFORMANCE fIN = 30 kHz Sine Wave

Signal-to-Noise + Distortion (SINAD)
Signal-to-Noise Ratio (SNR)

2

Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)

2

2

2

2

1, 2

Unit Test Conditions/Comments

70 dB min
71 dB min
–78 dB typ
–80 dB typ

fa = 29.1 kHz, fb = 29.9 kHz
Second Order Terms –78 dB typ
Third Order Terms –78 dB typ

Aperture Delay 10 ns typ
Aperture Jitter 30 ps typ
Full Power Bandwidth TBD MHz typ @ 3 dB
Full Power Bandwidth TBD MHz typ @ 0.1 dB

DC ACCURACY

Resolution 12 Bits
Integral Nonlinearity

Differential Nonlinearity
Offset Error

Gain Error

3

3

2

2

±1.5 LSB max
±0.6 LSB typ
–0.9/+1.5 LSB max Guaranteed No Missed Codes to 12 Bits
±0.75 LSB typ
±1.5 LSB max
±1.5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to V

DD

V
DC Leakage Current ±1 µA max
Input Capacitance 30 pF typ

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V

INH

INL

Input Current, IIN, SCLK Pin ±1 µ A ma x Typically 10 nA, V
Input Current, IIN, CS Pin ±1 µA typ
Input Capacitance, C

2,3

IN

0.7(VDD) V min VDD = 1.8 V to 3.6 V

0.4 V max

IN

10 pF max

= 0 V or V

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current ±10 µA max
Floating-State Output Capacitance

OH

OL

2,3

VDD – 0.2 V m in I

0.2 V max I
10 pF max

= 200 µA; VDD = 1.8 V to 3.6 V

SOURCE

= 200 µA

SINK

Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 6.66 µs max Sixteen SCLK Cycles
Track/Hold Acquisition Time TBD ns max Full-Scale Step Input

TBD ns max Sine Wave Input

Throughput Rate 100 kSPS max See Serial Interface Section

POWER REQUIREMENTS

V

DD

I

DD

1.8/3.6 V min/max
Digital I/Ps = 0 V or V

DD

Normal Mode (Operational) 350 µA max VDD = 3 V. SCLK On or Off

200 µA max VDD = 1.8 V. SCLK On or Off

DD

Power-Down 0.5 µA max SCLK Off
Power Dissipation

4

80 µA max SCLK On

Normal Mode (Operational) TBD mW max VDD = 3 V. f

mW max VDD = 1.8 V. f

Power-Down 1.5 µW max VDD = 3 V. SCLK Off

0.9 µW max VDD = 1.8 V. SCLK Off

NOTES

1

Temperature ranges as follows: B Versions: –40°C to +85°C.

2

See Terminology.

3

Sample tested at 25°C to ensure compliance.

4

See Power Versus Throughput Rate section.

Specifications subject to change without notice.

–2– REV. PrC

SAMPLE

SAMPLE

= TBD

= TBD

1

AD7467–SPECIFICATIONS

Parameter B Version

DYNAMIC PERFORMANCE fIN = 30 kHz Sine Wave,

Signal-to-Noise + Distortion (SINAD)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)

2

2

2

2

T

to T

MIN

, unless otherwise noted.)

MAX

61 dB min
–73 dB max
–74 dB max

(VDD = 1.8 V to 3.6 V, f

= 2.4 MHz, f

SCLK

1, 2

Unit Test Conditions/Comments

= 100 kSPS unless otherwise noted; TA =

SAMPLE

fa = 29.1 kHz, fb = 29.9 kHz
Second Order Terms –7 8 dB typ
Third Order Terms –78 dB typ

Aperture Delay 1 0 ns typ
Aperture Jitter 30 ps typ
Full Power Bandwidth TBD MHz typ @ 3 dB

Full Power Bandwidth TBD MHz typ @ 0.1 dB

DC ACCURACY

Resolution 10 Bits
Integral Nonlinearity ±1 LSB max
Differential Nonlinearity ±0.9 LSB max Guaranteed No Missed Codes to 10 Bits
Offset Error ±1 LSB max
Gain Error ±1 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to V

DD

V
DC Leakage Current ±1 µA max
Input Capacitance 30 pF typ

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Current, IIN, CS Pin ±1 µA typ
Input Capacitance, C

INH

INL

, SCLK Pin ±1 µA m ax Typically 10 nA, V

IN

2,3

IN

0.7(V

DD)

0.4 V max

10 pF max

V min VDD = 1.8 to 3.6 V

= 0 V or V

IN

DD

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current ±10 µA max
Floating-State Output Capacitance

OH

OL

2,3

VDD – 0.2 V min I

0.2 V max I

10 pF max

SOURCE

= 200 µA

SINK

= 200 µA;

Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 5 µs max 12 SCLK Cycles with SCLK at 20 MHz
Track/Hold Acquisition Time TBD ns max
Throughput Rate 100 kSPS max See Serial Interface Section

POWER REQUIREMENTS

V

DD

I

DD

1.8/3.6 V min/max
Digital I/Ps = 0 V or V

DD

Normal Mode (Operational) 350 µA max VDD = 3 V . SCLK On or Off

200 µA max V

= 1.8 V . SCLK On or Off

DD

Power-Down Mode 0.5 µA max SCLK Off

Power Dissipation

4

Normal Mode (Operational) TBD mW max VDD = 3 V. f

Power-Down 1.5 µW max V

80 µA max SCLK On

TBD mW max V

= 1.8 V. f

DD

= 3 V. SCLK Off

DD

SAMPLE

SAMPLE

= 100 kSPS

= TBD

0.9 µW max VDD = 1.8 V. SCLK Off

NOTES

1

Temperature ranges as follows: B Versions: –40°C to +85°C.

2

See Terminology.

3

Sample tested at 25°C to ensure compliance.

4

See Power Versus Throughput Rate section.

Specifications subject to change without notice.

–3–

REV. PrC

1

AD7468–SPECIFICATIONS

(VDD = 1.8 V to 3.6 V, f
T

to T

MIN

, unless otherwise noted.)

MAX

Parameter B Version

DYNAMIC PERFORMANCE fIN =30 kHz Sine Wave, f

Signal-to-Noise + Distortion (SINAD)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)

2

2

2

2

49 dB min
–65 dB max
–65 dB max

= 2.4 MHz, f

SCLK

1, 2

Unit Test Conditions/Comments

= 100 kSPS unless otherwise noted; TA =

SAMPLE

fa = 29.1 kHz, fb = 29.9 kHz

SAMPLE

Second Order Terms –6 8 dB typ

Third Order Terms –6 8 dB typ
Aperture Delay 10 ns typ
Aperture Jitter 30 ps typ
Full Power Bandwidth TBD MHz typ @ 3 dB

Full Power Bandwidth TBD MHz typ @ 0.1 dB

DC ACCURACY

2

Resolution 8 Bits
Integral Nonlinearity ±0.5 LSB max
Differential Nonlinearity ±0.5 LSB max Guaranteed No Missed Codes to 8 Bits
Offset Error ±0.5 LSB max
Gain Error ±0.5 LSB max
Total Unadjusted Error (TUE) ±0.5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to V

DD

V
DC Leakage Current ±1 µA max
Input Capacitance 30 pF typ

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Current, IIN, CS Pin ±1 µA typ
Input Capacitance, C

INH

INL

, SCLK Pin ±1 µ A max Typically 10 nA, V

IN

2,3

IN

0.7(V

DD)

0.4 V max

10 pF max

V min VDD = 1.8 to 3.6 V

= 0 V or V

IN

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current ±10 µA max
Floating-State Output Capacitance

OH

OL

3, 4

VDD – 0.2 V min I

0.2 V max I

10 pF max

= 200 µA; VDD = 1.8 V to 3.6 V

SOURCE

= 200 µA

SINK

Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 4.166 µs max 10 SCLK Cycles with SCLK at 2.4 MHz
Track/Hold Acquisition Time TBD ns max
Throughput Rate 100 kSPS max See Serial Interface Section

POWER REQUIREMENTS

V

DD

I

DD

1.8/3.6 V min/max
Digital I/Ps = 0 V or V

DD

Normal Mode (Static) 350 µA max VDD = 3V. SCLK On or Off

200 µA max V

= 1.8 V . SCLK On or Off

DD

Power-Down Mode 0.5 µA max SCLK Off

Power Dissipation

5

Normal Mode (Operational) TBD mW max VDD = 3 V. f

Power-Down 1.5 µW max V

80 µA max SCLK On

TBD mW max V

= 1.8 V. f

DD

= 3 V. SCLK Off

DD

SAMPLE

SAMPLE

= TBD

= TBD

0.9 µW max VDD = 1.8 V. SCLK Off

NOTES

1

Temperature ranges as follows: B Versions: –40°C to +85°C.

2

See Terminology.

3

Sample tested at 25°C to ensure compliance.

4

See Power Versus Throughput Rate section.

Specifications subject to change without notice.

=100kSPS

DD

–4– REV. PrC

AD7466/AD7467/AD7468

1

TIMING SPECIFICATIONS

(VDD = +1.8 V to +3.6 V; TA = T

Parameter AD7466 Units Description

2

f

SCLK

10 kHz min
TBD MHz max

t

CONVERT

t

quiet

16* t

SCLK

TBD ns min Minimum Quiet Time required between Bus Relinquish

and start of next conversion

t

1

t

2

3

t

3

3

t

4

t

5

t

6

t

7

4

t

8

5

t

power-up

NOTES

1

Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 Volts.

2

Mark/Space ratio for the SCLK input is 40/60 to 60/40.

3

Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.

4

t8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to
remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the
part and is independent of the bus loading.

5

See Power-up Time section.

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C unless otherwise noted)

T BD ns min Minimum CS Pulse Width
10 ns min CS to SCLK Setup Time
TBD ns max Delay from CS Until SDATA 3-State Disabled
TBD ns max Data Access Time After SCLK Falling Edge

0.4t

0.4t

SCLK
SCLK

ns min SCLK Low Pulse Width

ns min SCLK High Pulse Width
T BD ns min SCLK to Data Valid Hold Time
TBD ns max SCLK falling Edge to SDATA High Impedance
TBD µs typ Power up time from Full Power-down.

1

MIN

to T

, unless otherwise noted.)

MAX

VDD to GND –0.3 V to TBD V
Analog Input Voltage to GND –0.3 V to V

+ 0.3 V

DD

Digital Input Voltage to GND –0.3 V to TBDV
Digital Output Voltage to GND –0.3 V to V
Input Current to Any Pin Except Supplies

2

Operating Temperature Range

Commercial (A, B Version) –40°C to +85°C
Storage Temperature Range –65°C to +150°C

Junction Temperature +150°C

+ 0.3 V

DD

±10 mA

OUTPUT

PIN

TO

C

L

50pF

SOT-23 Package, Power Dissipation 450 mW

θ

Thermal Impedance 229.6°C/W (SOT23)

JA

205.9°C/W (µSOIC)
θ

Thermal Impedance 91.99°C/W (SOT23)

JC

43.74°C/W (µSOIC)

Figure 1. Load Circuit for Digital Output Timing

Lead Temperature, Soldering

Vapor Phase (60 secs) +215°C
Infared (15 secs) +220°C

ESD TBD

NOTES

1

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch up.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7466/AD7467/AD7468 feature proprietary ESD protection circuitr y, per­manent damage may occur on devices subjected to high energy electrostatic discharges. There­fore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.

–5–REV. PrC

200µA

200µA

I

Specifications

OL

I

+1.6V

OH