V
1.6 V, Micropower 12-Bit ADC
Known Good Die
FEATURES
Specified for V
Low power
0.62 mW typical at 100 kSPS with 3 V supplies
0.48 mW typical at 50 kSPS with 3.6 V supplies
0.12 mW typical at 100 kSPS with 1.6 V supplies
Fast throughput rate: 200 kSPS
Wide input bandwidth: 71 dB SNR at 30 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface
SPI/QSPI™/MICROWIRE™/DSP compatible
Automatic power-down
Power-down mode: 8 nA typical
APPLICATIONS
Battery-powered systems
Medical instruments
Remote data acquisition
Isolated data acquisition
of 1.6 V to 3.6 V
DD
AD7466-KGD
FUNCTIONAL BLOCK DIAGRAM
DD
12-BIT
T/H
V
IN
SUCCESSIVE
APPROXIMATION
ADC
CONTROL
LOGIC
AD7466-KGD
GND
Figure 1.
SCLK
SDATA
CS
10315-001
GENERAL DESCRIPTION
The AD7466-KGD1 are 12-bit, high speed, low power,
successive approximation analog-to-digital converter (ADC).
The part operates from a single 1.6 V to 3.6 V power supply and
features throughput rates up to 200 kSPS with low power
dissipation. The part contains a low noise, wide bandwidth
track-and-hold amplifier, which can handle input frequencies in
excess of 3 MHz.
The conversion process and data acquisition are controlled
CS
using
with microprocessors or DSPs. The input signal is sampled on
the falling edge of
point. There are no pipeline delays associated with the part.
The reference for the part is taken internally from V
allows the widest dynamic input range to the ADC. Thus, the
analog input range for the part is 0 V to V
rate is determined by the SCLK.
1
Protected by U.S. Patent No. 6,681,332.
and the serial clock, allowing the device to interface
CS
, and the conversion is also initiated at this
. This
DD
. The conversion
DD
PRODUCT HIGHLIGHTS
1. Specified for supply voltages of 1.6 V to 3.6 V.
2. High throughput rate with low power consumption.
Power consumption in normal mode of operation at
100 kSPS and 3 V is 0.9 mW maximum.
3. Flexible power/serial clock speed management.
The conversion rate is determined by the serial clock,
allowing the conversion time to be reduced through
increases in the serial clock speed. Automatic power-down
after conversion allows the average power consumption to
be reduced when in power-down. Current consumption is
0.1 μA maximum and 8 nA typically when in power-down.
4. Reference derived from the power supply.
5. No pipeline delay.
6. The part features a standard successive approximation
ADC with accurate control of conversions via a
CS
input.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
AD7466-KGD Known Good Die
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
REVISION HISTORY
11/11—Revision 0: Initial Version
Timing Examples...........................................................................6
Absolute Maximum Ratings ............................................................7
ESD Caution...................................................................................7
Pad Configuration and Function Descriptions.............................8
Outline Dimensions..........................................................................9
Die Specifications and Assembly Recommendations ..............9
Ordering Guide .............................................................................9
Rev. 0 | Page 2 of 12
Known Good Die AD7466-KGD
SPECIFICATIONS
VDD = 1.6 V to 3.6 V, f
The temperature range for the AD7466-KGD version is −40°C to +85°C.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE fIN = 30 kHz sine wave
Signal-to-Noise and Distortion (SINAD) 69 dB 1.8 V ≤ VDD ≤ 2 V
70 dB 2.5 V ≤ VDD ≤ 3.6 V
70 dB VDD = 1.6 V
Signal-to-Noise Ratio (SNR) 70 dB 1.8 V ≤ VDD ≤ 2 V
71 dB 1.8 V ≤ VDD ≤ 2 V
71 dB 2.5 V ≤ VDD ≤ 3.6 V
70.5 dB VDD = 1.6 V
Total Harmonic Distortion (THD) −83 dB
Peak Harmonic or Spurious Noise (SFDR) −85 dB
Intermodulation Distortion (IMD) fa = 29.1 kHz, fb = 29.9 kHz
Second-Order Terms −84 dB
Third-Order Terms −86 dB
Aperture Delay 10 ns
Aperture Jitter 40 ps
Full Power Bandwidth 3.2 MHz At 3 dB, 2.5 V ≤ VDD ≤ 3.6 V
1.9 MHz At 3 dB, 1.6 V ≤ VDD ≤ 2.2 V
750 kHz At 0.1 dB, 2.5 V ≤ VDD ≤ 3.6 V
450 kHz At 0.1 dB, 1.6 V ≤ VDD ≤ 2.2 V
DC ACCURACY
Resolution 12 Bits
Integral Nonlinearity ±1.5 LSB
Differential Nonlinearity −0.9/+1.5 LSB Guaranteed no missed codes to 12 bits
Offset Error ±1 LSB
Gain Error ±1 LSB
Total Unadjusted Error (TUE) ±2 LSB
ANALOG INPUT
Input Voltage Range 0 VDD V
DC Leakage Current ±1 μA
Input Capacitance 20 pF
LOGIC INPUTS
Input High Voltage, V
2 V 2.7 V ≤ VDD ≤ 3.6 V
Input Low Voltage, V
0.3 × VDD V 1.8 V ≤ VDD < 2.7 V
0.8 V 2.7 V ≤ VDD ≤ 3.6 V
Input Current, IIN, SCLK Pin ±1 μA Typically 20 nA, VIN = 0 V or VDD
Input Current, IIN, CS Pin
Input Capacitance, CIN 10 pF Sample tested at 25°C to ensure compliance
LOGIC OUTPUTS
Output High Voltage, VOH V
Output Low Voltage, VOL 0.2 V I
Floating-State Leakage Current ±1 μA
Floating-State Output Capacitance 10 pF
Output Coding Straight (natural) binary
= 3.4 MHz, f
SCLK
= 100 kSPS, unless otherwise noted. TA = T
SAMPLE
MIN
to T
MAX
Maximum specifications apply as typical figures
when VDD = 1.6 V
0.7 × VDD V 1.6 V ≤ VDD < 2.7 V
INH
0.2 × VDD V 1.6 V ≤ VDD < 1.8 V
INL
±1 μA
− 0.2 V I
DD
= 200 μA, VDD = 1.6 V to 3.6 V
SOURCE
= 200 μA
SINK
, unless otherwise noted.
Rev. 0 | Page 3 of 12
AD7466-KGD Known Good Die
Parameter Min Typ Max Unit Test Conditions/Comments
CONVERSION RATE
Conversion Time 4.70 μs 16 SCLK cycles with SCLK at 3.4 MHz
Throughput Rate 200 kSPS
POWER REQUIREMENTS
VDD 1.6 3.6 V
IDD Digital inputs = 0 V or VDD
Normal Mode (Operational) 300 μA VDD = 3 V, f
110 μA VDD = 3 V, f
20 μA VDD = 3 V, f
240 μA VDD = 2.5 V, f
80 μA VDD = 2.5 V, f
16 μA VDD = 2.5 V, f
165 μA VDD = 1.8 V, f
50 μA VDD = 1.8 V, f
10 μA VDD = 1.8 V, f
Power-Down Mode 0.1 μA SCLK on or off, typically 8 nA
Power Dissipation
Normal Mode (Operational) 0.9 mW VDD = 3 V, f
0.6 mW VDD = 2.5 V, f
0.3 mW VDD = 1.8 V, f
Power-Down Mode 0.3 μW VDD = 3 V
= 100 kSPS
SAMPLE
= 50 kSPS
SAMPLE
= 10 kSPS
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
= 100 kSPS
SAMPLE
SAMPLE
SAMPLE
= 100 kSPS
= 50 kSPS
= 10 kSPS
= 100 kSPS
= 50 kSPS
= 10 kSPS
= 100 kSPS
= 100 kSPS
Rev. 0 | Page 4 of 12
Known Good Die AD7466-KGD
TIMING SPECIFICATIONS
For all devices, VDD = 1.6 V to 3.6 V; TA = T
signals are specified with tr = tf = 5 ns (10% to 90% of V
Table 2.
Parameter Limit at T
f
3.4 MHz max Mark/space ratio for the SCLK input is 40/60 to 60/40.
SCLK
MIN
, T
Unit Description
MAX
10 kHz min 1.6 V ≤ VDD ≤ 3 V; minimum f
20 kHz min VDD = 3.3 V; minimum f
150 kHz min VDD = 3.6 V; minimum f
t
16 × t
CONVER T
SCLK
Acquisition Time
780 ns max VDD = 1.6 V.
640 ns max 1.8 V ≤ VDD ≤ 3.6 V.
t
10 ns min
QUIET
t1 10 ns min
t2 55 ns min
t3 55 ns max
t4 140 ns max
t5 0.4 t
t6 0.4 t
ns min SCLK low pulse width.
SCLK
ns min SCLK high pulse width.
SCLK
t7 10 ns min
t8 60 ns max
7 ns min SCLK falling edge to SDATA three-state.
MIN
to T
, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input
MAX
) and timed from a voltage level of 1.4 V.
DD
at which specifications are guaranteed.
SCLK
at which specifications are guaranteed.
SCLK
at which specifications are guaranteed.
SCLK
Acquisition time/power-up time from power-down. The acquisition time is the
time required for the part to acquire a full-scale step input value within ±1 LSB or a
30 kHz ac input value within ±0.5 LSB.
Minimum quiet time required between bus relinquish and the start of the next
conversion.
Minimum CS
to SCLK setup time. If VDD = 1.6 V and f
CS
pulse width.
= 3.4 MHz, t2 has to be 192 ns
SCLK
minimum in order to meet the maximum figure for the acquisition time.
Delay from CS
in and defined as the time required for the output to cross the VIH or VIL
Figure 2
until SDATA is three-state disabled. Measured with the load circuit
voltage.
Data access time after SCLK falling edge. Measured with the load circuit in Figure 2
and defined as the time required for the output to cross the VIH or VIL voltage.
SCLK to data valid hold time. Measured with the load circuit in Figure 2 and
defined as the time required for the output to cross the V
SCLK falling edge to SDATA three-state. t
is derived from the measured time taken
8
or VIL voltage.
IH
by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The
measured number is then extrapolated back to remove the effects of charging or
discharging the 50 pF capacitor. This means that the time, t
, quoted in the timing
8
characteristics, is the true bus relinquish time of the part, and is independent of
the bus loading.
200µA I
TO OUTPUT
PIN
C
L
50pF
200µA I
Figure 2. Load Circuit for Digital Output Timing Specifications
Rev. 0 | Page 5 of 12
OL
1.4V
OH
10315-002
AD7466-KGD Known Good Die
TIMING EXAMPLES
Figure 3 shows some of the timing parameters from Tab l e 2 in
the Timing Specifications section.
Timing Example 1
As shown in Figure 3, f
100 kSPS gives a cycle time of t
Assuming V
= 1.8 V, t
DD
4.41 μs = 4.46 μs, and t
which satisfies the requirement of 10 ns for t
fully powered up and the signal is fully acquired at Point A.
This means that the acquisition/power-up time is t
= 55 ns + 588 ns = 643 ns, satisfying the maximum requirement
of 640 ns for the power-up time.
CS
SCLK
= 3.4 MHz and a throughput of
SCLK
+ t8 + t
CONVERT
= t2 + 15(1/f
CONVERT
= 60 ns maximum, then t
8
t
2
1
ACQUISIT ION TI M E
TRACK-AND-HOLD
IN TRACK
B A
23
QUIET
) = 55 ns +
SCLK
QUIET
= 10 μs.
= 5.48 μs,
QUIET
. The part is
+ 2(1/f
2
t
CONVERT
5
4
SCLK
)
TRACK-AND-HOL D IN HOLD
Timing Example 2
The AD7466-KGD can also operate with slower clock frequencies.
As shown in Figure 3, assuming V
throughput of 50 kSPS gives a cycle time of t
20 μs. With t
and t
= 60 ns maximum, this leaves t
8
CONVERT
= t2 + 15(1/f
satisfies the requirement of 10 ns for t
= 1.8 V, f
DD
) = 55 ns + 7.5 μs = 7.55 μs,
SCLK
QUIET
QUIET
= 2 MHz, and a
SCLK
+ t8 + t
CONVERT
to be 12.39 μs, which
. The part is fully
QUIET
powered up and the signal is fully acquired at Point A, which
means the acquisition/power-up time is t
+ 2(1/f
2
) = 55 ns +
SCLK
1 μs = 1.05 μs, satisfying the maximum requirement of 640 ns
for the power-up time. In this example and with other slower
clock values, the part is fully powered up and the signal already
acquired before the third SCLK falling edge; however, the trackand-hold does not go into hold mode until that point. In this
example, the part can be powered up and the signal can be fully
acquired at approximately Point B in Figure 3.
13
14
15
16
t
8
t
QUIET
AUTOMATIC
POWER-DOWN
=
1/THROUGHPUT
POINT A: THE PART I F FULLY POWERED UP WITH V
FULLY ACQUIRED.
IN
10315-003
Figure 3. AD7466-KGD Serial Interface Timing Diagram Example
Rev. 0 | Page 6 of 12
Known Good Die AD7466-KGD
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Table 3.
Parameter Rating
VDD to GND −0.3 V to +7 V
Analog Input Voltage to GND −0.3 V to VDD + 0.3 V
Digital Input Voltage to GND −0.3 V to +7 V
Digital Output Voltage to GND −0.3 V to VDD + 0.3 V
Input Current to any Pin Except Supplies ±10 mA
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
ESD 3.5 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 7 of 12
AD7466-KGD Known Good Die
PAD CONFIGURATION AND FUNCTION DESCRIPTIONS
6
1
2
5
4
3
Figure 4. Pad Configuration
Table 4. Pad Function Descriptions
Pad No. X-Axis (μm) Y-Axis (μm) Mnemonic Pad Type Description
1 −173 +634
2 −173 +494 SDATA Single
3 −187 −600 SCLK Single
4 +187 −600 VIN Single
5A +173 +447.6 GND Double
5B +173 +489.6 GND Double
6A +173 +637.6 VDD Double Power Supply Input. The VDD range for the devices is from 1.6 V to 3.6 V.
6B +173 +679.6 VDD Double Power Supply Input. The VDD range for the devices is from 1.6 V to 3.6 V.
CS
Single
Chip Select. Active low logic input. This input provides the dual function of
initiating conversions on the devices and frames the serial data transfer.
Data Out. Logic output. The conversion result from the AD7466-KGD is
provided on this output as a serial data stream. The bits are clocked out on
the falling edge of the SCLK input. The data stream from the AD7466-KGD
consists of four leading zeros followed by the 12 bits of conversion data,
provided MSB first.
Serial Clock. Logic input. SCLK provides the serial clock for accessing data
from the parts. This clock input is also used as the clock source for the
conversion process of the parts.
Analog Input. Single-ended analog input channel. The input range is 0 V
to V
DD
Analog Ground. Ground reference point for all circuitry on the devices.
All analog input signals should be referred to this GND voltage.
Analog Ground. Ground reference point for all circuitry on the devices.
All analog input signals should be referred to this GND voltage.
10315-004
.
Rev. 0 | Page 8 of 12
Known Good Die AD7466-KGD
OUTLINE DIMENSIONS
0.880
1
2
3
6
5
2.185
4
0.500
TOP VIEW
(CIRCUIT SI DE)
0.076 × 0.076
Figure 5. 6-Pad Bare Die [CHIP]
(C-6-4)
Dimensions shown in millimeters
SIDE VIEW
11-03-2011-A
DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS
Table 5. Die Specifications
Parameter Value Unit
Chip Size 660 (x) × 2015 (y) μm
Scribe Line Width 120 (x) × 170 (y) μm
Die Size 880 (x) × 2185 (y) μm
Thickness 500 μm
Backside Silicon Not applicable
Passivation Nitride Not applicable
Bond Pads (Minimum Size) 76 × 76 μm
Bond Pad Composition 98.5% Al, 1% Si, 0.5% Cu %
ESD 3.5 kV
Table 6. Assembly Recommendations
Assembly Component Recommendation
Die Attach Epoxy adhesive
Bonding Method Gold ball or aluminum wedge
Bonding Sequence Five First
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD7466-KGD-DF −40°C to +85°C 6-Pad Bare Die [CHIP] C-6-4
Rev. 0 | Page 9 of 12
AD7466-KGD Known Good Die
NOTES
Rev. 0 | Page 10 of 12
Known Good Die AD7466-KGD
NOTES
Rev. 0 | Page 11 of 12
AD7466-KGD Known Good Die
NOTES
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10315-0-11/11(0)
Rev. 0 | Page 12 of 12
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