ANALOG DEVICES AD7466-KGD Service Manual

V

1.6 V, Micropower 12-Bit ADC

Known Good Die

FEATURES

Specified for V
Low power

0.62 mW typical at 100 kSPS with 3 V supplies

0.48 mW typical at 50 kSPS with 3.6 V supplies

0.12 mW typical at 100 kSPS with 1.6 V supplies
Fast throughput rate: 200 kSPS
Wide input bandwidth: 71 dB SNR at 30 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface

SPI/QSPI™/MICROWIRE™/DSP compatible
Automatic power-down
Power-down mode: 8 nA typical

APPLICATIONS

Battery-powered systems
Medical instruments
Remote data acquisition
Isolated data acquisition

of 1.6 V to 3.6 V

DD

AD7466-KGD

FUNCTIONAL BLOCK DIAGRAM

DD

12-BIT

T/H

V

IN

SUCCESSIVE

APPROXIMATION

ADC

CONTROL

LOGIC

AD7466-KGD

GND

Figure 1.

SCLK
SDATA
CS

10315-001

GENERAL DESCRIPTION

The AD7466-KGD1 are 12-bit, high speed, low power,
successive approximation analog-to-digital converter (ADC).
The part operates from a single 1.6 V to 3.6 V power supply and
features throughput rates up to 200 kSPS with low power
dissipation. The part contains a low noise, wide bandwidth
track-and-hold amplifier, which can handle input frequencies in
excess of 3 MHz.

The conversion process and data acquisition are controlled

CS

using
with microprocessors or DSPs. The input signal is sampled on
the falling edge of
point. There are no pipeline delays associated with the part.

The reference for the part is taken internally from V
allows the widest dynamic input range to the ADC. Thus, the
analog input range for the part is 0 V to V
rate is determined by the SCLK.

1

Protected by U.S. Patent No. 6,681,332.

and the serial clock, allowing the device to interface

CS

, and the conversion is also initiated at this

. This

DD

. The conversion

DD

PRODUCT HIGHLIGHTS

1. Specified for supply voltages of 1.6 V to 3.6 V.

2. High throughput rate with low power consumption.

Power consumption in normal mode of operation at
100 kSPS and 3 V is 0.9 mW maximum.

3. Flexible power/serial clock speed management.

The conversion rate is determined by the serial clock,
allowing the conversion time to be reduced through
increases in the serial clock speed. Automatic power-down
after conversion allows the average power consumption to
be reduced when in power-down. Current consumption is

0.1 μA maximum and 8 nA typically when in power-down.

4. Reference derived from the power supply.

5. No pipeline delay.

6. The part features a standard successive approximation

ADC with accurate control of conversions via a

CS

input.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.

AD7466-KGD Known Good Die

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 5

REVISION HISTORY

11/11—Revision 0: Initial Version

Timing Examples...........................................................................6

Absolute Maximum Ratings ............................................................7

ESD Caution...................................................................................7

Pad Configuration and Function Descriptions.............................8

Outline Dimensions..........................................................................9

Die Specifications and Assembly Recommendations ..............9

Ordering Guide .............................................................................9

Rev. 0 | Page 2 of 12

Known Good Die AD7466-KGD

SPECIFICATIONS

VDD = 1.6 V to 3.6 V, f
The temperature range for the AD7466-KGD version is −40°C to +85°C.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 30 kHz sine wave

Signal-to-Noise and Distortion (SINAD) 69 dB 1.8 V ≤ VDD ≤ 2 V

70 dB 2.5 V ≤ VDD ≤ 3.6 V

70 dB VDD = 1.6 V

Signal-to-Noise Ratio (SNR) 70 dB 1.8 V ≤ VDD ≤ 2 V

71 dB 1.8 V ≤ VDD ≤ 2 V

71 dB 2.5 V ≤ VDD ≤ 3.6 V

70.5 dB VDD = 1.6 V

Total Harmonic Distortion (THD) −83 dB

Peak Harmonic or Spurious Noise (SFDR) −85 dB

Intermodulation Distortion (IMD) fa = 29.1 kHz, fb = 29.9 kHz

Second-Order Terms −84 dB

Third-Order Terms −86 dB
Aperture Delay 10 ns
Aperture Jitter 40 ps
Full Power Bandwidth 3.2 MHz At 3 dB, 2.5 V ≤ VDD ≤ 3.6 V

1.9 MHz At 3 dB, 1.6 V ≤ VDD ≤ 2.2 V
750 kHz At 0.1 dB, 2.5 V ≤ VDD ≤ 3.6 V

450 kHz At 0.1 dB, 1.6 V ≤ VDD ≤ 2.2 V
DC ACCURACY

Resolution 12 Bits
Integral Nonlinearity ±1.5 LSB
Differential Nonlinearity −0.9/+1.5 LSB Guaranteed no missed codes to 12 bits
Offset Error ±1 LSB
Gain Error ±1 LSB
Total Unadjusted Error (TUE) ±2 LSB

ANALOG INPUT

Input Voltage Range 0 VDD V
DC Leakage Current ±1 μA
Input Capacitance 20 pF

LOGIC INPUTS

Input High Voltage, V
2 V 2.7 V ≤ VDD ≤ 3.6 V
Input Low Voltage, V

0.3 × VDD V 1.8 V ≤ VDD < 2.7 V

0.8 V 2.7 V ≤ VDD ≤ 3.6 V
Input Current, IIN, SCLK Pin ±1 μA Typically 20 nA, VIN = 0 V or VDD
Input Current, IIN, CS Pin
Input Capacitance, CIN 10 pF Sample tested at 25°C to ensure compliance

LOGIC OUTPUTS

Output High Voltage, VOH V
Output Low Voltage, VOL 0.2 V I
Floating-State Leakage Current ±1 μA
Floating-State Output Capacitance 10 pF
Output Coding Straight (natural) binary

= 3.4 MHz, f

SCLK

= 100 kSPS, unless otherwise noted. TA = T

SAMPLE

MIN

to T

MAX

Maximum specifications apply as typical figures
when VDD = 1.6 V

0.7 × VDD V 1.6 V ≤ VDD < 2.7 V

INH

0.2 × VDD V 1.6 V ≤ VDD < 1.8 V

INL

±1 μA

− 0.2 V I

DD

= 200 μA, VDD = 1.6 V to 3.6 V

SOURCE

= 200 μA

SINK

, unless otherwise noted.

Rev. 0 | Page 3 of 12

AD7466-KGD Known Good Die

Parameter Min Typ Max Unit Test Conditions/Comments

CONVERSION RATE

Conversion Time 4.70 μs 16 SCLK cycles with SCLK at 3.4 MHz
Throughput Rate 200 kSPS

POWER REQUIREMENTS

VDD 1.6 3.6 V
IDD Digital inputs = 0 V or VDD

Normal Mode (Operational) 300 μA VDD = 3 V, f
110 μA VDD = 3 V, f
20 μA VDD = 3 V, f
240 μA VDD = 2.5 V, f
80 μA VDD = 2.5 V, f
16 μA VDD = 2.5 V, f
165 μA VDD = 1.8 V, f
50 μA VDD = 1.8 V, f
10 μA VDD = 1.8 V, f

Power-Down Mode 0.1 μA SCLK on or off, typically 8 nA
Power Dissipation

Normal Mode (Operational) 0.9 mW VDD = 3 V, f

0.6 mW VDD = 2.5 V, f

0.3 mW VDD = 1.8 V, f

Power-Down Mode 0.3 μW VDD = 3 V

= 100 kSPS

SAMPLE

= 50 kSPS

SAMPLE

= 10 kSPS

SAMPLE

SAMPLE

SAMPLE

SAMPLE

SAMPLE

SAMPLE

SAMPLE

= 100 kSPS

SAMPLE

SAMPLE

SAMPLE

= 100 kSPS
= 50 kSPS
= 10 kSPS
= 100 kSPS
= 50 kSPS
= 10 kSPS

= 100 kSPS
= 100 kSPS

Rev. 0 | Page 4 of 12