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AD7466 7 8 a
Datasheet
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Analog Devices AD7466 7 8 a Datasheet

V
1.6 V, Micropower
12-, 10-, and 8-Bit ADCs in 6-Lead SOT-23

FEATURES

Specified for V Low power:
0.62 mW typ at 100 kSPS with 3 V supplies
0.48 mW typ at 50 kSPS with 3.6 V supplies
0.12 mW typ at 100 kSPS with 1.6 V supplies Fast throughput rate: 200 kSPS Wide input bandwidth:
71 dB SNR at 30 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface:
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible Automatic power-down Power-down mode: 8 nA typ 6-lead SOT-23 package 8-lead MSOP package

APPLICATIONS

Battery-powered systems Medical instruments Remote data acquisition Isolated data acquisition

GENERAL DESCRIPTION

The AD7466/AD7467/AD74681 are 12-, 10-, and 8-bit, high speed, low power, successive approximation ADCs, respectively. The parts operate from a single 1.6 V to 3.6 V power supply and feature throughput rates up to 200 kSPS with low power dissipation. The parts contain a low noise, wide bandwidth track-and-hold amplifier, which can handle input frequencies in excess of 3 MHz.
The conversion process and data acquisition are controlled using
with microprocessors or DSPs. The input signal is sampled on the falling edge of
point. There are no pipeline delays associated with the part.
The reference for the part is taken internally from V allows the widest dynamic input range to the ADC. Thus, the analog input range for the part is 0 V to V rate is determined by the SCLK.
1
Protected by U.S. Patent No. 6,681,332.
Rev. A
and the serial clock, allowing the devices to interface
CS
of 1.6 V to 3.6 V
DD
, and the conversion is also initiated at this
CS
. The conversion
DD
DD
. This
AD7466/AD7467/AD7468

FUNCTIONAL BLOCK DIAGRAM

V
DD
12-/10-/8-BIT
T/H
IN

PRODUCT HIGHLIGHTS

1. Specified for supply voltages of 1.6 V to 3.6 V.
2. 12-, 10-, and 8-bit ADCs in SOT-23 packages.
3. High throughput rate with low power consumption. Power consumption in normal mode of operation at 100 kSPS and 3 V is 0.9 mW maximum.
4. Flexible power/serial clock speed management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through increases in the serial clock speed. Automatic power-down after conversion allows the average power consumption to be reduced when in power-down. Current consumption is
0.1 µA maximum and 8 nA typically when in power-down.
5. Reference derived from the power supply.
6. No pipeline delay. The part features a standard successive approximation ADC with accurate control of conversions via a
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
www.analog.com
SUCCESSIVE
APPROXIMATION
ADC
CONTROL
LOGIC
AD7466/AD7467/AD7468
GND
Figure 1.
SCLK SDATA CS
CS
02643-001
input.
AD7466/AD7467/AD7468
TABLE OF CONTENTS
AD7466 Specifications..................................................................... 3
Converter Operation.................................................................. 17
AD7467 Specifications..................................................................... 5
AD7468 Specifications..................................................................... 7
Timing Specifications....................................................................... 9
Timing Examples........................................................................ 10
Absolute Maximum Ratings.......................................................... 11
ESD Caution................................................................................ 11
Pin Configurations and Function Descriptions .........................12
Te r mi n ol o g y ................................................................................ 13
Typical Performance Characteristics........................................... 14
Dynamic Performance Curves ................................................. 14
DC Accuracy Curves .................................................................14
Power Requirements Curves..................................................... 14
Circuit Information........................................................................ 17
REVISION HISTORY
ADC Transfer Function............................................................. 17
Typical Conne ction Diag ram ................................................... 18
Analog Input............................................................................... 18
Digital Inputs.............................................................................. 19
Normal Mode.............................................................................. 19
Power Consumption .................................................................. 20
Serial Interface................................................................................ 22
Microprocessor Interfacing....................................................... 23
Application Hints ........................................................................... 25
Grounding and Layout .............................................................. 25
Evaluating the Performance of the AD7466 and AD7467.... 25
Outline Dimensions .......................................................................26
Ordering Guide .......................................................................... 27
11/04—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to General Description .................................................... 1
Added Patent Number..................................................................... 1
Updated Outline Dimensions....................................................... 26
Changes to Ordering Guide.......................................................... 27
5/03—Revision 0: Initial Version
Rev. A | Page 2 of 28
AD7466/AD7467/AD7468

AD7466 SPECIFICATIONS

VDD = 1.6 V to 3.6 V, f The temperature range for the B version is −40°C to +85°C.
Table 1.
Parameter B Version Unit Test Conditions/Comments
DYNAMIC PERFORMANCE fIN = 30 kHz sine wave
Signal-to-Noise and Distortion (SINAD) 69 dB min 1.8 V ≤ VDD ≤ 2 V; see the Terminology section 70 dB min 2.5 V ≤ VDD ≤ 3.6 V 70 dB typ VDD = 1.6 V Signal-to-Noise Ratio (SNR) 70 dB min 1.8 V ≤ VDD ≤ 2 V; see the Terminology section 71 dB typ 1.8 V ≤ VDD ≤ 2 V 71 dB min 2.5 V ≤ VDD ≤ 3.6 V
70.5 dB typ VDD = 1.6 V Total Harmonic Distortion (THD) −83 dB typ See the Terminology section Peak Harmonic or Spurious Noise (SFDR) −85 dB typ See the Terminology section Intermodulation Distortion (IMD) fa = 29.1 kHz, fb = 29.9 kHz; see the Terminology section
Second-Order Terms −84 dB typ
Third-Order Terms −86 dB typ Aperture Delay 10 ns typ Aperture Jitter 40 ps typ Full-Power Bandwidth 3.2 MHz typ @ 3 dB, 2.5 V ≤ VDD ≤ 3.6 V
1.9 MHz typ @ 3 dB, 1.6 V ≤ VDD ≤ 2.2 V 750 kHz typ @ 0.1 dB, 2.5 V ≤ VDD ≤ 3.6 V
450 kHz typ @ 0.1 dB, 1.6 V ≤ VDD ≤ 2.2 V DC ACCURACY
Resolution 12 Bits Integral Nonlinearity ±1.5 LSB max See the Terminology section Differential Nonlinearity −0.9/+1.5 LSB max
Offset Error ±1 LSB max See the Terminology section Gain Error ±1 LSB max See the Terminology section Total Unadjusted Error (TUE) ±2 LSB max See the Terminology section
ANALOG INPUT
Input Voltage Ranges 0 to V DC Leakage Current ±1 µA max Input Capacitance 20 pF typ
LOGIC INPUTS
Input High Voltage, V 2 V min 2.7 V ≤ VDD ≤ 3.6 V Input Low Voltage, V
0.3 × V
0.8 V max 2.7 V ≤ VDD ≤ 3.6 V Input Current, IIN, SCLK Pin ±1 µA max Typically 20 nA, VIN = 0 V or V Input Current, IIN, CS Pin Input Capacitance, C
LOGIC OUTPUTS
Output High Voltage, V
Output Low Voltage, V Floating-State Leakage Current ±1 µA max Floating-State Output Capacitance 10 pF max Output Coding Straight (Natural) Binary
= 3.4 MHz, f
SCLK
INH
INL
IN
OH
OL
= 100 kSPS, unless otherwise noted. TA = T
SAMPLE
DD
0.7 × V
0.2 × V
V
V min 1.6 V ≤ VDD < 2.7 V
DD
V max 1.6 V ≤ VDD < 1.8 V
DD
V max 1.8 V ≤ VDD < 2.7 V
DD
±1 µA typ 10 pF max Sample tested at 25°C to ensure compliance
VDD − 0.2
V min I
0.2 V max I
MIN
to T
, unless otherwise noted.
MAX
Maximum specifications apply as typical figures when
= 1.6 V
V
DD
Guaranteed no missed codes to 12 bits; see the Terminology section
DD
= 200 µA; VDD = 1.6 V to 3.6 V
SOURCE
= 200 µA
SINK
Rev. A | Page 3 of 28
AD7466/AD7467/AD7468
Parameter B Version Unit Test Conditions/Comments
CONVERSION RATE
Conversion Time 4.70 µs max 16 SCLK cycles with SCLK at 3.4 MHz Throughput Rate 200 kSPS max See the Serial Interface section
POWER REQUIREMENTS
V
DD
I
DD
Normal Mode (Operational) 300 µA max VDD = 3 V, f 110 µA typ VDD = 3 V, f 20 µA typ VDD = 3 V, f 240 µA max VDD = 2.5 V, f 80 µA typ VDD = 2.5 V, f 16 µA typ VDD = 2.5 V, f 165 µA max VDD = 1.8 V, f 50 µA typ VDD = 1.8 V, f 10 µA typ VDD = 1.8 V, f
Power-Down Mode 0.1 µA max SCLK on or off, typically 8 nA Power Dissipation See the Power Consumption section
Normal Mode (Operational) 0.9 mW max VDD = 3 V, f
0.6 mW max VDD = 2.5 V, f
0.3 mW max VDD = 1.8 V, f
Power-Down Mode 0.3 µW max VDD = 3 V
1.6/3.6 V min/max Digital inputs = 0 V or V
= 100 kSPS
SAMPLE
= 50 kSPS
SAMPLE
= 10 kSPS
SAMPLE
= 100 kSPS
SAMPLE
= 50 kSPS
SAMPLE
= 10 kSPS
SAMPLE
= 100 kSPS
SAMPLE
= 50 kSPS
SAMPLE
= 10 kSPS
SAMPLE
= 100 kSPS
SAMPLE
= 100 kSPS
SAMPLE
= 100 kSPS
SAMPLE
DD
Rev. A | Page 4 of 28
AD7466/AD7467/AD7468

AD7467 SPECIFICATIONS

VDD = 1.6 V to 3.6 V, f
The temperature range for the B version is −40°C to +85°C.
Table 2.
Parameter B Version Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise and Distortion (SINAD) 61 dB min See the Terminology section Total Harmonic Distortion (THD) −72 dB max See the Terminology section Peak Harmonic or Spurious Noise (SFDR) −74 dB max See the Terminology section Intermodulation Distortion (IMD) fa = 29.1 kHz, fb = 29.9 kHz; see the Terminology section
Second-Order Terms −83 dB typ
Third-Order Terms −83 dB typ Aperture Delay 10 ns typ Aperture Jitter 40 ps typ Full-Power Bandwidth 3.2 MHz typ @ 3 dB, 2.5 V ≤ VDD ≤ 3.6 V
1.9 MHz typ @ 3 dB, 1.6 V ≤ VDD ≤ 2.2 V 750 kHz typ @ 0.1 dB, 2.5 V ≤ VDD ≤ 3.6 V
450 kHz typ @ 0.1 dB, 1.6 V ≤ VDD ≤ 2.2 V DC ACCURACY
Resolution 10 Bits Integral Nonlinearity ±0.5 LSB max See the Terminology section Differential Nonlinearity ±0.5 LSB max
Offset Error ±0.2 LSB max See the Terminology section Gain Error ±0.2 LSB max See the Terminology section Total Unadjusted Error (TUE) ±1 LSB max See the Terminology section
ANALOG INPUT
Input Voltage Ranges 0 to V DC Leakage Current ±1 µA max Input Capacitance 20 pF typ
LOGIC INPUTS
Input High Voltage, V 2 V min 2.7 V ≤ VDD ≤ 3.6 V Input Low Voltage, V
0.3 × V
0.8 V max 2.7 V ≤ VDD ≤ 3.6 V Input Current, IIN, SCLK Pin ±1 µA max Typically 20 nA, VIN = 0 V or V Input Current, IIN, CS Pin Input Capacitance, C
LOGIC OUTPUTS
Output High Voltage, V Output Low Voltage, V Floating-State Leakage Current ±1 µA max Floating-State Output Capacitance 10 pF max Sample tested at 25°C to ensure compliance Output Coding Straight (Natural) Binary
CONVERSION RATE
Conversion Time 3.52 µs max 12 SCLK cycles with SCLK at 3.4 MHz Throughput Rate 275 kSPS max See the Serial Interface section
= 3.4 MHz, f
SCLK
INH
INL
IN
OH
OL
= 100 kSPS, unless otherwise noted. TA = T
SAMPLE
V
DD
0.7 × V
0.2 × V
V min 1.6 V ≤ VDD < 2.7 V
DD
V max 1.6 V ≤ VDD < 1.8 V
DD
V max 1.8 V ≤V DD < 2.7 V
DD
±1 µA typ 10 pF max Sample tested at 25°C to ensure compliance
VDD − 0.2 V min I
0.2 V max I
MIN
to T
, unless otherwise noted.
MAX
Maximum/minimum specifications apply as typical figures when V
= 1.6 V, fIN = 30 kHz sine wave
DD
Maximum specifications apply as typical figures when
= 1.6 V
V
DD
Guaranteed no missed codes to 10 bits;
see the Terminology section
DD
= 200 µA; VDD = 1.6 V to 3.6 V
SOURCE
= 200 µA
SINK
Rev. A | Page 5 of 28
AD7466/AD7467/AD7468
Parameter B Version Unit Test Conditions/Comments
POWER REQUIREMENTS
V
DD
I
DD
Normal Mode (Operational) 210 µA max VDD = 3 V, f 170 µA max VDD = 2.5 V, f 140 µA max VDD = 1.8 V, f
Power-Down Mode 0.1 µA max SCLK on or off, typically 8 nA Power Dissipation See the Power Consumption section
Normal Mode (Operational) 0.63 mW max VDD = 3 V, f
0.42 mW max VDD = 2.5 V, f
0.25 mW max VDD = 1.8 V, f
Power-Down Mode 0.3 µW max VDD = 3 V
1.6/3.6 V min/max Digital inputs = 0 V or V
= 100 kSPS
SAMPLE
= 100 kSPS
SAMPLE
= 100 kSPS
SAMPLE
= 100 kSPS
SAMPLE
= 100 kSPS
SAMPLE
= 100 kSPS
SAMPLE
DD
Rev. A | Page 6 of 28
AD7466/AD7467/AD7468

AD7468 SPECIFICATIONS

VDD = 1.6 V to 3.6 V, f
The temperature range for the B version is −40°C to +85°C.
Table 3.
Parameter B Version Unit Test Conditions/Comments
DYNAMIC PERFORMANCE Maximum/minimum specifications apply as typical figures when
Signal-to-Noise and Distortion (SINAD) 49 dB min See the Terminology section Total Harmonic Distortion (THD) −66 dB max See the Terminology section Peak Harmonic or Spurious Noise (SFDR) −66 dB max See the Terminology section Intermodulation Distortion (IMD) fa = 29.1 kHz, fb = 29.9 kHz; see the Terminology section
Second-Order Terms −77 dB typ
Third-Order Terms −77 dB typ Aperture Delay 10 ns typ Aperture Jitter 40 ps typ Full-Power Bandwidth 3.2 MHz typ @ 3 dB, 2.5 V ≤ VDD ≤ 3.6 V
1.9 MHz typ @ 3 dB, 1.6 V ≤ VDD ≤ 2.2 V 750 kHz typ @ 0.1 dB, 2.5 V ≤ VDD ≤ 3.6 V 450 kHz typ @ 0.1 dB, 1.6 V ≤ VDD ≤ 2.2 V
DC ACCURACY Maximum specifications apply as typical figures when VDD = 1.6 V
Resolution 8 Bits Integral Nonlinearity ±0.2 LSB max See the Terminology section Differential Nonlinearity ±0.2 LSB max
Offset Error ±0.1 LSB max See the Terminology section Gain Error ±0.1 LSB max See the Terminology section Total Unadjusted Error (TUE) ±0.3 LSB max See the Terminology section
ANALOG INPUT
Input Voltage Ranges 0 to V DC Leakage Current ±1 µA max Input Capacitance 20 pF typ
LOGIC INPUTS
Input High Voltage, V 2 V min 2.7 V ≤ V Input Low Voltage, V
0.3 × V
0.8 V max 2.7 V ≤ VDD ≤ 3.6 V Input Current, IIN, SCLK Pin ±1 µA max Typically 20 nA, VIN = 0 V or V Input Current, IIN, CS Pin Input Capacitance, C
LOGIC OUTPUTS
Output High Voltage, V Output Low Voltage, V Floating-State Leakage Current ±1 µA max Floating-State Output Capacitance 10 pF max Sample tested at 25°C to ensure compliance Output Coding Straight (Natural) Binary
CONVERSION RATE
Conversion Time 2.94 µs max 10 SCLK cycles with SCLK at 3.4 MHz Throughput Rate 320 kSPS max See the Serial Interface section
= 3.4 MHz, f
SCLK
INH
INL
IN
OH
OL
= 100 kSPS, unless otherwise noted. TA = T
SAMPLE
V
= 1.6 V, fIN = 30 kHz sine wave
DD
MIN
to T
, unless otherwise noted.
MAX
Guaranteed no missed codes to 8 bits; see the Terminology section
V
DD
0.7 × V
0.2 × V
V min 1.6 V ≤ VDD < 2.7 V
DD
V max 1.6 V ≤ VDD < 1.8 V
DD
V max 1.8 V ≤ VDD < 2.7 V
DD
≤ 3.6 V
DD
±1 µA typ 10 pF max Sample tested at 25°C to ensure compliance
VDD − 0.2 V min I
0.2 V max I
= 200 µA; VDD = 1.6 V to 3.6 V
SOURCE
= 200 µA
SINK
DD
Rev. A | Page 7 of 28
AD7466/AD7467/AD7468
Parameter B Version Unit Test Conditions/Comments
POWER REQUIREMENTS
V
DD
I
DD
Normal Mode (Operational) 190 µA max VDD = 3 V, f
155 µA max VDD = 2.5 V, f
120 µA max VDD = 1.8 V, f
Power-Down Mode 0.1 µA max SCLK on or off, typically 8 nA
Power Dissipation See the Power Consumption section
Normal Mode (Operational) 0.57 mW max VDD = 3 V, f
0.4 mW max VDD = 2.5 V, f
0.2 mW max VDD = 1.8 V, f Power-Down Mode 0.3 µW max VDD = 3 V
1.6/3.6 V min/max Digital inputs = 0 V or V
= 100 kSPS
SAMPLE
= 100 kSPS
SAMPLE
= 100 kSPS
SAMPLE
= 100 kSPS
SAMPLE
= 100 kSPS
SAMPLE
= 100 kSPS
SAMPLE
DD
Rev. A | Page 8 of 28
AD7466/AD7467/AD7468

TIMING SPECIFICATIONS

For all devices, VDD = 1.6 V to 3.6 V; TA = T signals are specified with tr = tf = 5 ns (10% to 90% of V
Table 4.
Parameter Limit at T
f
SCLK
3.4 MHz max Mark/space ratio for the SCLK input is 40/60 to 60/40.
MIN
, T
MAX
10 kHz min 1.6 V ≤ VDD ≤ 3 V; minimum f 20 kHz min VDD = 3.3 V; minimum f 150 kHz min VDD = 3.6 V; minimum f t
CONVERT
12 × t 10 × t
16 × t
SCLK
SCLK
SCLK
Acquisition Time
780 ns max VDD = 1.6 V.
640 ns max 1.8 V ≤ V
t
QUIET
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
10 ns min
10 ns min 55 ns min
55 ns max
140 ns max
0.4 t
SCLK
0.4 t
SCLK
10 ns min
60 ns max
7 ns min SCLK falling edge to SDATA three-state.
to T
MIN
, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input
MAX
) and timed from a voltage level of 1.4 V.
DD
Unit Description
AD7466 AD7467 AD7468
Acquisition time/power-up time from power-down. See the Terminology section. The acquisition time is the time required for the part to acquire a full­scale step input value within ±1 LSB or a 30 kHz ac input value within ±0.5 LSB.
≤ 3.6 V.
DD
Minimum quiet time required between bus relinquish and the start of the next conversion.
Minimum
CS pulse width.
CS to SCLK setup time. If VDD = 1.6 V and f minimum in order to meet the maximum figure for the acquisition time.
Delay from
CS until SDATA is three-state disabled. Measured with the load circuit in Figure 2 and defined as the time required for the output to cross the V or V
voltage.
IL
Data access time after SCLK falling edge. Measured with the load circuit in Figure 2 and defined as the time required for the output to cross the V voltage.
ns min SCLK low pulse width. ns min SCLK high pulse width.
SCLK to data valid hold time. Measured with the load circuit in Figure 2 and defined as the time required for the output to cross the V
SCLK falling edge to SDATA three-state. t taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
at which specifications are guaranteed.
SCLK
at which specifications are guaranteed.
SCLK
at which specifications are guaranteed.
SCLK
= 3.4 MHz, t2 has to be 192 ns
SCLK
IH
is derived from the measured time
8
IH
or VIL voltage.
or VIL
,
8
IH
200µAI
TO OUTPUT
PIN
C
L
50pF
200µAI
Figure 2. Load Circuit for Digital Output Timing Specifications
Rev. A | Page 9 of 28
OL
1.4V
OH
02643-002
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