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1.8 V, Micro-Power ,
a
Preliminary Technical Data
FEATURES
Specified for V
Low Power:
0.9 mW max at 60 kSPS with 3.6 V Supplies
0.4 mW max at 100 kSPS with 1.8 V Supplies
Fast Throughput Rate: 100 kSPS
Wide Input Bandwidth:
70dB SNR at 30 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface
SPI/QSPI/
Standby Mode: 0.5
6-Lead SOT-23 Package and 8 lead
APPLICATIONS
Battery Powered Systems
Medical Instruments
of 1.8 V to 3.6 V
DD
µµ
µWire/DSP Compatible
µµ
µA max
µµ
µSOIC
µµ
8/10/12-Bit ADCs in 6 Lead SOT-23
AD7466/AD7467/AD7468
FUNCTIONAL BLOCK DIAGRAM
V
DD
IN
AD7466/67/68
T/HV
GND
12/10/8-BIT
SUCCESSIVE
APPROXIMATION
ADC
SCLK
CONTROL LOGIC SDAT A
CS
Ramote Data Acquisition
Isolated Data Acquisition
GENERAL DESCRIPTION
The AD7466/AD7467/AD7468 are 12/10/8-bit, high
speed, low power, successive-approximation ADCs respectively. The parts operate from a single 1.8 V to 3.6 V
power supply and feature throughput rates up to 100
kSPS. The parts contain a low-noise, wide bandwidth
track/hold amplifier which can handle input frequencies in
excess of 100 kHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to
interface with microprocessors or DSPs. The input signal
is sampled on the falling edge of CS and the conversion is
also initiated at this point. There are no pipelined delays
associated with the part.
The AD7466/AD7467/AD7468 use advanced design techniques to achieve very low power dissipation at high
throughput rates.
The reference for the part is taken internally from V
This allows the widest dynamic input range to the ADC.
Thus the analog input range for the part is 0 to V
conversion rate is determined by the SCLK.
DD
DD.
. The
PRODUCT HIGHLIGHTS
1. Specified for Supply voltages of 1.8 V to 3.6 V
2. 8/10/12-Bit ADCs in a SOT-23 package.
3. High Throughput with Low Power Consumption
4. Flexible Power/Serial Clock Speed Management
The conversion rate is determined by the serial clock
allowing the conversion time to be reduced through the
serial clock speed increase. Automatic power down after
conversion, which allows the average power cunsumption
to be reduced when in powerdown. Power consumption
is 0.5 µA max when in powerdown.
5. Reference derived from the power supply.
6. No Pipeline Delay
The part features a standard successive-approximation
ADC with accurate control of the conversions via a CS
input.
REV. PrC 07/01
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One T ec hnology Wa y , P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 Analog Devices, Inc., 2001
AD7466–SPECIFICATIONS
1
(VDD = 1.8 V to 3.6 V, f
T
to T
MIN
, unless otherwise noted.)
MAX
= 2.4 MHz, f
SCLK
= 100 kSPS unless otherwise noted; TA =
SAMPLE
Parameter B Version
DYNAMIC PERFORMANCE fIN = 30 kHz Sine Wave
Signal-to-Noise + Distortion (SINAD)
Signal-to-Noise Ratio (SNR)
2
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)
2
2
2
2
1, 2
Unit Test Conditions/Comments
70 dB min
71 dB min
–78 dB typ
–80 dB typ
fa = 29.1 kHz, fb = 29.9 kHz
Second Order Terms –78 dB typ
Third Order Terms –78 dB typ
Aperture Delay 10 ns typ
Aperture Jitter 30 ps typ
Full Power Bandwidth TBD MHz typ @ 3 dB
Full Power Bandwidth TBD MHz typ @ 0.1 dB
DC ACCURACY
Resolution 12 Bits
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
3
3
2
2
±1.5 LSB max
±0.6 LSB typ
–0.9/+1.5 LSB max Guaranteed No Missed Codes to 12 Bits
±0.75 LSB typ
±1.5 LSB max
±1.5 LSB max
ANALOG INPUT
Input Voltage Ranges 0 to V
DD
V
DC Leakage Current ±1 µA max
Input Capacitance 30 pF typ
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
INH
INL
Input Current, IIN, SCLK Pin ±1 µ A ma x Typically 10 nA, V
Input Current, IIN, CS Pin ±1 µA typ
Input Capacitance, C
2,3
IN
0.7(VDD) V min VDD = 1.8 V to 3.6 V
0.4 V max
IN
10 pF max
= 0 V or V
LOGIC OUTPUTS
Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current ±10 µA max
Floating-State Output Capacitance
OH
OL
2,3
VDD – 0.2 V m in I
0.2 V max I
10 pF max
= 200 µA; VDD = 1.8 V to 3.6 V
SOURCE
= 200 µA
SINK
Output Coding Straight (Natural) Binary
CONVERSION RATE
Conversion Time 6.66 µs max Sixteen SCLK Cycles
Track/Hold Acquisition Time TBD ns max Full-Scale Step Input
TBD ns max Sine Wave Input
Throughput Rate 100 kSPS max See Serial Interface Section
POWER REQUIREMENTS
V
DD
I
DD
1.8/3.6 V min/max
Digital I/Ps = 0 V or V
DD
Normal Mode (Operational) 350 µA max VDD = 3 V. SCLK On or Off
200 µA max VDD = 1.8 V. SCLK On or Off
DD
Power-Down 0.5 µA max SCLK Off
Power Dissipation
4
80 µA max SCLK On
Normal Mode (Operational) TBD mW max VDD = 3 V. f
mW max VDD = 1.8 V. f
Power-Down 1.5 µW max VDD = 3 V. SCLK Off
0.9 µW max VDD = 1.8 V. SCLK Off
NOTES
1
Temperature ranges as follows: B Versions: –40°C to +85°C.
2
See Terminology.
3
Sample tested at 25°C to ensure compliance.
4
See Power Versus Throughput Rate section.
Specifications subject to change without notice.
–2– REV. PrC
SAMPLE
SAMPLE
= TBD
= TBD
1
AD7467–SPECIFICATIONS
Parameter B Version
DYNAMIC PERFORMANCE fIN = 30 kHz Sine Wave,
Signal-to-Noise + Distortion (SINAD)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)
2
2
2
2
T
to T
MIN
, unless otherwise noted.)
MAX
61 dB min
–73 dB max
–74 dB max
(VDD = 1.8 V to 3.6 V, f
= 2.4 MHz, f
SCLK
1, 2
Unit Test Conditions/Comments
= 100 kSPS unless otherwise noted; TA =
SAMPLE
fa = 29.1 kHz, fb = 29.9 kHz
Second Order Terms –7 8 dB typ
Third Order Terms –78 dB typ
Aperture Delay 1 0 ns typ
Aperture Jitter 30 ps typ
Full Power Bandwidth TBD MHz typ @ 3 dB
Full Power Bandwidth TBD MHz typ @ 0.1 dB
DC ACCURACY
Resolution 10 Bits
Integral Nonlinearity ±1 LSB max
Differential Nonlinearity ±0.9 LSB max Guaranteed No Missed Codes to 10 Bits
Offset Error ±1 LSB max
Gain Error ±1 LSB max
ANALOG INPUT
Input Voltage Ranges 0 to V
DD
V
DC Leakage Current ±1 µA max
Input Capacitance 30 pF typ
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Current, IIN, CS Pin ±1 µA typ
Input Capacitance, C
INH
INL
, SCLK Pin ±1 µA m ax Typically 10 nA, V
IN
2,3
IN
0.7(V
DD)
0.4 V max
10 pF max
V min VDD = 1.8 to 3.6 V
= 0 V or V
IN
DD
LOGIC OUTPUTS
Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current ±10 µA max
Floating-State Output Capacitance
OH
OL
2,3
VDD – 0.2 V min I
0.2 V max I
10 pF max
SOURCE
= 200 µA
SINK
= 200 µA;
Output Coding Straight (Natural) Binary
CONVERSION RATE
Conversion Time 5 µs max 12 SCLK Cycles with SCLK at 20 MHz
Track/Hold Acquisition Time TBD ns max
Throughput Rate 100 kSPS max See Serial Interface Section
POWER REQUIREMENTS
V
DD
I
DD
1.8/3.6 V min/max
Digital I/Ps = 0 V or V
DD
Normal Mode (Operational) 350 µA max VDD = 3 V . SCLK On or Off
200 µA max V
= 1.8 V . SCLK On or Off
DD
Power-Down Mode 0.5 µA max SCLK Off
Power Dissipation
4
Normal Mode (Operational) TBD mW max VDD = 3 V. f
Power-Down 1.5 µW max V
80 µA max SCLK On
TBD mW max V
= 1.8 V. f
DD
= 3 V. SCLK Off
DD
SAMPLE
SAMPLE
= 100 kSPS
= TBD
0.9 µW max VDD = 1.8 V. SCLK Off
NOTES
1
Temperature ranges as follows: B Versions: –40°C to +85°C.
2
See Terminology.
3
Sample tested at 25°C to ensure compliance.
4
See Power Versus Throughput Rate section.
Specifications subject to change without notice.
–3–
REV. PrC
1
AD7468–SPECIFICATIONS
(VDD = 1.8 V to 3.6 V, f
T
to T
MIN
, unless otherwise noted.)
MAX
Parameter B Version
DYNAMIC PERFORMANCE fIN =30 kHz Sine Wave, f
Signal-to-Noise + Distortion (SINAD)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)
2
2
2
2
49 dB min
–65 dB max
–65 dB max
= 2.4 MHz, f
SCLK
1, 2
Unit Test Conditions/Comments
= 100 kSPS unless otherwise noted; TA =
SAMPLE
fa = 29.1 kHz, fb = 29.9 kHz
SAMPLE
Second Order Terms –6 8 dB typ
Third Order Terms –6 8 dB typ
Aperture Delay 10 ns typ
Aperture Jitter 30 ps typ
Full Power Bandwidth TBD MHz typ @ 3 dB
Full Power Bandwidth TBD MHz typ @ 0.1 dB
DC ACCURACY
2
Resolution 8 Bits
Integral Nonlinearity ±0.5 LSB max
Differential Nonlinearity ±0.5 LSB max Guaranteed No Missed Codes to 8 Bits
Offset Error ±0.5 LSB max
Gain Error ±0.5 LSB max
Total Unadjusted Error (TUE) ±0.5 LSB max
ANALOG INPUT
Input Voltage Ranges 0 to V
DD
V
DC Leakage Current ±1 µA max
Input Capacitance 30 pF typ
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Current, IIN, CS Pin ±1 µA typ
Input Capacitance, C
INH
INL
, SCLK Pin ±1 µ A max Typically 10 nA, V
IN
2,3
IN
0.7(V
DD)
0.4 V max
10 pF max
V min VDD = 1.8 to 3.6 V
= 0 V or V
IN
LOGIC OUTPUTS
Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current ±10 µA max
Floating-State Output Capacitance
OH
OL
3, 4
VDD – 0.2 V min I
0.2 V max I
10 pF max
= 200 µA; VDD = 1.8 V to 3.6 V
SOURCE
= 200 µA
SINK
Output Coding Straight (Natural) Binary
CONVERSION RATE
Conversion Time 4.166 µs max 10 SCLK Cycles with SCLK at 2.4 MHz
Track/Hold Acquisition Time TBD ns max
Throughput Rate 100 kSPS max See Serial Interface Section
POWER REQUIREMENTS
V
DD
I
DD
1.8/3.6 V min/max
Digital I/Ps = 0 V or V
DD
Normal Mode (Static) 350 µA max VDD = 3V. SCLK On or Off
200 µA max V
= 1.8 V . SCLK On or Off
DD
Power-Down Mode 0.5 µA max SCLK Off
Power Dissipation
5
Normal Mode (Operational) TBD mW max VDD = 3 V. f
Power-Down 1.5 µW max V
80 µA max SCLK On
TBD mW max V
= 1.8 V. f
DD
= 3 V. SCLK Off
DD
SAMPLE
SAMPLE
= TBD
= TBD
0.9 µW max VDD = 1.8 V. SCLK Off
NOTES
1
Temperature ranges as follows: B Versions: –40°C to +85°C.
2
See Terminology.
3
Sample tested at 25°C to ensure compliance.
4
See Power Versus Throughput Rate section.
Specifications subject to change without notice.
=100kSPS
DD
–4– REV. PrC
AD7466/AD7467/AD7468
1
TIMING SPECIFICATIONS
(VDD = +1.8 V to +3.6 V; TA = T
Parameter AD7466 Units Description
2
f
SCLK
10 kHz min
TBD MHz max
t
CONVERT
t
quiet
16* t
SCLK
TBD ns min Minimum Quiet Time required between Bus Relinquish
and start of next conversion
t
1
t
2
3
t
3
3
t
4
t
5
t
6
t
7
4
t
8
5
t
power-up
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 Volts.
2
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4
t8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to
remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the
part and is independent of the bus loading.
5
See Power-up Time section.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C unless otherwise noted)
T BD ns min Minimum CS Pulse Width
10 ns min CS to SCLK Setup Time
TBD ns max Delay from CS Until SDATA 3-State Disabled
TBD ns max Data Access Time After SCLK Falling Edge
0.4t
0.4t
SCLK
SCLK
ns min SCLK Low Pulse Width
ns min SCLK High Pulse Width
T BD ns min SCLK to Data Valid Hold Time
TBD ns max SCLK falling Edge to SDATA High Impedance
TBD µs typ Power up time from Full Power-down.
1
MIN
to T
, unless otherwise noted.)
MAX
VDD to GND –0.3 V to TBD V
Analog Input Voltage to GND –0.3 V to V
+ 0.3 V
DD
Digital Input Voltage to GND –0.3 V to TBDV
Digital Output Voltage to GND –0.3 V to V
Input Current to Any Pin Except Supplies
2
Operating Temperature Range
Commercial (A, B Version) –40°C to +85°C
Storage Temperature Range –65°C to +150°C
Junction Temperature +150°C
+ 0.3 V
DD
±10 mA
OUTPUT
PIN
TO
C
L
50pF
SOT-23 Package, Power Dissipation 450 mW
θ
Thermal Impedance 229.6°C/W (SOT23)
JA
205.9°C/W (µSOIC)
θ
Thermal Impedance 91.99°C/W (SOT23)
JC
43.74°C/W (µSOIC)
Figure 1. Load Circuit for Digital Output Timing
Lead Temperature, Soldering
Vapor Phase (60 secs) +215°C
Infared (15 secs) +220°C
ESD TBD
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch up.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7466/AD7467/AD7468 feature proprietary ESD protection circuitr y, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
–5–REV. PrC
200µA
200µA
I
Specifications
OL
I
+1.6V
OH
AD7466/AD7467/AD7468
PIN FUNCTION DESCRIPTION
Pin Pin
No. Mnemonic Function
6 CS Chip Select. Active low logic input. This input provides the dual function of initiating con-
versions on the AD7466/AD7467/AD7468 and also frames the serial data transfer.
1V
DD
2 GND Analog Ground. Ground reference point for all circuitry on the AD7466/AD7467/AD7468.
3V
IN
5 SDATA Data Out. Logic Output. The conversion result from the AD7466/AD7467/AD7468 is pro-
4 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part.
Power Supply Input. The VDD range for the AD7466/67/68 is from +1.8 V to +3.6 V.
All analog input signals should be referred to this GND voltage.
Analog Input. Single-ended analog input channel. The input range is 0 to VDD.
vided on this output as a serial data stream. The bits are clocked out on the falling edge of
the SCLK input. The data stream from the AD7466 consists of four leading zeros followed
by the 12 bits of conversion data which is provided MSB first. The data stream for the
AD7467 consists of four leading zeros followed by 10 bits of data. The datastream for the
AD7468 consists of four leading zeros followed by 8 bits of data.
This clock input is also used as the clock source for the AD7466/AD7467/AD7468 conversion process.
ORDERING GUIDE
Temperature Linearity Package Branding
Model Range Error (LSB)
1
Option
2
Information
AD7466BRT –40°C to +85°C ±1 max RT-6 CLB
AD7467BRT –40°C to +85°C ±1 max RT-6 CMB
AD7468BRT –40°C to +85°C ±0.5 max RT-6 CNB
AD7466BRM –40°C to +85°C ±1 max RM-8 CQB
AD7467BRM –40°C to +85°C ±1 max RM-8 CRB
AD7468BRM –40°C to +85°C ±0.5 max RM-8 CSB
EVAL-AD7466CB
EVAL-AD7467CB
EVAL-CONTROL BRD2
NOTES
1
Linearity Error here refers to integral linearity error.
2
RT = SOT-23, RM = µSOIC.
3
This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.
4
This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
3
3
4
AD7466/67/68 PINCONFIGURATION
AD7466/67/68 SOT-23
V
DD
GND
V
IN
1
AD7466/7/8
2
TOP VIEW
3
(Not to Scale)
6
CS
SDATA
5
SCLK
4
AD7466/67/68
CS
1
2
SDA T A
SCLK
AD7466/7/ 8
TOP VIEW
3
(Not to Scale)
45
NC
µµ
µSOIC
µµ
–6– REV. PrC
V
8
DD
GND
7
V
6
IN
NC
AD7466/AD7467/AD7468
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function.
For the AD7466/67/68 the endpoints of the transfer
function are zero scale, a point 1 LSB below the first
code transition, and full scale, a point 1 LSB above the
last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1
LSB change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 . . .
000) to (00 . . . 001) from the ideal, i.e AGND + 1
LSB.
Gain Error
This is the deviation of the last code transition (111 . . .
110) to (111 . . . 111) from the ideal (i.e., V
– 1LSB)
REF
after the offset error has been adjusted out.
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode at the
end of conversion. Track/Hold acquisition time is the
time required for the output of the track/hold amplifier
to reach its final value, within ±0.5 LSB, after the end
of conversion. See serial interface timing section for
more details.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is
the rms amplitude of the fundamental. Noise is the sum
of all nonfundamental signals up to half the sampling
frequency (f
/2), excluding dc. The ratio is dependent on
S
the number of quantization levels in the digitization
process; the more levels, the smaller the quantization
noise. The theoretical signal to (noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is
given by:
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB and for a 10-
bit converter this is 62dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms
sum of harmonics to the fundamental. For the AD7466/
AD7467/AD7468, it is defined as:
2
2
2
2
V
V
V
+
THD (dB)=20 log
where V
V
3
is the rms amplitude of the fundamental and V2,
1
, V4, V5 and V6 are the rms amplitudes of the second
2
+
3
V
+
4
V
1
2
V
+
5
6
through the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of
the rms value of the next largest component in the ADC
output spectrum (up to f
/2 and excluding dc) to the rms
S
value of the fundamental. Normally, the value of this
specification is determined by the largest harmonic in the
spectrum, but for ADCs where the harmonics are buried
in the noise floor, it will be a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa
and fb, any active device with nonlinearities will create
distortion products at sum and difference frequencies of
mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation
distortion terms are those for which neither m nor n are
equal to zero. For example, the second order terms include (fa + fb) and (fa – fb), while the third order terms
include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
The AD7466/AD7467/AD7468 are tested using the CCIF
standard where two input frequencies are used. In this
case, the second order terms are usually distanced in frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are
specified separately. The calculation of the
intermodulation distortion is as per the THD specification
where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the
fundamentals expressed in dBs.
–7–REV. PrC
AD7466/AD7467/AD7468
AD7466/AD7467/AD7468 TYPICAL PERFORMANCE
CURVES
Figure 2 shows a typical FFT plot for the AD7466 at 100
kHz sample rate and 30 kHz input frequency.
0
E
L
0
IT
T
0
000
0000
TITLE
Figure 2. AD7466 Dynamic Performance at 100 kSPS
0
E
L
0
IT
T
0
E
L
0
IT
T
0
000
0000
TITLE
Figure 4. PSRR vs Supply Ripple Frequency
0
E
L
0
IT
T
0
000
0000
TITLE
Figure 3. AD7466 SINAD vs Analog Input Frequency at 100
kSPS
0
000
0000
TITLE
Figure 5. AD7466 THD vs Analog Input Frequency at 100
kSPS
–8– REV. PrC
CIRCUIT INFORMATION
The AD7466/AD7467/AD7468 are fast, micro-power, 12/
10/8-bit, A/D converters respectively. The parts can be
operated from a +1.8 V to +3.6 V supply. When operated
from any supply voltage within this range, the AD7466/
AD7467/AD7468 is capable of throughput rates of 100
kSPS when provided with a 2 MHz clock.
The AD7466/AD7467/AD7468 provides the user with an
on-chip track/hold, A/D converter, and a serial interface
housed in a tiny 6-pin SOT-23 package, which offers the
user considerable space saving advantages over alternative
solutions. The serial clock input accesses data from the
part but also provides the clock source for the successiveapproximation A/D converter. The analog input range is 0
to V
. An external reference is not required for the ADC
DD
and neither is there a reference on-chip. The reference for
the AD7466/AD7467/AD7468 is derived from the power
supply and thus gives the widest dynamic input range.
The AD7466/AD7467/AD7468 also features an automatic
power-down mode option to allow power saving between
conversions. The power-down feature is implemented
across the standard serial interface as described in the
“Modes of Operation” section.
AD7466/AD7467/AD7468
CHARGE
REDISTRIBUTION
SAMPLING
CAPACITOR
SW1
A
AGND
B
CONVERSION
PHASE
V
/ 2
DD
SW2
COMPARATOR
V
IN
Figure 9. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding of the AD7466/AD7467/AD7468 is
straight binary. The designed code transitions occur at
successive integer LSB values (i.e., 1LSB, 2LSBs, etc.).
The LSB size is = V
is = V
V
DD
/1024 for the AD7467, and the LSB size is =
DD
/256 for the AD7468 . The ideal transfer characteristic
/4096 for the AD7466,the LSB size
DD
for the AD7466/AD7467/AD7468 is shown in figure 10
below.
DAC
CONTROL
LOGIC
CONVERTER OPERATION
The AD7466/AD7467/AD7468 is a successive approximation analog-to-digital converter based around a charge
redistribution DAC. Figures 8 and 9 show simplified
schematics of the ADC. Figure 8 shows the ADC during
its acquisition phase. SW2 is closed and SW1 is in position A, the comparator is held in a balanced condition and
the sampling capacitor acquires the signal on V
SAMPLING
CAPA CITOR
SW1
A
AGND
B
ACQUI SITION
PHASE
VDD / 2
SW2
COMPARATOR
V
IN
.
IN
CHARGE
REDISTRIBUTION
DAC
CONT ROL
LOGIC
Figure 8. ADC Acquisition Phase
When the ADC starts a conversion, see figure 9, SW2 will
open and SW1 will move to position B causing the comparator to become unbalanced. The Control Logic and
the Charge Redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor
to bring the comparator back into a balanced condition.
When the comparator is rebalanced the conversion is complete. The Control Logic generates the ADC output code.
Figure 10 shows the ADC transfer function.
111...111
111...110
E
D
111...000
O
C
C
011...111
D
A
000...010
000...001
000...000
1LSB
0V
ANALOG INPUT
1LSB = VDD/4096 (AD7466)
1LSB = VDD/1024 (AD7467)
1LSB = VDD/256 (AD7468)
+VDD-1LSB
Figure 10. AD7466/67/68 Transfer Characteristic
–9–REV. PrC
AD7466/AD7467/AD7468
TYPICAL CONNECTION DIAGRAM
Figure 11 shows a typical connection diagram for the
AD7466/AD7467/AD7468. V
V
and as such VDD should be well decoupled. This pro-
DD
vides an analog input range of 0V to V
is taken internally from
REF
. For the
DD
AD7466 the conversion result is output in a 16-bit word
with four leading zeroes followed by the MSB of the 12bit result. The AD7467 conversion result consists of four
leading zeros followed by the MSB of the 10-bit result.
The AD7468 conversion result consists of four leading
zeros followed by the MSB of the 8-bit result.
Alternatively, because the supply current required by the
AD7466/AD7467/AD7468 is so low, a presision reference
can be used as the supply source to the AD7466/AD7467/
AD7468. A REF19x voltage reference (REF193 for 3V,
REF192 for 2.5 V ) can be used to supply the required
voltage to the ADC - see figure 11. This configuration is
especially useful if your power supply is quite noisy or if
the system supply voltages are at some value other than 3V
(e.g. 2.5V). The REF19x will output a steady voltage to
the AD7466/AD7467/AD7468. In applications where
power consumption is important, the automatic power
down mode of the ADC and the sleep mode of the
REF19x reference should be used to improve power performance. See Modes of Operation section of the
datasheet.
Analog Input
Figure 12 shows an equivalent circuit of the analog input
sturcture of the AD7466/AD7467/7468. The two diodes
D1 and D2 provide ESD protection for the analog inputs.
Care must be taken to ensure that the analog input signal
never exceeds the supply rails by more than 200mV. This
will cause these diodes to become forward biased and start
conducting current into the substrate. The capacitor C1 in
figure 12 is typically about 4pF and can primarily be attributed to pin capacitance. The resistor R1 is a lumped
component made up of the on resistance of a switch. This
resistor is typically about 100Ω.
The capacitor C2 is the
ADC sampling capacitor and has a capacitance of 16pF
typically. For ac applications, removing high frequency
components from the analog input signal is recommended
by use of a band-pass filter on the relevant analog input
pin. In applications where harmonic distortion and signal
to noise ratio are critical the analog input should be driven
V
DD
D1
V
IN
C2
16PF
R1
680nF
0V toV
INPUT
DD
1mA
0.1µF
V
AD7466/67/68
DD
V
IN
GND
+3V
1µF
TANT
REF193
SCLK
SDATA
CS
SERIAL
INTERFACE
0.1µF10µF
+5V
SUPPLY
µC/µP
Figure 11. REF193 as Power Supply to AD7466/AD7467/
AD7468
C1
4pF
D2
CONVERSION PHASE - SWITCH OPEN
TRACK PHASE - SWITCH CLOSED
Figure 12. Equivalent Analog Input Circuit
from a low impedance source. Large source impedances
will significantly affect the ac performance of the ADC.
This may necessitate the use of an input buffer amplifier.
The choice of the op amp will be a function of the particular application.
When no amplifier is used to drive the analog input the
source impedance should be limited to low values. The
maximum source impedance will depend on the amount of
total harmonic distortion (THD) that can be tolerated.
The THD will increase as the source impedance increases
and performance will degrade. Figure 13 shows a graph of
the Total Harmonic Distortion vs. analog input signal
frequency for different source impedances when using a
supply voltage of 2.7V and sampling at a rate of 100
kSPS.
–10– REV. PrC
AD7466/AD7467/AD7468
0
E
L
0
IT
T
0
000
0000
TITLE
Figure 13. THD vs. Analog Input Frequency for Various
Source Impedance
Digital Inputs
The digital inputs applied to the AD7466/AD7467/
AD7468 are not limited by the maximum ratings which
limit the analog inputs. One advantage of SCLK and CS
not being restricted by the V
+ 0.3V limit is the fact that
DD
power supply sequencing issues are avoided. If CS or
SCLK are applied before V
then there is no risk of
DD
latch-up as there would be on the analog inputs if a signal
greater than 0.3V was applied prior to V
DD
.
MODE OF OPERATION
The AD7466/AD7467/AD7468 automatically enters
powerdown at the end of each conversion. This mode of
operation is designed to provide flexible power management options and to optimize the power dissipation/
throughput rate ratio for differing application requirements. Figure 14 shows the general diagram of the
operaion of the AD7466/AD7467/AD7468. On the falling
CS edge the part begins to power up and the Track and
Hold, which was in Hold while the part was in power
down, will go into track mode. When operating the part
with a 2.4 MHz clock it will take 2 clock cycles to fully
power up the part and acquire the input signal. On the
third SCLK falling edge after the CS falling edge the
Track and Hold will return to hold mode. For the
AD7466 sixteen serial clock cycles are required to complete the conversion and access the complete conversion
result.On the 16th SCLK falling edge the part will automatically enter power down . The AD7467 will automatically enter powerdown on the fourteenth SCLK falling
edge. The AD7468 will automatically enter powerdown
on the twelveth SCLK falling edge. When supplies are
first applied to the AD7466/AD7467/AD7468 a dummy
conversion should be performed to ensure that the part is
in powerdown mode.
The conversion is iniated on the falling edge of CS as
described in the Serial Interface section. For the AD7466
if CS is brought high any time before the 16th SCLK
falling edge the part will enter power down and the conversion that was initiated by the falling edge of CS will be
terminated and SDATA will go back into tri-state. This
also applies for the AD7467/AD7468, if CS is brought
high before the conversion is complete (the 14th SCLK
falling edge for the AD7467, and the 12th SCLK falling
edge for the AD7468) the part will enter powerdown and
the conversion will be terminated.
Once a data transfer is complete (SDATA has returned to
tri-state), another conversion can be initiated after the
quiet time, t
, has elapsed by bringing CS low again.
quiet
THE PART BEGINS
TO POWER U P
1
AD7468 ENTERS
POWERDOWN
3
2
12
AD7467 ENTERS
14
VALID DATA
Figure 14. Normal Mode Operation
–11–REV. PrC
POWERDOWN
16
AD7466 ENTERS
POWERDOWN
AD7466/AD7467/AD7468
SERIAL INTERFACE
Figure 15, 16, 17 show the detailed timing diagram for
serial interfacing to the AD7466/AD7467/AD7468.The
serial clock provides the conversion clock and also controls the transfer of information from the ADC during a
conversion.
On the CS falling edge the part begins to power up. The
falling edge of CS puts the track and hold into track mode
and takes the bus out of tristate. The conversion is also
initiated at this point and will require 16 SCLK cycles to
complete. On the third SCLK falling edge the part should
be fully powered up, as shown in figure 15 at point B. On
the third SCLK falling edge after the CS falling edge the
track and hold will return to hold. On the 16th SCLK
falling edge the SDATA line will go back into tristate and
the AD7466 will enter power down. If the rising edge of
CS occurs before 16 SCLKs have elapsed then the conversion will be terminated and the SDATA line will go back
into tri-state and the part will enter power down, otherwise
SDATA returns to tri-state on the 16th SCLK falling
edge as shown in Figure 15. Sixteen serial clock cycles
are required to perform the conversion process and to
access data from the AD7466.
For the AD7467, the fourteenth SCLK falling edge will
cause the SDATA line to go back into tri-state and the
part will enter powerdown. If the rising edge of CS occurs
before 14 SCLKs have elapsed then the conversion will be
terminated and the SDATA line will go back into tri-state
and the AD7467 will enter powerdown, otherwise SDATA
returns to tri-state on the 14th SCLK falling edge as
ahown in figure 16. Fourteen serial clock cycles are required to perform the conversion process and to access
data from the AD7467.
For the AD7468, the 12th SCLK falling edge will cause
the SDATA line to go back into tri-state and the part will
enter powerdown. If the rising edge of CS occurs before
12 SCLKs have elapsed then the conversion will be terminated and the SDATA line will go back into tri-state and
the AD7468 will enter powerdown, otherwise SDATA
returns to tri-state on the 12th SCLK falling edge as
ahown in figure 17. Twelve serial clock cycles are required to perform the conversion process and to access
data from the AD7468.
CS going low provides the first leading zero to be read in
by the microcontroller or DSP. The remaining data is
then clocked out by subsequent SCLK falling edges beginning with the 2nd leading zero, thus the first falling
clock edge on the serial clock has the first leading zero
provided and also clocks out the second leading zero. For
the Ad7466 the final bit in the data transfer is valid on the
sixteenth falling edge, having being clocked out on the
previous (15th) falling edge.
CS
SCLK
SDATA
CS
SCLK
SDATA
CS
SCLK
SDATA
3-STATE
3-STATE
3-STATE
t
2
Z
t
1
t
3
t
2
Z
2
1
t
Z
2
ZERO
ZERO
4 LEADING ZERO'S
1
t
3
3
2
ZERO
4 LEADING ZERO'S
2
ZEROZERO
4 LEADINGZERO'S
t
convert
B
34
ZERO
t
DB11
t
6
5
t
4
7
DB10
13
14
t
DB2
5
DB1
15
16
t
8
DB0
Figure 15. AD7466 Serial Interface Timing Diagram
t
convert
B
34
ZEROZERO
t
DB9
t
6
5
t
4
7
DB8
13
t
5
DB0
14
t
8
Figure 16. AD7467 Serial Interface Timing Diagram
t
convert
B
34
ZERO
t
6
t
5
t
4
DB7
8 BITS OF DATA
11
12
t
7
t
8
DB0
3-STATE
t
quiet
3-STATE
t
quiet
3-STATE
t
quie
t
Figure 17. AD7468 Serial Interface Timing Diagram
–12– REV. PrC
AD7466/AD7467/AD7468
MICROPROCESSOR INTERFACING
The serial interface on the AD7466/AD7467/AD7468
allows the part to be directly connected to a range of many
different microprocessors. This section explains how to
interface the AD7466/AD7467/AD7468 with some of the
more common microcontroller and DSP serial interface
protocols.
AD7466/7/8 to TMS320C5xC54x
The serial interface on the TMS320C5x uses a continuous
serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices
like the AD7466/67/68. The CS input allows easy interfacing between the TMS320C5x and the AD7466/67/68
without any glue logic required. The serial port of the
TMS320C5x/C54x is set up to operate in burst mode
with internal CLKX (TX serial clock) and FSX (TX
frame sync). The serial port control register (SPC) must
have the following setup: FO = 0, FSM = 1, MCM = 1
and TXM = 1. The format bit, FO, may be set to 1 to set
the word length to 8-bits, in order to implement the
power-down mode on the AD7466/67/68.
The connection diagram is shown in Figure 18. It should
be noted that for signal processing applications, it is imperative that the frame synchronisation signal from the
TMS320C5x/C54x will provide equidistant sampling.
AD7466/7/8*
SCLK
SDATA
CS
*AdditionalPins omitted for clarity
TMS320C5x/C54x*
CLKX
CLKR
DR
FSX
FSR
Figure 18. Interfacing to the TMS320C5x
AD7466/7/8 to ADSP21xx
The ADSP21xx family of DSPs are interfaced directly to
the AD7466/67/68 without any glue logic required. The
SPORT control register should be set up as follows:
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data words
ISCLK = 1, Internal serial clock
TFSR = RFSR = 1, Frame every word
IRFS = 0,
ITFS = 1.
The connection diagram is shown in Figure 19. The
ADSP21xx has the TFS and RFS of the SPORT tied
together, with TFS set as an output and RFS set as an
input. The DSP operates in Alternate Framing Mode and
the SPORT control register is set up as described. The
Frame synchronisation signal generated on the TFS is
tied to CS and as with all signal processing applications
equidistant sampling is necessary. However, in this example, the timer interrupt is used to control the sampling
rate of the ADC and under certain conditions, equidistant
sampling may not be acheived.
The Timer registers etc. are loaded with a value
which will provide an interrupt at the required sample
interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). The TFS is
used to control the RFS and hence the reading of data.
The frequency of the serial clock is set in the SCLKDIV
register. When the instrustion to transmit with TFS is
given, (i.e. AX0=TX0), the state of the SCLK is checked.
The DSP will wait until the SCLK has gone High, Low
and High before transmission will start. If the timer and
SCLK values are chosen such that the instruction to transmit occurs on or near the rising edge of SCLK, then the
data may be transmitted or it may wait until the next clock
edge.
For example, the ADSP2111 has a master clock frequency
of 16MHz. If the SCLKDIV register is loaded with the
value 3 then a SCLK of 2MHz is obtained, and 8 master
clock periods will elapse for every 1 SCLK period. If the
timer registers are loaded with the value 803, then 100.5
SCLKs will occur between interrupts and subsequently
between transmit instructions. This situation will result in
non-equidistant sampling as the transmit instruction is
occuring on a SCLK edge. If the number of SCLKs between interrupts is a whole integer figure of N then equidistant sampling will be implemented by the DSP.
AD7466/7/8*
SCLK
SDATA
CS
*Additional Pins omitted for clarity
ADSP21xx*
SCLK
DR
RFS
TFS
Figure 19. Interfacing to the ADSP-21xx
AD7466/67/68 to DSP56xxx
The connection diagram in figure 20 shows how the
AD7466/67/68 can be connected to the SSI (Synchronous
Serial Interface) of the DSP56xxx family of DSPs from
Motorola. The SSI is operated in Synchronous Mode
(SYN bit in CRB =1) with internally generated 1-bit
clock period frame sync for both TX and RX (bits FSL1
=1 and FSL0 =0 in CRB). Set the word length to 16 by
setting bits WL1 =1 and WL0 = 0 in CRA. It should be
noted that for signal processing applications, it is imperative that the frame synchronisation signal from the
DSP56xxx will provide equidistant sampling.
–13–REV. PrC
AD7466/AD7467/AD7468
AD7466/7/8*
SCLK
SDATA
CS
*Additional Pins omitted for clarity
DSP56xxx*
SCK
SRD
SC2
Figure 20. Interfacing to the DSP56xx
AD7466/67/68 to MC68HC16
The Serial Peripheral Interface (SPI) on the MC68HC16
is configured for Master Mode (MSTR = 1), Clock Polarity Bit (CPOL) = 1 and the Clock Phase Bit (CPHA)
= 0. The SPI is configured by writing to the SPI Control
Register (SPCR) - see 68HC16 user manual. The serial
transfer will take place as a 16-bit operation when the
SIZE bit in the SPCR register is set to SIZE = 1. A connection diagram is shown in figure 21.
AD7466/7/8*
SCLK
SDATA
CS
MC68HC16*
SCLK/PMC2
MISO/PMC0
SS/PMC3
*Additio nalPins omitted for clarity
Figure 21. Interfacing to the MC68HC16
–14– REV. PrC
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
6-lead SOT23 (RT-6)
0.122 (3.10)
0.106 (2.70)
AD7466/AD7467/AD7468
0.071 (1.80)
0.059 (1.50)
0.051 (1.30)
0.035 (0.90)
0.122 ( 3. 1 0)
0.114 ( 2. 9 0)
0.006 ( 0. 1 5)
0.002 ( 0. 0 5)
SEATING
PIN 1
0.006 (0.15)
0.000 (0.00)
0. 122 ( 3.10)
0. 114 ( 2.90)
8
1
PIN 1
0.0256 (0.65) BSC
0. 120 ( 3.05)
0. 112 ( 2.84)
0. 018 (0. 46)
0. 008 (0. 20)
PLANE
4 5 6
0.118 (3.00)
1
0.075 (1.90)
2
BSC
0.020 (0.50)
0.010 (0.25)
0.098 (2.50)
3
0.037 (0.95) BSC
0.057 (1.45)
0.035 (0.90)
SEATING
PLANE
0.009 (0.23)
0.003 (0.08)
8-lead microSOIC (RM-8)
5
0.199 ( 5. 05)
0.187 ( 4. 75)
4
0. 043 ( 1.09)
0. 037 ( 0.94)
0.011 ( 0. 2 8)
0.003 ( 0. 0 8)
0. 120 ( 3.05)
0. 112 ( 2.84)
33°
27°
10
°
0
°
0.028 ( 0. 7 1)
0.016 ( 0. 4 1)
0.022 (0.55)
0.014 (0.35)
–15–REV. PrC
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