ANALOG DEVICES AD7457 Service Manual

Low Power, Pseudo Differential, 100 kSPS

V

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FEATURES

Specified for VDD of 2.7 V to 5.25 V
Low power:

DD

= 3 V

DD

= 5 V

0.9 mW max at 100 kSPS with V

3 mW max at 100 kSPS with V
Pseudo differential analog input
Wide input bandwidth:

70 dB SINAD at 30 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface—SPI®-/QSPI™-/

MICROWIRE™-/DSP-compatible
Automatic power-down mode
8-lead SOT-23 package

APPLICATIONS

Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation

GENERAL DESCRIPTION

The AD7457 is a 12-bit, low power, successive approximation
(SAR) analog-to-digital converter that features a pseudo
differential analog input. This part operates from a single 2.7 V
to 5.25 V power supply and features throughput rates of up to
100 kSPS.

The part contains a low noise, wide bandwidth, differential
track-and-hold (T/H) amplifier that can handle input frequen­cies in excess of 1 MHz. The reference voltage for the AD7457 is
applied externally to the V
V

, depending on what suits the application.

DD

The conversion process and data acquisition are controlled

CS

using

and the serial clock, allowing the device to interface
with microprocessors or DSPs. The SAR architecture of this
part ensures that there are no pipeline delays.

The AD7457 uses advanced design techniques to achieve very
low power dissipation.

pin and can range from 100 mV to

REF

12-Bit ADC in an 8-Lead SOT-23

AD7457

FUNCTIONAL BLOCK DIAGRAM

V

DD

V

IN+

V

IN

–

REF

T/H

AD7457

GND

PRODUCT HIGHLIGHTS

1. Operation with 2.7 V to 5.25 V power supplies.

2. Low power consumption. With a 3 V supply, the AD7457

offers 0.9 mW maximum power consumption for a
100 kSPS throughput rate.

3. Pseudo differential analog input.

4. Flexible power/serial clock speed management. The

conversion rate is determined by the serial clock, allowing
the power to be reduced as the conversion time is reduced
through the serial clock speed increase. Automatic power­down after conversion allows the average power consump­tion to be reduced.

5. Variable voltage reference input.

6. No pipeline delays.

7. Accurate control of the sampling instant via the

and once-off conversion control.

8. ENOB > 10 bits typically with 500 mV reference.

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

CONTROL LOGIC

Figure 1.

CS

SCLK
SDATA
CS

input

03157-0-013

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

AD7457

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TABLE OF CONTENTS

Specifications..................................................................................... 3

Analog Input............................................................................... 12

Timing Specifications....................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Te r m in o l o g y .................................................................................... 10

Theory of Operation ...................................................................... 11

Circuit Information.................................................................... 11

Converter Operation.................................................................. 11

ADC Transfer Function............................................................. 11

Typical C o n necti on D i a g ram ................................................... 11

REVISION HISTORY

2/05—Rev. 0 to Rev. A

Changes to Table 3............................................................................ 6

Changes to Ordering Guide.......................................................... 17

Analog Input Structure.............................................................. 12

Digital Inputs .............................................................................. 13

Reference Section ....................................................................... 13

Serial Interface............................................................................ 13

Power Consumption .................................................................. 14

Microprocessor Interfacing....................................................... 14

Application Hints ........................................................................... 16

Grounding and Layout .............................................................. 16

Outline Dimensions....................................................................... 17

Ordering Guide .......................................................................... 17

10/03—Rev. 0: Initial Version

Rev. A | Page 2 of 20

AD7457

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SPECIFICATIONS

VDD = 2.7 V to 5.25 V, f

Table 1.

Parameter Test Conditions/Comments B Version

DYNAMIC PERFORMANCE fIN = 30 kHz

Signal to Noise Ratio (SNR)
Signal to (Noise + Distortion) (SINAD)2 70 dB min
Total Harmonic Distortion (THD)2 −84 dB typ −75 dB max
Peak Harmonic or Spurious Noise2 −86 dB typ −75 dB max
Intermodulation Distortion (IMD)2 fa = 25 kHz; fb = 35 kHz

Second-Order Terms −80 dB typ

Third-Order Terms −80 dB typ
Aperture Delay2 5 ns typ
Aperture Jitter2 50 ps typ
Full-Power Bandwidth

@ −0.1 dB 2.5 MHz typ
DC ACCURACY

Resolution 12 Bits
Integral Nonlinearity (INL)2 ±1 LSB max
Differential Nonlinearity (DNL)2 Guaranteed no missed codes to 12 bits ±0.95 LSB max
Offset Error2 ±4.5 LSB max
Gain Error2 ±2 LSB max

ANALOG INPUT

Full-Scale Input Span

Absolute Input Voltage
V

IN+

4

V

IN−

V
DC Leakage Current ±1 µA max
Input Capacitance When in track/hold 30/10 pF typ

REFERENCE INPUT

V

Input Voltage

REF

DC Leakage Current ±1 µA max
V

Input Capacitance When in track/hold 10/30 pF typ

REF

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

IN

Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, V
V
Output Low Voltage, V
Floating-State Leakage Current ±1 µA max
Floating-State Output Capacitance6 10 pF max
Output Coding Straight natural binary

CONVERSION RATE

Conversion Time 1.6 µs with a 10 MHz SCLK 16 SCLK cycles
Track-and-Hold Acquisition Time2 1 µs max
Throughput Rate See the Serial Interface section 100 kSPS max

= 10 MHz, fS = 100 kSPS, V

SCLK

2

2, 3

5

INH

INL

6

IN

OH

OL

= 2.5 V, TA = T

REF

MIN

to T

, unless otherwise noted.

MAX

1

Unit

71 dB min

@ −3 dB 20 MHz typ

V

− V

IN+

IN−

V

V

REF

REF

V

V

VDD = 2.7 V to 3.6 V −0.1 to +0.4 V

= 4.75 V to 5.25 V −0.1 to +1.5 V

DD

±1% tolerance for specified performance 2.5 V

2.4 V min

0.8 V max
Typically 10 nA, VIN = 0 V or V

DD

±1 µA max

10 pF max

VDD = 4.75 V to 5.25 V, I

= 2.7 V to 3.6 V, I

DD

I

= 200 µA 0.4 V max

SINK

= 200 µA 2.8 V min

SOURCE

= 200 µA 2.4 V min

SOURCE

Rev. A | Page 3 of 20

AD7457

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Parameter Test Conditions/Comments B Version

1

Unit

POWER REQUIREMENTS

V

DD

7, 8

I

DD

During Conversion

6

V

2.7/5.25 V min/max

VDD = 4.75 V to 5.25 V 1.5 mA max

= 2.7 V to 3.6 V 1.2 mA max

DD

Normal Mode (Static) SCLK on or off 0.5 mA typ
Normal Mode (Operational) VDD = 4.75 V to 5.25 V 0.7 mA max

V

= 2.7 V to 3.6 V 0.33 mA max

DD

Power-Down SCLK on or off 1 µA max
Power Dissipation

Normal Mode (Operational) VDD = 5 V 3 mW max
V

= 3 V 0.9 mW max

DD

Power-Down VDD = 5 V; SCLK on or off 5 µW max

V

= 3 V; SCLK on or off 3 µW max

DD

1

Temperature range for B version: −40°C to +85°C.

2

See the section. Terminology

3

Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by the

converter.

4

A dc input is applied to V

5

The AD7457 is functional with a reference input range of 100 mV to VDD.

6

Guaranteed by characterization.

7

See the section. Power Consumption

8

Measured with a full-scale dc input.

to provide a pseudo ground for V

IN–

.

IN+

Rev. A | Page 4 of 20

AD7457

A

www.BDTIC.com/ADI

TIMING SPECIFICATIONS

VDD = 2.7 V to 5.25 V, f

Table 2.

Parameter Limit at T

2

f

SCLK

10 MHz max
t

CONVERT

1.6 µs max
t2 10 ns min

3

t

3

3

t

4

t5 0.4 t
t6 0.4 t
t7 10 ns min SCLK edge to data valid hold time

4

t

8

35 ns max SCLK falling edge to SDATA three-state enabled

5

t

POWER-UP

t

POWER-DOWN

1

The timing specifications are guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of

1.6 V. See and the Serial section. Figure 2 Interface

2

Mark/space ratio for the SCLK input is 40/60 to 60/40.

3

Measured with the load circuit of and defined as the time required for the output to cross 0.8 V or 2.4 V with VFigure 3

cross 0.4 V or 2.0 V for VDD = 3 V.

4

t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of The measured number is then extrapolated

back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.

5

See the section. Power Consumption

= 10 MHz, fS = 100 kSPS, V

SCLK

, T

MIN

10 kHz min

16 × t

SCLK

20 ns max
40 ns max Data access time after SCLK falling edge

ns min SCLK high pulse width

SCLK

ns min SCLK low pulse width

SCLK

10 ns min SCLK falling edge to SDATA three-state enabled

1 µs max Power-up time from full power-down

7.4 µs min Minimum time spent in power-down

POWER

UP

CS

SCLK

SDAT

THREE-STATE

1

= 2.5 V, TA = T

REF

Unit Description

MAX

t

= 1/f

SCLK

CS

rising edge to SCLK falling edge setup time

Delay from CS rising edge until SDATA three-state disabled

CONVERT

START

TRACK TRACK

T

POWERUP

T

ACQUISITION

t

t

2

5

t

t

t

4

3

0 0 0 DB11 DB10 DB2 DB1 DB00

4 LEADING ZEROS

6

Figure 2. AD7457 Serial Interface Timing Diagram

SCLK

MIN

HOLD

t

7

to T

, unless otherwise noted.

MAX

DD

Figure 3.

AUTOMATIC

POWER DOWN

t

8

T

POWERDOWN

THREE-STATE

= 5 V, and the time required for the output to

T

POWERUP

T

ACQUISTION

03157-0-001

Rev. A | Page 5 of 20

AD7457

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND −0.3 V to +7 V
V

to GND −0.3 V to VDD + 0.3 V

IN+

V

to GND −0.3 V to VDD + 0.3 V

IN–

Digital Input Voltage to GND −0.3 V to +7 V
Digital Output Voltage to GND −0.3 V to VDD + 0.3 V
V

to GND −0.3 V to VDD + 0.3 V

REF

Input Current
Operating Temperature Range

to Any Pin Except

Supplies1±10 mA

Commercial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance 211.5°C/W (SOT-23)
θJC Thermal Impedance 91.99°C/W (SOT-23)
Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C
Pb-Free Temperature, Soldering

Reflow 260(+0)°C

1

Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Figure 3. Load Circuit for Digital Output Timing Specifications

OUTPUT

PIN

I

OL

1.6mA

TO

C

L

25pF

I

OH

200µA

1.6V

03157-0-012

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 6 of 20