ANALOG DEVICES AD7453 Service Manual

Pseudo Differential, 555 kSPS

V

V

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FEATURES

Specified for VDD of 2.7 V to 5.25 V
Low power at max throughput rate:

3.3 mW max at 555 kSPS with V

7.25 mW max at 555 kSPS with V
Pseudo differential analog input
Wide input bandwidth:
70 dB SINAD at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface:
SPI®/QSPI™/MICROWIRE™/DSP compatible
Power-down mode: 1 µA max
8-lead SOT-23 package

APPLICATIONS

Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation

GENERAL DESCRIPTION

The AD74531 is a 12-bit, high speed, low power, successive
approximation (SAR) analog-to-digital converter that features a
pseudo differential analog input. This part operates from a
single 2.7 V to 5.25 V power supply and features throughput
rates up to 555 kSPS.

The part contains a low noise, wide bandwidth, differential
track-and-hold amplifier (T/H) that can handle input frequen­cies up to 3.5 MHz. The reference voltage for the AD7453 is
applied externally to the V
V

, depending on the power supply and what suits the

DD

application.

The conversion process and data acquisition are controlled

CS

using

and the serial clock, allowing the device to interface
with microprocessors or DSPs. The input signals are sampled on
the falling edge of

CS

point.

The SAR architecture of this part ensures that there are no
pipeline delays. The AD7453 uses advanced design techniques
to achieve very low power dissipation.

pin and can range from 100 mV to

REF

; the conversion is also initiated at this

DD

DD

= 3 V

= 5 V

12-Bit ADC in an 8-Lead SOT-23

AD7453

FUNCTIONAL BLOCK DIAGRAM

DD

V

V

IN+

IN–

REF

T/H

AD7453

GND

PRODUCT HIGHLIGHTS

1. Operation with 2.7 V to 5.25 V Power Supplies.

2. High Throughput with Low Power Consumption. With a

3 V supply, the AD7453 offers 3.3 mW max power
consumption for a 555 kSPS throughput rate.

3. Pseudo Differential Analog Input.

4. Flexible Power/Serial Clock Speed Management. The

conversion rate is determined by the serial clock, allowing
the power to be reduced as the conversion time is reduced
through the serial clock speed increase. This part also
features a shutdown mode to maximize power efficiency at
lower throughput rates.

5. Variable Voltage Reference Input.

6. No Pipeline Delay.

7. Accurate control of the sampling instant via a

once-off conversion control.

8. ENOB > 10 bits Typically with 500 mV Reference.

1

Protected by U.S. Patent Number 6,681,332.

12-BIT

SUCCESSIVE

APPROXIMATION

CONTROL LOGIC

Figure 1.

ADC

SCLK
SDATA
CS

03155-A-001

CS

input and

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD7453

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TABLE OF CONTENTS

Specifications..................................................................................... 3

Reference ..................................................................................... 13

Timing Specifications .................................................................. 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Terminology ...................................................................................... 8

AD7453–Typical Performance Characteristics ............................ 9

Circuit Information........................................................................ 11

Converter Operation.................................................................. 11

ADC Transfer Function............................................................. 11

Typical Connection Diagram ................................................... 12

The Analog Input........................................................................ 12

Digital Inputs .............................................................................. 13

REVISION HISTORY

2/04—Data Sheet changed from Rev. A to Rev. B

Serial Interface............................................................................ 13

Modes of Operation ....................................................................... 15

Normal Mode.............................................................................. 15

Power-Down Mode.................................................................... 15

Power-Up Time .......................................................................... 16

Power vs. Throughput Rate....................................................... 17

Microprocessor and DSP Interfacing ...................................... 17

Application Hints ....................................................................... 19

Evaluating the AD7453’s Performance .................................... 19

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

Added Patent Note ....................................................................... 1

1/04—Data Sheet changed from Rev. 0 to Rev. A

Updated Format..............................................................Universal

Changes to General Description ................................................ 1

Changes to Specifications............................................................ 3

Changes to Timing Specifications.............................................. 5

Changes to Table 4........................................................................ 7

Replaced Figures 11, 12, 13........................................................ 10

Changes to Typical Connection Diagram section ................. 12

Change to Figure 18 ................................................................... 12

Changes to Reference Section................................................... 13

Changes to Timing Example 1.................................................. 14

8/03—Rev. 0: Initial Version

Rev. B | Page 2 of 20

AD7453

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SPECIFICATIONS

VDD = 2.7 V to 5.25 V, f

Table 1.

Parameter Test Conditions/Comments A Version1 B Version1 Unit

DYNAMIC PERFORMANCE fIN = 100 kHz

Signal to Noise Ratio (SNR)
Signal to (Noise + Distortion) (SINAD)2 VDD = 2.7 V to 3.6 V 69 69 dB min

V

Total Harmonic Distortion (THD)2 VDD = 2.7 V to 3.6 V; –78 dB typ –73 –73 dB max

V

Peak Harmonic or Spurious Noise2 V

V

Intermodulation Distortion (IMD)2 fa = 90 kHz; fb = 110 kHz

Second-Order Terms –80 –80 dB typ

Third-Order Terms –80 –80 dB typ
Aperture Delay2 5 5 ns typ
Aperture Jitter2 50 50 ps typ
Full-Power Bandwidth

@ –0.1 dB 2.5 2.5 MHz typ
DC ACCURACY

Resolution 12 12 Bits
Integral Nonlinearity (INL)2 ±1.5 ±1 LSB max
Differential Nonlinearity (DNL)2 Guaranteed no missed codes to 12 bits ±0.95 ±0.95 LSB max
Offset Error2 ±3.5 ±3.5 LSB max
Gain Error2 ±3 ±3 LSB max

ANALOG INPUT

Full-Scale Input Span V
Absolute Input Voltage

V

V

IN+

4

V

VDD = 2.7 V to 3.6 V –0.1 to +0.4 –0.1 to +0.4 V

IN–

V

DC Leakage Current ±1 ±1 µA max
Input Capacitance When in track/hold 30/10 30/10 pF typ

REFERENCE INPUT

V

Input Voltage ± 1% tolerance for specified performance 2.5 5 2.55 V

REF

DC Leakage Current ±1 ±1 µA max
V

Input Capacitance When in track/hold 10/30 10/30 pF typ

REF

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

IN

Input Capacitance, CIN

LOGIC OUTPUTS

Output High Voltage, V

V

Output Low Voltage, VOL I
Floating-State Leakage Current ±1 ±1 µA max
Floating-State Output Capacitance6 10 10 pF max
Output Coding Straight (natural) binary

= 10 MHz, fS = 555 kSPS, V

SCLK

2

2, 3

INH

INL

6

OH

= 2.5 V, FIN = 100 kHz, TA = T

REF

MIN

to T

, unless other wise noted

MAX

VDD = 2.7 V to 5.25 V 70 70 dB min

= 4.75 V to 5.25 V 70 70 dB min

DD

= 4.75 V to 5.25 V; –80 dB typ –75 –75 dB max

DD

= 2.7 V to 3.6 V; –80 dB typ –73 –73 dB max

DD

= 4.75 V to 5.25 V; –82 dB typ –75 –75 dB max

DD

@ –3 dB 20 20 MHz typ

– V

V

IN+

IN–

= 4.75 V to 5.25 V –0.1 to +1.5 –0.1 to +1.5 V

DD

V

REF

V

REF

V

REF

V

REF

2.4 2.4 V min

0.8 0.8 V max
Typically 10 nA, VIN = 0 V or VDD ±1 ±1 µA max
10 10 pF max

VDD = 4.75 V to 5.25 V, I

= 2.7 V to 3.6 V, I

DD

= 200 µA 0.4 0.4 V max

SINK

= 200 µA 2.8 2.8 V min

SOURCE

= 200 µA 2.4 2.4 V min

SOURCE

Rev. B | Page 3 of 20

AD7453

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Parameter Test Conditions/Comments A Version1 B Version1 Unit

CONVERSION RATE

Conversion Time 1.6 µs with a 10 MHz SCLK 16 16 SCLK cycles
Track-and-Hold Acquisition Time2 Sine wave input 250 250 ns max

Full-scale step input 290 290 ns max

Throughput Rate 555 555 kSPS max

POWER REQUIREMENTS

VDD 2.7/5.25 2.7/5.25 V min/max

7,

I

8

DD

Normal Mode (Static) SCLK on or off 0.5 0.5 mA typ
Normal Mode (Operational) VDD = 4.75 V to 5.25 V 1.5 1.5 mA max

V

Full Power-Down Mode SCLK on or off 1 1 µA max

Power Dissipation

Normal Mode (Operational) VDD = 5 V; 1.55 mW typ for 100 kSPS7 7.25 7.25 mW max

V

Full Power-Down Mode VDD = 5 V; SCLK on or off 5 5 µW max

V

1

Temperature ranges as follows: A, B versions: –40°C to +85°C.

2

See section. Terminology

3

Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by the

converter.

4

A small dc input is applied to V

5

The AD7453 is functional with a reference input in the range 100 mV to VDD.

6

Guaranteed by characterization.

7

See section. Power vs. Throughput Rate

8

Measured with a full-scale dc input.

to provide a pseudo ground for V

IN–

= 2.7 V to 3.6 V 1.2 1.2 mA max

DD

= 3 V; 0.64 mW typ for 100 kSPS7 3.3 3.3 mW max

DD

= 3 V; SCLK on or off 3 3 µW max

DD

.

IN+

Rev. B | Page 4 of 20

AD7453

A

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TIMING SPECIFICATIONS

Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage
level of 1.6 V.

See Figure 2 and the Serial Interface section.

= 2.7 V to 5.25 V, f

V

DD

= 10 MHz, fS = 555 kSPS, V

SCLK

= 2.5 V, TA = T

REF

MIN

to T

, unless otherwise noted.

MAX

Table 2.

Parameter Limit at T

1

f

10 kHz min

SCLK

MIN

, T

Unit Description

MAX

10 MHz max
t

CONVERT

16 × t

t

SCLK

SCLK

= 1/f

SCLK

1.6 µs max
t

60 ns min

QUIET

t1 10 ns min
t2 10 ns min

2

t

20 ns max

3

2

t

40 ns max Data access time after SCLK falling edge

4

t5 0.4 t
t6 0.4 t

ns min SCLK high pulse width

SCLK

ns min SCLK low pulse width

SCLK

Minimum quiet time between the end of a serial read and the next falling edge of

CS

Minimum
CS

falling edge to SCLK falling edge setup time

Delay from

pulse width

CS

falling edge until SDATA three-state disabled

t7 10 ns min SCLK edge to data valid hold time

3

t

10 ns min SCLK falling edge to SDATA three-state enabled

8

35 ns max SCLK falling edge to SDATA three-state enabled
t

4 1 µs max Power-up time from full power-down

POWER-UP

SCLK

SDAT

CS

t

2

12345 13141516

t

3

0 0 0 0 DB11 DB10 DB2 DB1 DB0

4 LEADING ZEROS THREE-STATE

t

4

Figure 2. AD7453 Serial Interface Timing Diagram

t

CONVERT

t

5

t

7

B

t

6

t

CS

t

1

8

t

QUIET

03155-A-002

1

Mark/space ratio for the SCLK input is 40/60 to 60/40.

2

Measured with the load circuit of and defined as the time required for the output to cross 0.8 V or 2.4 V with VFigure 3

cross 0.4 V or 2.0 V for V

3

t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of The measured number is then extrapolated

back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.

4

See Power-Up Time section.

= 3 V.

DD

Figure 3.

, quoted in the timing characteristics is the true bus relinquish

8

Rev. B | Page 5 of 20

= 5 V, and the time required for an output to

DD

AD7453

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND –0.3 V to +7 V
V

to GND –0.3 V to VDD + 0.3 V

IN+

V

to GND –0.3 V to VDD + 0.3 V

IN–

Digital Input Voltage to GND –0.3 V to +7 V
Digital Output Voltage to GND –0.3 V to VDD + 0.3 V
V

to GND –0.3 V to VDD + 0.3 V

REF

Input Current to Any Pin Except Supplies1±10 mA
Operating Temperature Range

Commercial (A, B Version) –40°C to +85°C
Storage Temperature Range –65°C to +85°C
Junction Temperature 150°C
θJA Thermal Impedance 211.5°C/W (SOT-23)
θJC Thermal Impedance 91.99°C/W (SOT-23)
Lead Temperature, Soldering

Vapor Phase (60 secs) 215°C

Infrared (15 secs) 220°C
ESD 1 kV

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Figure 3. Load Circuit for Digital Output Timing Specifications

TO OUTPUT

PIN

25pF

C

L

1.6mA I

200µAI

OL

OH

1.6V

03155-A-003

1

Transient currents of up to 100 mA will not cause SCR latch-up.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. B | Page 6 of 20