Pseudo Differential, 555 kSPS
V
V
FEATURES
Specified for VDD of 2.7 V to 5.25 V
Low power at max throughput rate:
3.3 mW max at 555 kSPS with V
7.25 mW max at 555 kSPS with V
Pseudo differential analog input
Wide input bandwidth:
70 dB SINAD at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface:
SPI®/QSPI™/MICROWIRE™/DSP compatible
Power-down mode: 1 µA max
8-lead SOT-23 package
APPLICATIONS
Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation
GENERAL DESCRIPTION
The AD74531 is a 12-bit, high speed, low power, successive
approximation (SAR) analog-to-digital converter that features a
pseudo differential analog input. This part operates from a
single 2.7 V to 5.25 V power supply and features throughput
rates up to 555 kSPS.
The part contains a low noise, wide bandwidth, differential
track-and-hold amplifier (T/H) that can handle input frequencies up to 3.5 MHz. The reference voltage for the AD7453 is
applied externally to the V
, depending on the power supply and what suits the
V
DD
application.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the device to interface
with microprocessors or DSPs. The input signals are sampled on
the falling edge of
CS
point.
The SAR architecture of this part ensures that there are no
pipeline delays. The AD7453 uses advanced design techniques
to achieve very low power dissipation.
pin and can range from 100 mV to
REF
; the conversion is also initiated at this
DD
DD
= 3 V
= 5 V
12-Bit ADC in an 8-Lead SOT-23
AD7453
FUNCTIONAL BLOCK DIAGRAM
DD
V
V
IN+
IN–
REF
T/H
AD7453
GND
PRODUCT HIGHLIGHTS
1. Operation with 2.7 V to 5.25 V Power Supplies.
2. High Throughput with Low Power Consumption. With a
3 V supply, the AD7453 offers 3.3 mW max power
consumption for a 555 kSPS throughput rate.
3. Pseudo Differential Analog Input.
4. Flexible Power/Serial Clock Speed Management. The
conversion rate is determined by the serial clock, allowing
the power to be reduced as the conversion time is reduced
through the serial clock speed increase. This part also
features a shutdown mode to maximize power efficiency at
lower throughput rates.
5. Variable Voltage Reference Input.
6. No Pipeline Delay.
7. Accurate control of the sampling instant via a
once-off conversion control.
8. ENOB > 10 bits Typically with 500 mV Reference.
1
Protected by U.S. Patent Number 6,681,332.
12-BIT
SUCCESSIVE
APPROXIMATION
CONTROL LOGIC
Figure 1.
ADC
SCLK
SDATA
CS
03155-A-001
CS
input and
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
www.analog.com
AD7453
TABLE OF CONTENTS
Specifications..................................................................................... 3
Reference ..................................................................................... 13
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Terminology ...................................................................................... 8
AD7453–Typical Performance Characteristics ............................ 9
Circuit Information........................................................................ 11
Converter Operation.................................................................. 11
ADC Transfer Function............................................................. 11
Typical Connection Diagram ................................................... 12
The Analog Input........................................................................ 12
Digital Inputs .............................................................................. 13
REVISION HISTORY
2/04—Data Sheet changed from Rev. A to Rev. B
Serial Interface............................................................................ 13
Modes of Operation ....................................................................... 15
Normal Mode.............................................................................. 15
Power-Down Mode.................................................................... 15
Power-Up Time .......................................................................... 16
Power vs. Throughput Rate....................................................... 17
Microprocessor and DSP Interfacing ...................................... 17
Application Hints ....................................................................... 19
Evaluating the AD7453’s Performance.................................... 19
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 20
Added Patent Note ....................................................................... 1
1/04—Data Sheet changed from Rev. 0 to Rev. A
Updated Format..............................................................Universal
Changes to General Description ................................................ 1
Changes to Specifications............................................................ 3
Changes to Timing Specifications.............................................. 5
Changes to Table 4........................................................................ 7
Replaced Figures 11, 12, 13........................................................ 10
Changes to Typical Connection Diagram section ................. 12
Change to Figure 18 ................................................................... 12
Changes to Reference Section................................................... 13
Changes to Timing Example 1.................................................. 14
8/03—Rev. 0: Initial Version
Rev. B | Page 2 of 20
AD7453
SPECIFICATIONS
VDD = 2.7 V to 5.25 V, f
Table 1.
Parameter Test Conditions/Comments A Version1 B Version1 Unit
DYNAMIC PERFORMANCE fIN = 100 kHz
Signal to Noise Ratio (SNR)
Signal to (Noise + Distortion) (SINAD)2 VDD = 2.7 V to 3.6 V 69 69 dB min
V
Total Harmonic Distortion (THD)2 VDD = 2.7 V to 3.6 V; –78 dB typ –73 –73 dB max
V
Peak Harmonic or Spurious Noise2 V
V
Intermodulation Distortion (IMD)2 fa = 90 kHz; fb = 110 kHz
Second-Order Terms –80 –80 dB typ
Third-Order Terms –80 –80 dB typ
Aperture Delay2 5 5 ns typ
Aperture Jitter2 50 50 ps typ
Full-Power Bandwidth
@ –0.1 dB 2.5 2.5 MHz typ
DC ACCURACY
Resolution 12 12 Bits
Integral Nonlinearity (INL)2 ±1.5 ±1 LSB max
Differential Nonlinearity (DNL)2 Guaranteed no missed codes to 12 bits ±0.95 ±0.95 LSB max
Offset Error2 ±3.5 ±3.5 LSB max
Gain Error2 ±3 ±3 LSB max
ANALOG INPUT
Full-Scale Input Span V
Absolute Input Voltage
V
V
IN+
4
V
VDD = 2.7 V to 3.6 V –0.1 to +0.4 –0.1 to +0.4 V
IN–
V
DC Leakage Current ±1 ±1 µA max
Input Capacitance When in track/hold 30/10 30/10 pF typ
REFERENCE INPUT
V
Input Voltage ± 1% tolerance for specified performance 2.5 5 2.55 V
REF
DC Leakage Current ±1 ±1 µA max
V
Input Capacitance When in track/hold 10/30 10/30 pF typ
REF
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
IN
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, V
V
Output Low Voltage, VOL I
Floating-State Leakage Current ±1 ±1 µA max
Floating-State Output Capacitance6 10 10 pF max
Output Coding Straight (natural) binary
= 10 MHz, fS = 555 kSPS, V
SCLK
2
2, 3
INH
INL
6
OH
= 2.5 V, FIN = 100 kHz, TA = T
REF
MIN
to T
, unless other wise noted
MAX
VDD = 2.7 V to 5.25 V 70 70 dB min
= 4.75 V to 5.25 V 70 70 dB min
DD
= 4.75 V to 5.25 V; –80 dB typ –75 –75 dB max
DD
= 2.7 V to 3.6 V; –80 dB typ –73 –73 dB max
DD
= 4.75 V to 5.25 V; –82 dB typ –75 –75 dB max
DD
@ –3 dB 20 20 MHz typ
– V
V
IN+
IN–
= 4.75 V to 5.25 V –0.1 to +1.5 –0.1 to +1.5 V
DD
V
REF
V
REF
V
REF
V
REF
2.4 2.4 V min
0.8 0.8 V max
Typically 10 nA, VIN = 0 V or VDD ±1 ±1 µA max
10 10 pF max
VDD = 4.75 V to 5.25 V, I
= 2.7 V to 3.6 V, I
DD
= 200 µA 0.4 0.4 V max
SINK
= 200 µA 2.8 2.8 V min
SOURCE
= 200 µA 2.4 2.4 V min
SOURCE
Rev. B | Page 3 of 20
AD7453
Parameter Test Conditions/Comments A Version1 B Version1 Unit
CONVERSION RATE
Conversion Time 1.6 µs with a 10 MHz SCLK 16 16 SCLK cycles
Track-and-Hold Acquisition Time2 Sine wave input 250 250 ns max
Full-scale step input 290 290 ns max
Throughput Rate 555 555 kSPS max
POWER REQUIREMENTS
VDD 2.7/5.25 2.7/5.25 V min/max
7, 8
I
DD
Normal Mode (Static) SCLK on or off 0.5 0.5 mA typ
Normal Mode (Operational) VDD = 4.75 V to 5.25 V 1.5 1.5 mA max
V
Full Power-Down Mode SCLK on or off 1 1 µA max
Power Dissipation
Normal Mode (Operational) VDD = 5 V; 1.55 mW typ for 100 kSPS7 7.25 7.25 mW max
V
Full Power-Down Mode VDD = 5 V; SCLK on or off 5 5 µW max
V
1
Temperature ranges as follows: A, B versions: –40°C to +85°C.
2
See section. Terminology
3
Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by the
converter.
4
A small dc input is applied to V
5
The AD7453 is functional with a reference input in the range 100 mV to VDD.
6
Guaranteed by characterization.
7
See section. Power vs. Throughput Rate
8
Measured with a full-scale dc input.
to provide a pseudo ground for V
IN–
= 2.7 V to 3.6 V 1.2 1.2 mA max
DD
= 3 V; 0.64 mW typ for 100 kSPS7 3.3 3.3 mW max
DD
= 3 V; SCLK on or off 3 3 µW max
DD
.
IN+
Rev. B | Page 4 of 20
AD7453
A
TIMING SPECIFICATIONS
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage
level of 1.6 V.
See Figure 2 and the Serial Interface section.
V
= 2.7 V to 5.25 V, f
DD
Table 2.
Parameter Limit at T
1
f
10 kHz min
SCLK
10 MHz max
t
16 × t
CONVERT
1.6 µs max
t
60 ns min
QUIET
t1 10 ns min
t2 10 ns min
2
t
20 ns max
3
2
t
40 ns max Data access time after SCLK falling edge
4
t5 0.4 t
t6 0.4 t
t7 10 ns min SCLK edge to data valid hold time
3
t
10 ns min SCLK falling edge to SDATA three-state enabled
8
35 ns max SCLK falling edge to SDATA three-state enabled
t
4 1 µs max Power-up time from full power-down
POWER-UP
= 10 MHz, fS = 555 kSPS, V
SCLK
, T
MIN
t
SCLK
Unit Description
MAX
= 2.5 V, TA = T
REF
= 1/f
SCLK
SCLK
Minimum quiet time between the end of a serial read and the next falling edge of
CS
Minimum
CS
falling edge to SCLK falling edge setup time
Delay from
ns min SCLK high pulse width
SCLK
ns min SCLK low pulse width
SCLK
pulse width
CS
falling edge until SDATA three-state disabled
to T
MIN
, unless otherwise noted.
MAX
CS
t
1
SCLK
SDAT
CS
t
2
12345 13141516
t
3
0 0 0 0 DB11 DB10 DB2 DB1 DB0
4 LEADING ZEROS THREE-STATE
t
4
t
CONVERT
t
5
t
7
B
t
6
t
8
t
QUIET
03155-A-002
Figure 2. AD7453 Serial Interface Timing Diagram
1
Mark/space ratio for the SCLK input is 40/60 to 60/40.
2
Measured with the load circuit of and defined as the time required for the output to cross 0.8 V or 2.4 V with VFigure 3
cross 0.4 V or 2.0 V for V
3
t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.
4
See Power-Up Time section.
= 3 V.
DD
= 5 V, and the time required for an output to
DD
Figure 3.
, quoted in the timing characteristics is the true bus relinquish
8
Rev. B | Page 5 of 20
AD7453
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VDD to GND –0.3 V to +7 V
V
to GND –0.3 V to VDD + 0.3 V
IN+
V
to GND –0.3 V to VDD + 0.3 V
IN–
Digital Input Voltage to GND –0.3 V to +7 V
Digital Output Voltage to GND –0.3 V to VDD + 0.3 V
V
to GND –0.3 V to VDD + 0.3 V
REF
Input Current to Any Pin Except Supplies1±10 mA
Operating Temperature Range
Commercial (A, B Version) –40°C to +85°C
Storage Temperature Range –65°C to +85°C
Junction Temperature 150°C
θJA Thermal Impedance 211.5°C/W (SOT-23)
θJC Thermal Impedance 91.99°C/W (SOT-23)
Lead Temperature, Soldering
Vapor Phase (60 secs) 215°C
Infrared (15 secs) 220°C
ESD 1 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Figure 3. Load Circuit for Digital Output Timing Specifications
TO OUTPUT
PIN
25pF
C
L
1.6mA I
200µAI
OL
OH
1.6V
03155-A-003
1
Transient currents of up to 100 mA will not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 6 of 20
AD7453
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Mnemonic Function
V
REF
Reference Input for the AD7453. An external reference in the range 100 mV to VDD must be applied to this input. The specified
reference input is 2.5 V. This pin should be decoupled to GND with a capacitor of at least 0.1 µF.
V
IN+
V
IN–
Noninverting Analog Input.
Inverting Input. This pin sets the ground reference point for the V
pseudo ground.
GND
Analog Ground. Ground reference point for all circuitry on the AD7453. All analog input signals and any external reference
signal should be referred to this GND voltage.
CS
Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on the AD7453 and
framing the serial data transfer.
SDATA
Serial Data. Logic output. The conversion result from the AD7453 is provided on this output as a serial data stream. The bits
are clocked out on the falling edge of the SCLK input. The data stream of the AD7453 consists of four leading zeros followed
by the 12 bits of conversion data that are provided MSB first. The output coding is straight (natural) binary.
SCLK
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the
clock source for the conversion process.
V
DD
Power Supply Input. VDD is 2.7 V to 5.25 V. This supply should be decoupled to GND with a 0.1 µF capacitor and a 10 µF
tantalum capacitor.
V
SCLK
SDATA
CS
DD
1
2
AD7453
TOP VIEW
3
(Not to Scale)
4
V
8
REF
7
V
IN+
6
V
IN–
GND
5
Figure 4. Pin Function Descriptions
input. Connect to ground or to a dc offset to provide a
IN+
03155-A-004
Rev. B | Page 7 of 20
AD7453
V
TERMINOLOGY
Signal-to-(Noise + Distortion) Ratio
The measured ratio of signal to (noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to
half the sampling frequency (f
dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise.
The theoretical signal-to-(noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by
Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB
Thus, for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion (THD)
Total harmonic distortion is the ratio of the rms sum of
harmonics to the fundamental. For the AD7453, it is defined as
THD
where V
V
is the rms amplitude of the fundamental and V2, V3,
1
, V5, and V6 are the rms amplitudes of the second to the sixth
4
= log20)dB(
harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
/2 and excluding dc) to the rms value of the
S
fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs
where the harmonics are buried in the noise floor, it is a noise
peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at the sum and difference frequencies of mfa ± nfb
where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion
terms are those for which neither m nor n are equal to zero. For
example, the second-order terms include (fa + fb) and (fa − fb),
while the third-order terms include (2fa + fb), (2fa − fb),
(fa + 2fb), and (fa − 2fb).
The AD7453 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second-order terms are usually distanced in
frequency from the original sine waves while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
/2), excluding dc. The ratio is
S
2
2
2
2
2
2
4
3
1
6
5
VVVVV
++++
as per the THD specification where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in dB.
Aperture Delay
The amount of time from the leading edge of the sampling
clock until the ADC actually takes the sample.
Aperture Jitter
The sample-to-sample variation in the effective point in time at
which the actual sample is taken.
Full Power Bandwidth
The full power bandwidth of an ADC is the input frequency at
which the amplitude of the reconstructed fundamental is
reduced by 0.1 dB or 3 dB for a full-scale input.
Integral Nonlinearity (INL)
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL)
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
The deviation of the first code transition (000...000 to 000...001)
from the ideal (i.e., AGND + 1 LSB)
Gain Error
This is the deviation of the last code transition (111...110 to
111...111) from the ideal (i.e., VREF – 1 LSB), after the offset
error has been adjusted out.
Track-and-Hold Acquisition Time
The minimum time required for the track and hold amplifier to
remain in track mode for its output to reach and settle to within
0.5 LSB of the applied input signal.
Power Supply Rejection Ratio (PSRR)
The ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the
ADC V
supply of frequency fS. The frequency of this input
DD
varies from 1 kHz to 1 MHz.
PSRR(dB) = 10log(Pf/Pf
)
S
Pf is the power at frequency f in the ADC output; Pfs is the
power at frequency f
in the ADC output.
S
Rev. B | Page 8 of 20
AD7453
AD7453–TYPICAL PERFORMANCE CHARACTERISTICS
Default Conditions: TA = 25°C, fS = 555 kSPS, f
75
70
65
SINAD (dB)
60
55
10
VDD = 4.75V
VDD = 3.6V
VDD = 2.7V
FREQUENCY (kHz)
= 10 MHz, VDD = 2.7 V to 5.25 V, V
SCLK
VDD = 5.25V
100 277
= 2.5 V, unless otherwise noted.
REF
1.0
0.8
0.6
0.4
0.2
0
–0.2
DNL ERROR (LS B)
–0.4
–0.6
–0.8
03155-A-005
–1.0
0 1024 30722048 4096
CODE
03155-A-008
Figure 5. SINAD vs. Analog Input Frequency for Various Supply Voltages
0
100mV p-p SINE WAVE ON V
NO DECOUPLING ON V
–20
–40
–60
–80
PSRR (dB)
–100
–120
–140
0 100 200 300 400 500
SUPPLY RIPPLE FREQUENCY (kHz)
DD
VDD= 3V
DD
VDD= 5V
600 700 800
03155-A-006
900 1000
Figure 6. PSRR vs. Supply Ripple Frequency without Supply Decoupling
0
–20
–40
–60
–80
SNR (dB)
–100
–120
–140
0 100 200
FREQUENCY (kHz)
Figure 7. Dynamic Performance for V
8192 POINT FFT
f
= 555kSPS
SAMPLE
f
= 100kSPS
IN
SINAD = 71.7dB
THD = –82dB
SFDR = –83dB
= 5 V
DD
03155-A-007
277
Figure 8. Typical DNL for the AD7453 for V
DD
= 5 V
1.0
0.8
0.6
0.4
0.2
0
–0.2
INL ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
0 1024 30722048 4096
Figure 9. Typical INL for the AD7453 for V
CODE
DD
= 5 V
03155-A-009
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
2046 2047 2048 2049 2050 2051
27 CODES 24 CODES
9949
CODES
CODES
03155-A-010
Figure 10. Histogram of 10,000 Conversions of a DC Input
Rev. B | Page 9 of 20
AD7453
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
CHANGE IN DNL (LSB)
0
–0.5
–1.0
012345
12
11
10
POSITIVE DNL
EFFECTIVE NUMBER OF BITS
NEGATIVE DNL
V
(V)
REF
03155-A-011
VDD = 3V
9
8
7
VDD = 5V
6
21304
(V)
V
REF
03155-A-013
5
Figure 11. Change in DNL vs. V
5
4
3
2
1
CHANGE IN INL (LSB)
0
–1
–2
012345
V
REF
Figure 12. Change in INL vs. V
REF
POSITIVE INL
NEGATIVE INL
(V)
REF
for VDD = 5 V
for VDD = 5 V
Figure 13. ENOB vs. V
for VDD = 3 V and 5 V
REF
03155-A-012
Rev. B | Page 10 of 20
AD7453
V
V
V
V
CIRCUIT INFORMATION
The AD7453 is a 12-bit, low power, single-supply, successive
approximation analog-to-digital converter (ADC) with a
pseudo differential analog input. It operates with a single 2.7 V
to 5.25 V power supply and is capable of throughput rates up to
555 kSPS when supplied with a 10 MHz SCLK. It requires an
external reference to be applied to the V
REF
pin.
The AD7453 has an on-chip differential track-and-hold
amplifier, a successive approximation (SAR) ADC, and a serial
interface, housed in an 8-lead SOT-23 package. The serial clock
input accesses data from the part and provides the clock source
for the successive approximation ADC. The AD7453 features a
power-down option for reduced power consumption between
conversions. The power-down feature is implemented across the
standard serial interface, as described in the Modes of
Operation section.
CONVERTER OPERATION
The AD7453 is a successive approximation ADC based around
two capacitive DACs. Figure 14 and Figure 15 show simplified
schematics of the ADC in the acquisition and conversion phase,
respectively. The ADC is comprised of control logic, an SAR,
and two capacitive DACs. In Figure 14 (acquisition phase), SW3
is closed and SW1 and SW2 are in Position A, the comparator is
held in a balanced condition, and the sampling capacitor arrays
acquire the differential signal on the input.
CAPACITIVE
DAC
B
IN+
A
A
IN–
B
C
S
SW1
SW2
C
S
V
REF
SW3
COMPARATOR
Figure 14. ADC Acquisition Phase
CONTROL
LOGIC
CAPACITIVE
DAC
03155-A-014
When the ADC starts a conversion (Figure 15), SW3 opens and
SW1 and SW2 move to Position B, causing the comparator to
become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates
the ADC’s output code. The output impedances of the sources
driving the V
IN+
and V
pins must be matched; otherwise the
IN–
two inputs have different settling times, resulting in errors.
CAPACITIVE
DAC
B
IN+
A
A
IN–
B
C
S
SW1
SW2
C
S
V
REF
SW3
COMPARATOR
CONTROL
LOGIC
CAPACITIVE
DAC
03155-A-015
Figure 15. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding for the AD7453 is straight (natural) binary.
The designed code transitions occur at successive LSB values
REF
REF
– 1LSB
/4096. The
03155-A-016
(i.e., 1 LSB, 2 LSB, and so on). The LSB size is V
ideal transfer characteristic of the AD7453 is shown in
Figure 16.
1LSB = V
111...11
111...10
111...00
011...11
ADC CODE
000...10
000...01
000...00
1LSB
0V
Figure 16. Ideal Transfer Characteristic
/4096
REF
ANALOG INPUT
V
Rev. B | Page 11 of 20
AD7453
V
V
TYPICAL CONNECTION DIAGRAM
Figure 17 shows a typical connection diagram for the AD7453.
In this setup, the GND pin is connected to the analog ground
plane of the system. The V
pin is connected to the AD780, a
REF
2.5 V decoupled reference source. The signal source is connected to the V
is connected to the V
input. The VDD pin should be decoupled to AGND with a
V
IN+
analog input via a unity gain buffer. A dc voltage
IN+
pin to provide a pseudo ground for the
IN–
10 µF tantalum capacitor in parallel with a 0.1 µF ceramic
capacitor. The reference pin should be decoupled to AGND with
a capacitor of at least 0.1 µF. The conversion result is output in a
16-bit word with four leading zeros followed by the MSB of the
12-bit result.
+2.7V TO +5.25V
SUPPLY
2.5V
AD780
SCLK
SDATA
CS
GND
10µF
SERIAL
INTERFACE
µC/µP
V
REF
P-TO-P
0.1µF
V
DD
AD7453
V
IN+
V
0.1µF
IN–
V
REF
DC INPUT
VOLTAGE
Figure 17. Typical Connection Diagram
THE ANALOG INPUT
The AD7453 has a pseudo differential analog input. The V
input is coupled to the signal source and must have an amplitude of V
part. A dc input is applied to V
p-p to make use of the full dynamic range of the
REF
. The voltage applied to this
IN–
input provides an offset from ground or a pseudo ground for
input. The main benefit of pseudo differential inputs
the V
IN+
is that they separate the analog input signal ground from the
ADC’s ground, allowing dc common-mode voltages to be
cancelled.
IN+
03155-A-017
2.5V
1.25V
0V
V
IN+
AD7453
V
IN–
V
REF
03155-A-018
+1.25V
–1.25V
R
R
0V
V
IN
3R
R
0.1µF
EXTERNAL
V
(2.5V)
REF
Figure 18. Op Amp Configuration to Level Shift a Bipolar Input Signal
Analog Input Structure
Figure 19 shows the equivalent circuit of the analog input structure of the AD7453. The four diodes provide ESD protection for
the analog inputs. Care must be taken to ensure that the analog
input signals never exceed the supply rails by more than
300 mV. This causes these diodes to become forward biased and
to start conducting into the substrate. These diodes can conduct
up to 10 mA without causing irreversible damage to the part.
The capacitors, C1 in Figure 19, are typically 4 pF and can be
attributed primarily to pin capacitance. The resistors are
lumped components made up of the on resistance of the
switches. The value of these resistors is typically about 100 Ω.
The capacitors C2 are the ADC’s sampling capacitors, and have
a typical capacitance of 16 pF.
For ac applications, removing high frequency components from
the analog input signal through the use of an RC low-pass filter
on the relevant analog input pins is recommended. In applications where harmonic distortion and signal-to-noise ratio are
critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac
performance of the ADC, which may necessitate the use of an
input buffer amplifier. The choice of the op amp is a function of
the particular application.
V
DD
Because the ADC operates from a single supply, it is necessary
to level shift ground-based bipolar signals to comply with the
input requirements. An op amp (for example, the AD8021) can
IN+
C1
D
D
C2
R1
be configured to rescale and level shift a ground-based (bipolar)
signal so that it is compatible with the input range of the
AD7453. See Figure 18.
V
DD
When a conversion takes place, the pseudo ground corresponds
to 0 and the maximum analog input corresponds to 4096.
IN–
C1
Conversion Phase—Switches Open; Track Phase—Switches Closed
Rev. B | Page 12 of 20
Figure 19. Equivalent Analog Input Circuit.
D
D
C2
R1
03155-A-019
AD7453
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance depends on the amount of total harmonic
distortion (THD) that can be tolerated. The THD increases as
the source impedance increases and performance degrades.
Figure 20 shows a graph of the THD versus analog input signal
frequency for different source impedances.
0
–10
–20
–30
–40
–50
THD (dB)
–60
–70
–80
–90
–100
100Ω
10
INPUT FREQUENCY (kHz)
200Ω
10Ω
62Ω
100 277
03155-A-020
Figure 20. THD vs. Analog Input Frequency for Various Source Impedances
Figure 21 shows a graph of THD versus analog input frequency
for various supply voltages while sampling at 555 kSPS with an
SCLK of 10 MHz. In this case, the source impedance is 10 Ω.
–50
TA = 25°C
–55
–60
–65
–70
THD (dBs)
–75
–80
–85
–90
10
VDD = 4.75V
INPUT FREQUENCY (kHz)
VDD = 2.7V
VDD = 3.6V
VDD = 5.25V
100 277
03155-A-021
Figure 21. THD vs. Analog Input Frequency for Various Supply Voltages
DIGITAL INPUTS
The digital inputs applied to the AD7453 are not limited by the
maximum ratings that limit the analog inputs. Instead, the
CS
digital inputs applied, i.e.,
not restricted by the V
The main advantage of the inputs not being restricted to the
+ 0.3 V limit is that power supply sequencing issues are
V
DD
avoided. If
CS
or SCLK are applied before VDD, there is no risk
of latch-up as there would be on the analog inputs if a signal
greater than 0.3 V were applied prior to V
and SCLK, can go to 7 V and are
+ 0.3 V limits as on the analog input.
DD
.
DD
REFERENCE
An external source is required to supply the reference to the
AD7453. This reference input can range from 100 mV to V
DD
.
The specified reference is 2.5 V for the 2.7 V to 5.25 V power
supply range. The reference input chosen for an application
should never be greater than the power supply. Errors in the
reference source result in gain errors in the AD7453 transfer
function. A capacitor of at least 0.1 µF should be placed on the
pin. Suitable reference sources for the AD7453 include the
V
REF
AD780 and the ADR421. Figure 22 shows a typical connection
diagram for the V
V
DD
10nF 0.1µF 0.1µF0.1µF
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 22. Typical V
REF
pin.
AD780
1
NC
2
V
IN
3
TEMP
4
GND
NC = NO CONNECT
Connection Diagram for VDD = 5 V
REF
OPSEL
V
OUT
TRIM
8
7
6
5
2.5V
NC
NC
NC
AD7453*
V
DD
V
REF
SERIAL INTERFACE
Figure 2 shows a detailed timing diagram of the serial interface
of the AD7453. The serial clock provides the conversion clock
and controls the transfer of data from the device during
conversion.
data transfer. The falling edge of
into hold mode and takes the bus out of three-state. The analog
input is sampled and the conversion is initiated at this point.
The conversion requires 16 SCLK cycles to complete.
Once 13 SCLK falling edges have occurred, the track-and-hold
goes back into track mode on the next SCLK rising edge, as
shown at Point B in Figure 2. On the 16th SCLK falling edge, the
SDATA line goes back into three-state.
If the rising edge of
the conversion is terminated and the SDATA line goes back into
three-state.
The conversion result from the AD7453 is provided on the
SDATA output as a serial data stream. The bits are clocked out
on the falling edge of the SCLK input. The data stream of the
AD7453 consists of four leading zeros, followed by 12 bits of
conversion data, provided MSB first. The output coding is
straight (natural) binary.
CS
initiates the conversion process and frames the
CS
puts the track-and-hold
CS
occurs before 16 SCLKs have elapsed,
03155-A-022
Rev. B | Page 13 of 20
AD7453
Sixteen serial clock cycles are required to perform a conversion
CS
and to access data from the AD7453.
first leading zero to be read in by the microcontroller or DSP.
The remaining data is then clocked out on the subsequent
SCLK falling edges, beginning with the second leading zero.
Thus the first falling clock edge on the serial clock provides the
second leading zero. The final bit in the data transfer is valid on
th
falling edge, having been clocked out on the previous
the 16
(15th) falling edge. Once the conversion is complete and the data
has been accessed after the 16 clock cycles, it is important to
ensure that, before the next conversion is initiated, enough time
is left to meet the acquisition and quiet time specifications. See
Timing Example 1.
going low provides the
Timing Example 1
Having F
= 10 MHz and a throughput rate of 555 kSPS gives
SCLK
a cycle time of
1/Throughput = 1/555,000 = 1.8 µs
A cycle consists of
t2 + 12.5(1/F
Therefore if t
= 10 ns,
2
10 ns + 12.5(1/10 MHz) + t
SCLK
t
ACQ
) + t
ACQ
= 540 ns
= 1.8 µs
= 1.8 µs
ACQ
In applications with a slower SCLK, it may be possible to read in
data on each SCLK rising edge, i.e., the first rising edge of SCLK
CS
after the
and the 15
falling edge would have the leading zero provided,
th
SCLK edge would have DB0 provided.
CS
10ns
SCLK
t
2
12345 13141516
t
12.5(1/F
SCLK
Figure 23. Serial Interface Timing Example
5
)
t
CONVERT
1/THROUGHPUT
This 540 ns satisfies the requirement of 290 ns for t
Figure 23, t
comprises
ACQ
2.5(1/F
SCLK
) + t8 + t
QUIET
where t8 = 35 ns. This allows a value of 255 ns for t
satisfying the minimum requirement of 60 ns.
t
6
t
8
t
ACQUISITION
t
QUIET
03155-A-023
ACQ
QUIET
. From
,
Rev. B | Page 14 of 20
AD7453
MODES OF OPERATION
The mode of operation of the AD7453 is selected by controlling
CS
the logic state of the
signal during a conversion. There are
two possible modes of operation, normal mode and powerdown mode. The point at which
CS
is pulled high after the
conversion has been initiated determines whether the AD7453
enters power-down mode. Similarly, if already in power-down,
CS
controls whether the device returns to normal operation or
remains in power-down. These modes of operation are designed
to provide flexible power management options. These options
can be chosen to optimize the power dissipation/ throughput
rate ratio for differing application requirements.
NORMAL MODE
This mode is intended for fastest throughput rate performance.
The user does not have to worry about any power-up times with
the AD7453 remaining fully powered up all the time. Figure 24
shows the general diagram of the operation of the AD7453 in
this mode. The conversion is initiated on the falling edge of
as described in the Serial Interface section. To ensure that the
part remains fully powered up,
CS
must remain low until at
least 10 SCLK falling edges have elapsed after the falling edge
CS
of
.
CS
,
POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required—the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate and the ADC is then
powered down for a relatively long duration between these
bursts of several conversions. When the AD7453 is in powerdown mode, all analog circuitry is powered down. For the
AD7453 to enter power-down mode, the conversion process
CS
must be interrupted by bringing
second falling edge of SCLK and before the 10
SCLK, as shown in Figure 25.
CS
Once
has been brought high in this window of SCLKs, the
part enters power-down, the conversion that was initiated by
the falling edge of
CS
is terminated, and SDATA goes back into
three-state. The time from the rising edge of
three-state enabled is never greater than t
Specifications). If
CS
is brought high before the second SCLK
falling edge, the part remains in normal mode and does not
power down. This avoids accidental power-down due to glitches
CS
on the
line.
high anywhere after the
th
falling edge of
CS
to SDATA
(see the Timing
8
CS
is brought high any time after the 10th SCLK falling edge
If
but before the 16
th
SCLK falling edge, the part remains powered
up but the conversion is terminated and SDATA goes back into
three-state. Sixteen serial clock cycles are required to complete
CS
the conversion and access the complete conversion result.
may idle high until the next conversion, or may idle low until
some time prior to the next conversion. Once a data transfer is
complete, i.e., when SDATA has returned to three-state, anothe r
conversion can be initiated after the quiet time, t
elapsed by again bringing
CS
SCLK
SDATA
110
4 LEADING ZEROS + CONVERSION RESULT
Figure 24. Normal Mode Operation
CS
low.
QUIET
16
, has
03155-A-024
To exit this mode of operation and power up the AD7453 again,
a dummy conversion is performed. On the falling edge of
CS
,
the device begins to power up, and continues to power up as
CS
long as
is held low until after the falling edge of the 10th
SCLK. The device is fully powered up after 1 µs has elapsed and,
as shown in Figure 26, valid data results from the next
conversion.
CS
is brought high before the 10th falling edge of SCLK, the
If
AD7453 again goes back into power-down. This avoids
accidental power-up due to glitches on the
inadvertent burst of eight SCLK cycles while
CS
line or an
CS
is low. So
although the device may begin to power up on the falling edge
CS
of
, it again powers down on the rising edge of CS as long as
it occurs before the 10
CS
SCLK
SDATA
th
SCLK falling edge.
2
1
Figure 25. Entering Power-Down Mode
10
THREE-STATE
03155-A-025
Rev. B | Page 15 of 20
AD7453
POWER-UP TIME
The power-up time of the AD7453 is typically 1 µs, which
means that with any frequency of SCLK up to 10 MHz, one
dummy cycle is always sufficient to allow the device to power
up. Once the dummy cycle is complete, the ADC is fully
powered up and the input signal is acquired properly. The quiet
time, t
bus goes back into three-state after the dummy conversion to
the next falling edge of
When running at the maximum throughput rate of 555 kSPS,
the AD7453 powers up and acquires a signal within ±0.5 LSB in
one dummy cycle. When powering up from power-down mode
with a dummy cycle, as in Figure 26, the track and-hold, which
was in hold mode while the part was powered down, returns to
track mode after the first SCLK edge the part receives after the
falling edge of
Although at any SCLK frequency one dummy cycle is sufficient
to power up the device and acquire V
mean that a full dummy cycle of 16 SCLKs must always elapse
to power up the device and acquire V
power up the device and acquire the input signal.
For example, if a 5 MHz SCLK frequency is applied to the ADC,
the cycle time is 3.2 µs (i.e., 1/(5 MHz) × 16). In one dummy
cycle, 3.2 µs, the part is powered up and V
However after 1 µs with a 5 MHz SCLK, only five SCLK cycles
have elapsed. At this stage, the ADC is fully powered up and the
signal acquired. So in this case,
th
10
to initiate the conversion.
, must still be allowed—from the point at which the
QUIET
CS
.
CS
. This is shown as Point A in Figure 26.
, it does not necessarily
IN
fully; 1 µs is sufficient to
IN
is acquired fully.
IN
CS
can be brought high after the
SCLK falling edge and brought low again after a time, t
t
POWER-UP
10 16 1 10 16
CS
SCLK
PART BEGINS
TO POWER UP
A
1
QUIET
When power supplies are first applied to the AD7453, the ADC
may either power up in the power-down mode or normal mode.
Because of this, it is best to allow a dummy cycle to elapse to
ensure that the part is fully powered up before attempting a
valid conversion. Likewise, if the user wants the part to power
up in power-down mode, the dummy cycle may be used to
ensure the device is in power-down mode by executing a cycle
such as that shown in Figure 25. Once supplies are applied to
the AD7453, the power-up time is the same as that when
powering up from power-down mode. It takes approximately
1 µs to power up fully if the part powers up in normal mode. It
is not necessary to wait 1 µs before executing a dummy cycle to
ensure the desired mode of operation. Instead, the dummy cycle
can occur directly after power is supplied to the ADC. If the
first valid conversion is then performed directly after the
dummy conversion, care must be taken to ensure that adequate
acquisition time has been allowed.
As mentioned earlier, when powering up from the power-down
mode, the part returns to track mode upon the first SCLK edge
CS
applied after the falling edge of
. However, when the ADC
powers up initially after supplies are applied, the track-and-hold
is already in track mode. This means (assuming one has the
facility to monitor the ADC supply current) that if the ADC
powers up in the desired mode of operation and thus a dummy
cycle is not required to change the mode, then a dummy cycle is
not required to place the track-and-hold into track.
,
THIS PART IS FULLY POWERED
UP WITH V
FULLY ACQUIRED
IN
SDATA
INVALID DATA VALID DATA
Figure 26. Exiting Power-Down Mode
Rev. B | Page 16 of 20
03155-A-026
AD7453
POWER VS. THROUGHPUT RATE
By using the power-down mode on the AD7453 when not converting, the average power consumption of the ADC decreases
at lower throughput rates. Figure 27 shows how, as the throughput rate is reduced, the device remains in its power-down state
longer and the average power consumption reduces accordingly.
For example, if the AD7453 is operated in continuous sampling
mode with a throughput rate of 100 kSPS and a 10 MHz SCLK,
and the device is placed in the power-down mode between conversions, then the power consumption is calculated as follows:
Power dissipation during normal operation = 7.25 mW max (for
= 5 V).
V
DD
If the power-up time is one dummy cycle (1.06 µs if
th
brought high after the 10
SCLK falling edge in the cycle and
then brought low after the quiet time) and the remaining
conversion time is another cycle (1.6 µs), then the AD7453 can
∗
be said to dissipate 7.25 mW for 2.66 µs
during each
conversion cycle.
If the throughput rate = 100 kSPS, then the cycle time = 10 µs
and the average power dissipated during each cycle is
(2.66/10) × 7.25 mW = 1.92 mW
For the same scenario, if V
= 3 V, the power dissipation during
DD
normal operation is 3.3 mW max. The AD7453 can now be said
∗
to dissipate 3.3 mW for 2.66 µs
during each conversion cycle.
The average power dissipated during each cycle with a
throughput rate of 100 kSPS is therefore
(2.66/10) × 3.3 mW = 0.88 mW
This is how the power numbers in Figure 27 are calculated.
100
CS
is
For throughput rates above 320 kSPS, the serial clock frequency
should be reduced for optimum power performance.
MICROPROCESSOR AND DSP INTERFACING
The serial interface on the AD7453 allows the part to be connected directly to a range of different microprocessors. This
section explains how to interface the AD7453 with some of the
more common microcontroller and DSP serial interface
protocols.
AD7453 to ADSP-21xx
The ADSP-21xx family of DSPs are interfaced directly to the
AD7453 without any glue logic required.
The SPORT control register should be set up as follows:
TFSW = RFSW = 1 Alternate Framing
INVRFS = INVTFS = 1 Active Low Frame Signal
DTYPE = 00 Right Justify Data
SLEN = 1111 16-Bit Data-Words
ISCLK = 1 Internal Serial Clock
TFSR = RFSR = 1 Frame Every Word
IRFS = 0
ITFS = 1
To implement power-down mode, SLEN should be set to 1001
to issue an 8-bit SCLK burst.
The connection diagram is shown in Figure 28. The ADSP-21xx
has the TFS and RFS of the SPORT tied together, with TFS set
as an output and RFS set as an input. The DSP operates in
alternate framing mode and the SPORT control register is set
up as described. The frame synchronization signal generated on
CS
the TFS is tied to
tions, equidistant sampling is necessary. However, in this
example, the timer interrupt is used to control the sampling rate
of the ADC, and, under certain conditions, equidistant sampling
may not be achieved.
, and, as with all signal processing applica-
10
1
POWER (mW)
0.1
0.01
Figure 27. Power vs. Throughput Rate for Power-Down Mode
50 100 150 200 250 300
0 350
VDD = 5V
V
DD
THROUGHPUT (kSPS)
= 3V
∗
This figure assumes a very short time to enter power-down mode. This
increases as the burst of clocks used to enter power down mode is
increased.
03155-A-027
Rev. B | Page 17 of 20
AD7453*
SCLK
SDATA
CS
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 28. Interfacing to the ADSP-21xx
ADSP-21xx*
SCLK
DR
RFS
TFS
03155-A-028
AD7453
The timer registers, for example, are loaded with a value that
provides an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and thus the
reading of data. The frequency of the serial clock is set in the
SCLKDIV register. When the instruction to transmit with TFS
is given, (i.e., AX0 = TX0), the state of the SCLK is checked. The
DSP waits until the SCLK has gone high, low, and high again
before transmission starts. If the timer and SCLK values are
chosen such that the instruction to transmit occurs on or near
the rising edge of SCLK, then the data may be transmitted or it
may wait until the next clock edge.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3, an
SCLK of 2 MHz is obtained and eight master clock periods
elapse for every SCLK period. If the timer registers are loaded
with the value 803, then 100.5 SCLKs occur between interrupts
and subsequently between transmit instructions. This situation
results in nonequidistant sampling as the transmit instruction is
occurring on an SCLK edge. If the number of SCLKs between
interrupts is a whole integer figure of N, equidistant sampling is
implemented by the DSP.
AD7453 to TMS320C5x/C54x
The serial interface on the TMS320C5x/C54x uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7453. The
TMS320C5x/C54x and the AD7453 without any glue logic
required. The serial port of the TMS320C5x/C54x is set up to
operate in burst mode with internal CLKx (Tx serial clock) and
FSx (Tx frame sync). The serial port control register (SPC) must
have the following setup: FO = 0, FSM = 1, MCM = 1 and TXM
= 1. The format bit, FO, may be set to 1 to set the word length to
eight bits in order to implement the power-down mode on the
AD7453. The connection diagram is shown in Figure 29. For
signal processing applications, it is imperative that the frame
synchronization signal from the TMS320C5x/C54x provide
equidistant sampling.
CS
input allows easy interfacing between the
AD7453*
SCLK
SDATA
CS
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 29. Interfacing to the TMS320C5x/C54x
TMS320C5x/
C54x*
CLKx
CLKR
DR
FSx
FSR
AD7453 to DSP56xxx
The connection diagram in Figure 30 shows how the AD7453
can be connected to the SSI (synchronous serial interface) of
the DSP56xxx family of DSPs from Motorola. The SSI is
operated in synchronous mode (SYN bit in CRB = 1) with
internally generated 1-bit clock period frame sync for both Tx
and Rx (Bit FSL1 = 1 and Bit FSL0 = 0 in CRB). Set the word
length to 16 by setting Bits WL1 = 1 and WL0 = 0 in CRA. To
implement the power-down mode on the AD7453, the word
length can be changed to eight bits by setting Bits WL1 = 0 and
WL0 = 0 in CRA. For signal processing applications, it is
imperative that the frame synchronization signal from the
DSP56xxx provide equidistant sampling.
AD7453*
SCLK
SDATA
CS
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 30. Interfacing to the DSP56xxx
DSP56xxx*
SCLK
SRD
SR2
03155-A-029
03155-A-030
Rev. B | Page 18 of 20
AD7453
APPLICATION HINTS
Grounding and Layout
The printed circuit board that houses the AD7453 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. A minimum
etch technique is generally best for ground planes as it gives the
best shielding. Digital and analog ground planes should be
joined in only one place, and the connection should be a star
ground point established as close to the GND pin on the
AD7453 as possible.
Avoid running digital lines under the device as this couples
noise onto the die. The analog ground plane should be allowed
to run under the AD7453 to avoid noise coupling. The power
supply lines to the AD7453 should use as large a trace as
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line.
Fast switching signals like clocks should be shielded with digital
ground to avoid radiating noise to other sections of the board,
and clock signals should never run near the analog inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A
microstrip technique is by far the best but is not always possible
with a double-sided board.
In this technique, the component side of the board is dedicated
to ground planes while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should
be decoupled with 10 µF tantalum capacitors in parallel with
0.1 µF capacitors to GND. To achieve the best from these
decoupling components, they must be placed as close as
possible to the device.
EVALUATING THE AD7453’S PERFORMANCE
The evaluation board package includes a fully assembled and
tested evaluation board, documentation, and software for
controlling the board from a PC via the evaluation board
controller. The evaluation board controller can be used in
conjunction with the AD7453 evaluation board, as well as many
other Analog Devices evaluation boards ending with the CB
designator, to demonstrate/evaluate the ac and dc performance
of the AD7453.
The software allows the user to perform ac (Fast Fourier
Transform) and dc (histogram of codes) tests on the AD7453.
For more information, see the AD7453 application note that
accompanies the evaluation kit.
Rev. B | Page 19 of 20
AD7453
OUTLINE DIMENSIONS
2.90 BSC
2
1.95
BSC
5 6
0.65 BSC
2.80 BSC
1.45 MAX
SEATING
PLANE
0.22
0.08
8°
4°
0°
0.60
0.45
0.30
1.60 BSC
PIN 1
1.30
1.15
0.90
0.15 MAX
84 7
13
0.38
0.22
COMPLIANT TO JEDEC STANDARDS MO-178BA
Figure 31. 8-Lead Small Outline Transistor Package [SOT-23]
(RT-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Linearity Error (LSB)1 Package Description Package Option Branding
AD7453ART-REEL7 –40°C to +85°C ±1.5 8-Lead SOT-23 RT-8 C0C
AD7453BRT-R2 –40°C to +85°C ±1 8-Lead SOT-23 RT-8 C09
AD7453BRT-REEL7 –40°C to +85°C ±1 8-Lead SOT-23 RT-8 C09
EVAL-AD7453CB2 Evaluation Board
EVAL-CONTROL BRD23 Controller Board
1
Linearity error here refers to integral nonlinearity error.
2
This can be used as a standalone evaluation board or in conjunction with the evaluation board controller for evaluation/demonstration purposes.
3
The evaluation board controller is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator.
For a complete Evaluation Kit, you will need to order the ADC evaluation board, i.e., EVAL-AD7453CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See the
AD7453 application note that accompanies the evaluation kit for more information.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03155–0–2/04(B)
Rev. B | Page 20 of 20
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