ANALOG DEVICES AD7452 Service Manual

Differential Input, 555 kSPS

V

V

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FEATURES

Specified for VDD of 3 V and 5 V
Low power at max throughput rate:

3.3 mW max at 555 kSPS with 3 V supplies

7.25 mW max at 555 kSPS with 5 V supplies
Fully differential analog input
Wide input bandwidth:
70 dB SINAD at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface:
SPI®/QSPI™/MICROWIRE™/DSP compatible
Power-down mode: 1 µA max
8-lead SOT-23 package

APPLICATIONS

Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation
Motor control

GENERAL DESCRIPTION

The AD74521 is a 12-bit, high speed, low power, successive
approximation (SAR) analog-to-digital converter that features a
fully differential analog input. This part operates from a single
3 V or 5 V power supply and features throughput rates up to
555 kSPS.

The part contains a low noise, wide bandwidth, differential
track-and-hold amplifier (T/H) that can handle input
frequencies up to 3.5 MHz. The reference voltage is applied
externally to the V

3.5 V depending on the power supply and what suits the
application. The value of the reference voltage determines the
common-mode voltage range of the part. With this truly
differential input structure and variable reference input, the
user can select a variety of input ranges and bias points.

The conversion process and data acquisition are controlled

CS

using

and the serial clock, allowing the device to interface
with microprocessors or DSPs. The input signals are sampled on
the falling edge of
point.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

pin and can be varied from 100 mV to

REF

CS

, and the conversion is also initiated at this

12-Bit ADC in an 8-Lead SOT-23

AD7452

FUNCTIONAL BLOCK DIAGRAM

DD

V

V

IN+

IN–

REF

T/H

AD7452

GND

The SAR architecture of this part ensures that there are no
pipeline delays.

The AD7452 uses advanced design techniques to achieve very
low power dissipation.

PRODUCT HIGHLIGHTS

1. Operation with Either 3 V or 5 V Power Supplies.

2. High Throughput with Low Power Consumption. With a

3 V supply, the AD7452 offers 3.3 mW max power
consumption for 555 kSPS throughput.

3. Fully Differential Analog Input.

4. Flexible Power/Serial Clock Speed Management. The

conversion rate is determined by the serial clock, allowing
the power to be reduced as the conversion time is reduced
through the serial clock speed increase. This part also
features a shutdown mode to maximize power efficiency at
lower throughput rates.

5. Variable Voltage Reference Input.

6. No Pipeline Delay.

7. Accurate Control of the Sampling Instant via a

and Once-Off Conversion Control.

8. ENOB > 8 Bits Typically with 100 mV Reference.

1

Protected by U.S. Patent Number 6,681,332.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

12-BIT

SUCCESSIVE

APPROXIMATION

CONTROL LOGIC

Figure 1.

ADC

CS

SCLK
SDATA
CS

03154-A-001

Input

AD7452

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TABLE OF CONTENTS

AD7452–Specifications.................................................................... 3

Reference ..................................................................................... 18

Timing Specifications .................................................................. 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Te r m in o l o g y ...................................................................................... 8

AD7452–Typical Performance Characteristics .......................... 10

Circuit Information........................................................................ 13

Converter Operation.................................................................. 13

ADC Transfer Function............................................................. 13

Typical C o n necti o n D i ag ram ................................................... 14

Analog Input ............................................................................... 14

Driving Differential Inputs........................................................ 16

Digital Inputs ..............................................................................18

REVISION HISTORY

2/04—Data Sheet changed from Rev. A to Rev. B

Single-Ended Operation............................................................ 18

Serial Interface............................................................................ 19

Modes of Operation ....................................................................... 20

Normal Mode.............................................................................. 20

Power-Down Mode .................................................................... 20

Power-Up Time .......................................................................... 21

Power vs. Throughput Rate ....................................................... 22

Microprocessor and DSP Interfacing ...................................... 22

Application Hints ....................................................................... 24

Evaluating the AD7452’s Performance .................................... 24

Outline Dimensions....................................................................... 25

Ordering Guide .......................................................................... 25

Added Patent Note ....................................................................... 1

2/04—Data Sheet changed from Rev. 0 to Rev. A

Updated Formatting.......................................................Universal

C

hanges to Applications section................................................. 1

Changes to General Description ................................................ 1

Changes to Specifications............................................................ 4

Changes to Timing Specifications.............................................. 5

Changes to Timing Example..................................................... 19

9/03—Revision 0: Initial Version

Rev. B | Page 2 of 28

AD7452

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AD7452–SPECIFICATIONS

VDD = 2.7 V to 3.6 V, f

1

V

= V

CM

; T = T to T , unless other wise noted.

REF A MIN MAX

Table 1.

Parameter Test Conditions/Comments B Version

DYNAMIC PERFORMANCE fIN = 100 kHz

Signal-to-(Noise + Distortion) (SINAD)
Total Harmonic Distortion (THD)3 VDD = 4.75 V to 5.25 V, –86 dB typ –76 dB max

V

Peak Harmonic or Spurious Noise3 V

V

Intermodulation Distortion (IMD)3 fa = 90 kHz, fb = 110 kHz

Second-Order Terms –89 dB typ

Third-Order Terms –89 dB typ
Aperture Delay3 5 ns typ
Aperture Jitter3 50 ps typ
Full Power Bandwidth

@ –0.1 dB 2.5 MHz typ
DC ACCURACY

Resolution 12 Bits
Integral Nonlinearity (INL) 3 ±1 LSB max
Differential Nonlinearity (DNL) 3 Guaranteed no missed codes to 12 bits ± 0.95 LSB max
Zero-Code Error3 ±6 LSB max
Positive Gain Error3 ±2 LSB max
Negative Gain Error3 ±2 LSB max

ANALOG INPUT

Full-Scale Input Span 2 × V
Absolute Input Voltage

V

VCM = V

IN+

V

VCM = V

IN–

DC Leakage Current ±1 µA max
Input Capacitance When in track/hold 30/10 pF typ

REFERENCE INPUT

V

Input Voltage

REF

DC Leakage Current ±1 µA max
V

Input Capacitance When in track/hold 10/30 pF typ

REF

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, IIN Typically 10 nA, VIN = 0 V or VDD ±1 µA max
Input Capacitance, CIN

LOGIC OUTPUTS

Output High Voltage, VOH VDD = 4.75 V to 5.25 V, I

V

Output Low Voltage, VOL I
Floating-State Leakage Current ±1 µA max
Floating-State Output Capacitance8 10 pF max
Output Coding Twos Complement

= 10 MHz, fS = 555 kSPS, V

SCLK

3

3, 4

INH

INL

8

= 2.0 V; VDD = 4.75 V to 5.25 V, f

REF

= 10 MHz, fS = 555 kSPS, V

SCLK

2

= 2.5 V;

REF

Unit

70 dB min

= 2.7 V to 3.6 V, –84 dB typ –74 dB max

DD

= 4.75 V to 5.25 V, –86 dB typ –76 dB max

DD

= 2.7 V to 3.6 V, –84 dB typ –74 dB max

DD

@ –3 dB 20 MHz typ

5

REF

V

REF

V

REF

= 4.75 V to 5.25 V (±1% tolerance for

V

DD

V

– V

V

IN+

IN–

1

± V

CM

CM

2.5

/2 V

REF

1

± V

/2 V

REF

6

V

specified performance)

7

V

= 2.7 V to 3.6 V (±1% tolerance for

V

DD

2.0

specified performance)

2.4 V min

0.8 V max

10 pF max

= 200 µA 2.8 V min

SOURCE

= 2.7 V to 3.6 V, I

DD

= 200 µA 0.4 V max

SINK

= 200 µA 2.4 V min

SOURCE

Rev. B | Page 3 of 28

AD7452

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Parameter Test Conditions/Comments B Version

2

Unit

CONVERSION RATE

Conversion Time 1.6 µs with a 10 MHz SCLK 16 SCLK cycles
Track-and-Hold Acquisition Time3 Sine wave input 200 ns max

Step input 290 ns max

Throughput Rate 555 kSPS max

POWER REQUIREMENTS

VDD Range: 3 V + 20%/–10%;

5 V ± 5% 2.7/5.25 V min/V max

9, 10

I

DD

Normal Mode (Static) SCLK on or off 0.5 mA typ
Normal Mode (Operational) VDD = 4.75 V to 5.25 V 1.5 mA max

V

= 2.7 V to 3.6 V 1.2 mA max

DD

Full Power-Down Mode SCLK on or off 1 µA max

Power Dissipation

Normal Mode (Operational) VDD = 5 V, 1.55 mW typ for 100 kSPS9 7.25 mW max

V

= 3 V, 0.64 mW typ for 100 kSPS9 3.3 mW max

DD

Full Power-Down VDD = 5 V, SCLK on or off 5 µW max

V

= 3 V, SCLK on or off 3 µW max

DD

are both V

IN–

and are 180° out of phase, the differential voltage is 2 × V

REF

REF.

1

Common-mode voltage. The input signal can be centered on a dc common-mode voltage in the range specified in and . Figure 23 Figure 24

2

Temperature ranges as follows: B Version: –40°C to +85°C.

3

See section. Terminology

4

Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by the

converter.

5

Because the input spans of V

6

The AD7452 is functional with a reference input from 100 mV; for VDD = 5 V, the reference can range up to 3.5 V.

7

The AD7452 is functional with a reference input from 100 mV; for VDD = 3 V, the reference can range up to 2.2 V.

8

Guaranteed by characterization.

9

See section. Power vs. Throughput Rate

10

Measured with a midscale dc input.

IN+

and V

Rev. B | Page 4 of 28

AD7452

A

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TIMING SPECIFICATIONS

Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a 1.6 V voltage
level. See Figure 2 and the Serial Interface section.

= 2.7 V to 3.6 V, f

V

DD

1

= V

V

CM

; T = T to T , unless other wise noted.

REF A MIN MAX

= 10 MHz, fS = 555 kSPS, V

SCLK

= 2.0 V; VDD = 4.75 V to 5.25 V, f

REF

= 10 MHz, fS = 555 kSPS, V

SCLK

Table 2.

Parameter Limit at T

2

f

SCLK

10 kHz min

MIN

, T

Unit Description

MAX

10 MHz max
t

CONVERT

16 × t

t

SCLK

SCLK

= 1/f

SCLK

1.6 µs max
t

60 ns min

QUIET

t1 10 ns min
t2 10 ns min

3

t

20 ns max

3

3

t

4

t5 0.4 t
t6 0.4 t

40 ns max Data access time after SCLK falling edge

ns min SCLK high pulse width

SCLK

ns min SCLK low pulse width

SCLK

Minimum quiet time between the end of a serial read and the next falling edge of

CS

Minimum
CS

falling edge to SCLK falling edge setup time

pulse width

Delay from CS falling edge until SDATA three-state disabled

t7 10 ns min SCLK edge to data valid hold time
t8 4 10 ns min SCLK falling edge to SDATA three-state enabled
35 ns max SCLK falling edge to SDATA three-state enabled

5

t

1 µs max Power-up time from full power-down

POWER-UP

SCLK

SDAT

CS

t

2

12345 13141516

t

3

0 0 0 0 DB11 DB10 DB2 DB1 DB0

4 LEADING ZEROS THREE-STATE

t

4

t

CONVERT

t

5

t

7

Figure 2. Serial Interface Timing Diagram

B

t

6

t

8

t

QUIET

= 2.5 V;

REF

CS

t

1

03154-A-002

1

Common-mode voltage.

2

Mark/space ratio for the SCLK input is 40/60 to 60/40.

3

Measured with the load circuit of and defined as the time required for the output to cross 0.8 V or 2.4 V with VFigure 3

4

t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of The measured number is then extrapolated

back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the Timing Specifications is the true bus relinquish
time of the part and is independent of the bus loading.

5

See section. Power-Up Time

Figure 3.

Rev. B | Page 5 of 28

= 5 V, or 0.4 V or 2.0 V for VDD = 3 V.

DD

AD7452

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND –0.3 V to +7 V
V

to GND –0.3 V to VDD + 0.3 V

IN+

V

to GND –0.3 V to VDD + 0.3 V

IN–

Digital Input Voltage to GND –0.3 V to +7 V
Digital Output Voltage to GND –0.3 V to VDD + 0.3 V
V

to GND –0.3 V to VDD + 0.3 V

REF

Input Current to Any Pin Except Supplies1±10 mA
Operating Temperature Range

Commercial (B Version) –40°C to +85°C
Storage Temperature Range –65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance 211.5°C/W
θJC Thermal Impedance 91.99°C/W
Lead Temperature, Soldering

Vapor Phase (60 secs) 215°C

Infrared (15 secs) 220°C
ESD 1 kV

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

TO OUTPUT

Figure 3. Load Circuit for Digital Output Timing Specifications

PIN

25pF

C

L

1.6mA I

200µAI

OL

OH

1.6V

03154-A-003

1

Transient currents of up to 100 mA will not cause SCR latch-up.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. B | Page 6 of 28

AD7452

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 4. 8-Lead SOT-23 Pin Configuration

Table 4. Pin Function Descriptions

Mnemonic Function

V

REF

Reference Input for the AD7452. An external reference must be applied to this input. For a 5 V power supply, the reference is

2.5 V (± 1%) for specified performance. For a 3 V power supply, the reference is 2 V (± 1%) for specified performance. This pin
should be decoupled to GND with a capacitor of at least 0.1 µF. See the Reference section for more details.

V

Positive Terminal for Differential Analog Input.

IN+

V

Negative Terminal for Differential Analog Input.

IN–

GND

Analog Ground. Ground reference point for all circuitry on the AD7452. All analog input signals and any external reference
signal should be referred to this GND voltage.

CS

Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on the AD7452 and
framing the serial data transfer.

SDATA

Serial Data. Logic output. The conversion result from the AD7452 is provided on this output as a serial data stream. The bits
are clocked out on the falling edge of the SCLK input. The data stream consists of four leading zeros followed by the 12 bits of
conversion data, which are provided MSB first. The output coding is twos complement.

SCLK

Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the
clock source for the conversion process.

VDD

Power Supply Input. V

is 3 V (+20%/–10%) or 5 V (± 5%). This supply should be decoupled to GND with a 0.1 µF capacitor

DD

and a 10 µF tantalum capacitor in parallel.

V

SCLK

SDATA

CS

DD

1
2

AD7452

TOP VIEW

3

(Not to Scale)

4

V

8

REF

V

7

IN+

6

V

IN–

GND

5

03154-A-004

Rev. B | Page 7 of 28

AD7452

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TERMINOLOGY

Signal-to-(Noise + Distortion) Ratio

The measured ratio of signal to (noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the fun­damental. Noise is the sum of all nonfundamental signals up to
half the sampling frequency (f
dependent on the number of quantization levels in the digitiza­tion process; the more levels, the smaller the quantization noise.
The theoretical signal-to-(noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by

/2), excluding dc. The ratio is

S

The AD7452 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second-order terms are usually distanced in
frequency from the original sine waves while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in dB.

Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB

Thus, for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion (THD)

Total harmonic distortion is the ratio of the rms sum of
harmonics to the fundamental. For the AD7452, it is defined as

22222

++++

65432

log20)dB(

THD

where V
V

is the rms amplitude of the fundamental and V2, V3,

1

, V5, and V6 are the rms amplitudes of the second to the sixth

4

=

1

V

VVVVV

harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f

/2 and excluding dc) to the rms value of the

S

fundamental. Normally, the value of this specification is deter­mined by the largest harmonic in the spectrum, but for ADCs
where the harmonics are buried in the noise floor, it is a noise
peak.

Aperture Delay

The amount of time from the leading edge of the sampling
clock until the ADC actually takes the sample.

Aperture Jitter

The sample-to-sample variation in the effective point in time at
which the actual sample is taken.

Full Power Bandwidth

The full power bandwidth of an ADC is the input frequency at
which the amplitude of the reconstructed fundamental is
reduced by 0.1 dB or 3 dB for a full-scale input.

Common-Mode Rejection Ratio (CMRR)

This is the ratio of the power in the ADC output at full-scale
frequency, f, to the power of a 100 mV p-p sine wave applied to
the common-mode voltage of V

CMRR(dB) = 10 log(Pf/Pf

Pf is the power at the frequency f in the ADC output; Pf

power at frequency f

in the ADC output.

S

IN+

and V

of frequency fS

IN–

)

S

is the

S

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion pro­ducts at the sum and difference frequencies of mfa ± nfb where

Integral Nonlinearity (INL)

The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function.

m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second-order terms include (fa + fb) and (fa − fb), while the
third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb) and

Differential Nonlinearity (DNL)

The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

(fa − 2fb).

Zero Code Error

The deviation of the midscale code transition (111…111 to

000...000) from the ideal V

IN+

Rev. B | Page 8 of 28

– V

(i.e., 0 LSB)

IN–

AD7452

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Positive Gain Error

This is the deviation of the last code transition (011...110 to

011...111) from the ideal V
zero code error has been adjusted out.

Negative Gain Error

This is the deviation of the first code transition (100...000 to

100...001) from the ideal V
the zero code error has been adjusted out.

IN+

IN+

– V

– V

(i.e., V

IN–

(i.e., –V

IN–

– 1 LSB), after the

REF

+ 1 LSB), after

REF

Power Supply Rejection Ratio (PSRR)

The ratio of the power in the ADC output at full-scale fre­quency, f, to the power of a 100 mV p-p sine wave applied to the
ADC V
varies from 1 kHz to 1 MHz.

Pf is t
power at frequency f

supply of frequency fS. The frequency of this input

DD

PSRR(dB) = 10log(Pf/Pf

he power at frequency f in the ADC output; Pfs is the

in the ADC output.

S

)

S

Track-and-Hold Acquisition Time

The minimum time required for the track-and-hold amplifier to
remain in track mode for its output to reach and settle to within

0.5 LSB of the applied input signal.

Rev. B | Page 9 of 28