ANALOG DEVICES AD7452 Service Manual

Differential Input, 555 kSPS

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FEATURES

Specified for VDD of 3 V and 5 V Low power at max throughput rate:

3.3 mW max at 555 kSPS with 3 V supplies

7.25 mW max at 555 kSPS with 5 V supplies Fully differential analog input Wide input bandwidth: 70 dB SINAD at 100 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface: SPI®/QSPI™/MICROWIRE™/DSP compatible Power-down mode: 1 µA max 8-lead SOT-23 package

APPLICATIONS

Transducer interface Battery-powered systems Data acquisition systems Portable instrumentation Motor control

GENERAL DESCRIPTION

The AD74521 is a 12-bit, high speed, low power, successive approximation (SAR) analog-to-digital converter that features a fully differential analog input. This part operates from a single 3 V or 5 V power supply and features throughput rates up to 555 kSPS.

The part contains a low noise, wide bandwidth, differential track-and-hold amplifier (T/H) that can handle input frequencies up to 3.5 MHz. The reference voltage is applied externally to the V

3.5 V depending on the power supply and what suits the application. The value of the reference voltage determines the common-mode voltage range of the part. With this truly differential input structure and variable reference input, the user can select a variety of input ranges and bias points.

The conversion process and data acquisition are controlled

using

and the serial clock, allowing the device to interface with microprocessors or DSPs. The input signals are sampled on the falling edge of point.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

pin and can be varied from 100 mV to

REF

, and the conversion is also initiated at this

12-Bit ADC in an 8-Lead SOT-23

AD7452

FUNCTIONAL BLOCK DIAGRAM

IN+

IN–

REF

T/H

AD7452

GND

The SAR architecture of this part ensures that there are no pipeline delays.

The AD7452 uses advanced design techniques to achieve very low power dissipation.

PRODUCT HIGHLIGHTS

1. Operation with Either 3 V or 5 V Power Supplies.

2. High Throughput with Low Power Consumption. With a

3 V supply, the AD7452 offers 3.3 mW max power consumption for 555 kSPS throughput.

3. Fully Differential Analog Input.

4. Flexible Power/Serial Clock Speed Management. The

conversion rate is determined by the serial clock, allowing the power to be reduced as the conversion time is reduced through the serial clock speed increase. This part also features a shutdown mode to maximize power efficiency at lower throughput rates.

5. Variable Voltage Reference Input.

6. No Pipeline Delay.

7. Accurate Control of the Sampling Instant via a

and Once-Off Conversion Control.

8. ENOB > 8 Bits Typically with 100 mV Reference.

Protected by U.S. Patent Number 6,681,332.

12-BIT

SUCCESSIVE

APPROXIMATION

CONTROL LOGIC

Figure 1.

ADC

SCLK SDATA CS

03154-A-001

Input

AD7452

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TABLE OF CONTENTS

AD7452–Specifications.................................................................... 3

Reference ..................................................................................... 18

Timing Specifications .................................................................. 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Te r m in o l o g y ...................................................................................... 8

AD7452–Typical Performance Characteristics .......................... 10

Circuit Information........................................................................ 13

Converter Operation.................................................................. 13

ADC Transfer Function............................................................. 13

Typical C o n necti o n D i ag ram ................................................... 14

Analog Input ............................................................................... 14

Driving Differential Inputs........................................................ 16

Digital Inputs ..............................................................................18

REVISION HISTORY

2/04—Data Sheet changed from Rev. A to Rev. B

Single-Ended Operation............................................................ 18

Serial Interface............................................................................ 19

Modes of Operation ....................................................................... 20

Normal Mode.............................................................................. 20

Power-Down Mode .................................................................... 20

Power-Up Time .......................................................................... 21

Power vs. Throughput Rate ....................................................... 22

Microprocessor and DSP Interfacing ...................................... 22

Application Hints ....................................................................... 24

Evaluating the AD7452’s Performance .................................... 24

Outline Dimensions....................................................................... 25

Ordering Guide .......................................................................... 25

Added Patent Note ....................................................................... 1

2/04—Data Sheet changed from Rev. 0 to Rev. A

Updated Formatting.......................................................Universal

hanges to Applications section................................................. 1

Changes to General Description ................................................ 1

Changes to Specifications............................................................ 4

Changes to Timing Specifications.............................................. 5

Changes to Timing Example..................................................... 19

9/03—Revision 0: Initial Version

Rev. B | Page 2 of 28

AD7452

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AD7452–SPECIFICATIONS

VDD = 2.7 V to 3.6 V, f

= V

; T = T to T , unless other wise noted.

REF A MIN MAX

Table 1.

Parameter Test Conditions/Comments B Version

DYNAMIC PERFORMANCE fIN = 100 kHz

Signal-to-(Noise + Distortion) (SINAD) Total Harmonic Distortion (THD)3 VDD = 4.75 V to 5.25 V, –86 dB typ –76 dB max

Peak Harmonic or Spurious Noise3 V

Intermodulation Distortion (IMD)3 fa = 90 kHz, fb = 110 kHz

Second-Order Terms –89 dB typ

Third-Order Terms –89 dB typ Aperture Delay3 5 ns typ Aperture Jitter3 50 ps typ Full Power Bandwidth

@ –0.1 dB 2.5 MHz typ DC ACCURACY

Resolution 12 Bits Integral Nonlinearity (INL) 3 ±1 LSB max Differential Nonlinearity (DNL) 3 Guaranteed no missed codes to 12 bits ± 0.95 LSB max Zero-Code Error3 ±6 LSB max Positive Gain Error3 ±2 LSB max Negative Gain Error3 ±2 LSB max

ANALOG INPUT

Full-Scale Input Span 2 × V Absolute Input Voltage

VCM = V

IN+

VCM = V

IN–

DC Leakage Current ±1 µA max Input Capacitance When in track/hold 30/10 pF typ

REFERENCE INPUT

Input Voltage

REF

DC Leakage Current ±1 µA max V

Input Capacitance When in track/hold 10/30 pF typ

REF

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, IIN Typically 10 nA, VIN = 0 V or VDD ±1 µA max Input Capacitance, CIN

LOGIC OUTPUTS

Output High Voltage, VOH VDD = 4.75 V to 5.25 V, I

Output Low Voltage, VOL I Floating-State Leakage Current ±1 µA max Floating-State Output Capacitance8 10 pF max Output Coding Twos Complement

= 10 MHz, fS = 555 kSPS, V

SCLK

3, 4

INH

INL

= 2.0 V; VDD = 4.75 V to 5.25 V, f

REF

= 10 MHz, fS = 555 kSPS, V

SCLK

= 2.5 V;

REF

Unit

70 dB min

= 2.7 V to 3.6 V, –84 dB typ –74 dB max

= 4.75 V to 5.25 V, –86 dB typ –76 dB max

= 2.7 V to 3.6 V, –84 dB typ –74 dB max

@ –3 dB 20 MHz typ

REF

= 4.75 V to 5.25 V (±1% tolerance for

– V

IN+

IN–

± V

2.5

/2 V

REF

± V

/2 V

REF

specified performance)

= 2.7 V to 3.6 V (±1% tolerance for

2.0

specified performance)

2.4 V min

0.8 V max

10 pF max

= 200 µA 2.8 V min

SOURCE

= 2.7 V to 3.6 V, I

= 200 µA 0.4 V max

SINK

= 200 µA 2.4 V min

SOURCE

Rev. B | Page 3 of 28

AD7452

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Parameter Test Conditions/Comments B Version

Unit

CONVERSION RATE

Conversion Time 1.6 µs with a 10 MHz SCLK 16 SCLK cycles Track-and-Hold Acquisition Time3 Sine wave input 200 ns max

Step input 290 ns max

Throughput Rate 555 kSPS max

POWER REQUIREMENTS

VDD Range: 3 V + 20%/–10%;

5 V ± 5% 2.7/5.25 V min/V max

9, 10

Normal Mode (Static) SCLK on or off 0.5 mA typ Normal Mode (Operational) VDD = 4.75 V to 5.25 V 1.5 mA max

= 2.7 V to 3.6 V 1.2 mA max

Full Power-Down Mode SCLK on or off 1 µA max

Power Dissipation

Normal Mode (Operational) VDD = 5 V, 1.55 mW typ for 100 kSPS9 7.25 mW max

= 3 V, 0.64 mW typ for 100 kSPS9 3.3 mW max

Full Power-Down VDD = 5 V, SCLK on or off 5 µW max

= 3 V, SCLK on or off 3 µW max

are both V

IN–

and are 180° out of phase, the differential voltage is 2 × V

REF

REF.

Common-mode voltage. The input signal can be centered on a dc common-mode voltage in the range specified in and . Figure 23 Figure 24

Temperature ranges as follows: B Version: –40°C to +85°C.

See section. Terminology

Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by the

converter.

Because the input spans of V

The AD7452 is functional with a reference input from 100 mV; for VDD = 5 V, the reference can range up to 3.5 V.

The AD7452 is functional with a reference input from 100 mV; for VDD = 3 V, the reference can range up to 2.2 V.

Guaranteed by characterization.

See section. Power vs. Throughput Rate

Measured with a midscale dc input.

IN+

and V

Rev. B | Page 4 of 28

AD7452

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TIMING SPECIFICATIONS

Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a 1.6 V voltage level. See Figure 2 and the Serial Interface section.

= 2.7 V to 3.6 V, f

= V

; T = T to T , unless other wise noted.

REF A MIN MAX

= 10 MHz, fS = 555 kSPS, V

SCLK

= 2.0 V; VDD = 4.75 V to 5.25 V, f

REF

= 10 MHz, fS = 555 kSPS, V

SCLK

Table 2.

Parameter Limit at T

SCLK

10 kHz min

MIN

, T

Unit Description

MAX

10 MHz max t

CONVERT

16 × t

SCLK

= 1/f

SCLK

1.6 µs max t

60 ns min

QUIET

t1 10 ns min t2 10 ns min

20 ns max

t5 0.4 t t6 0.4 t

40 ns max Data access time after SCLK falling edge

ns min SCLK high pulse width

SCLK

ns min SCLK low pulse width

SCLK

Minimum quiet time between the end of a serial read and the next falling edge of

Minimum CS

falling edge to SCLK falling edge setup time

pulse width

Delay from CS falling edge until SDATA three-state disabled

t7 10 ns min SCLK edge to data valid hold time t8 4 10 ns min SCLK falling edge to SDATA three-state enabled 35 ns max SCLK falling edge to SDATA three-state enabled

1 µs max Power-up time from full power-down

POWER-UP

SCLK

SDAT

12345 13141516

0 0 0 0 DB11 DB10 DB2 DB1 DB0

4 LEADING ZEROS THREE-STATE

CONVERT

Figure 2. Serial Interface Timing Diagram

QUIET

= 2.5 V;

REF

03154-A-002

Common-mode voltage.

Mark/space ratio for the SCLK input is 40/60 to 60/40.

Measured with the load circuit of and defined as the time required for the output to cross 0.8 V or 2.4 V with VFigure 3

t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of The measured number is then extrapolated

back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the Timing Specifications is the true bus relinquish time of the part and is independent of the bus loading.

See section. Power-Up Time

Figure 3.

Rev. B | Page 5 of 28

= 5 V, or 0.4 V or 2.0 V for VDD = 3 V.

AD7452

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND –0.3 V to +7 V V

to GND –0.3 V to VDD + 0.3 V

IN+

to GND –0.3 V to VDD + 0.3 V

IN–

Digital Input Voltage to GND –0.3 V to +7 V Digital Output Voltage to GND –0.3 V to VDD + 0.3 V V

to GND –0.3 V to VDD + 0.3 V

REF

Input Current to Any Pin Except Supplies1±10 mA Operating Temperature Range

Commercial (B Version) –40°C to +85°C Storage Temperature Range –65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 211.5°C/W θJC Thermal Impedance 91.99°C/W Lead Temperature, Soldering

Vapor Phase (60 secs) 215°C

Infrared (15 secs) 220°C ESD 1 kV

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

TO OUTPUT

Figure 3. Load Circuit for Digital Output Timing Specifications

25pF

1.6mA I

200µAI

1.6V

03154-A-003

Transient currents of up to 100 mA will not cause SCR latch-up.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. B | Page 6 of 28

AD7452

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 4. 8-Lead SOT-23 Pin Configuration

Table 4. Pin Function Descriptions

Mnemonic Function

REF

Reference Input for the AD7452. An external reference must be applied to this input. For a 5 V power supply, the reference is

2.5 V (± 1%) for specified performance. For a 3 V power supply, the reference is 2 V (± 1%) for specified performance. This pin should be decoupled to GND with a capacitor of at least 0.1 µF. See the Reference section for more details.

Positive Terminal for Differential Analog Input.

IN+

Negative Terminal for Differential Analog Input.

IN–

GND

Analog Ground. Ground reference point for all circuitry on the AD7452. All analog input signals and any external reference signal should be referred to this GND voltage.

Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on the AD7452 and framing the serial data transfer.

SDATA

Serial Data. Logic output. The conversion result from the AD7452 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists of four leading zeros followed by the 12 bits of conversion data, which are provided MSB first. The output coding is twos complement.

SCLK

Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process.

VDD

Power Supply Input. V

is 3 V (+20%/–10%) or 5 V (± 5%). This supply should be decoupled to GND with a 0.1 µF capacitor

and a 10 µF tantalum capacitor in parallel.

SCLK

SDATA

1 2

AD7452

TOP VIEW

(Not to Scale)

REF

IN+

IN–

GND

03154-A-004

Rev. B | Page 7 of 28

AD7452

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TERMINOLOGY

Signal-to-(Noise + Distortion) Ratio

The measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by

/2), excluding dc. The ratio is

The AD7452 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dB.

Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB

Thus, for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion (THD)

Total harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. For the AD7452, it is defined as

22222

++++

65432

log20)dB(

THD

where V V

is the rms amplitude of the fundamental and V2, V3,

, V5, and V6 are the rms amplitudes of the second to the sixth

VVVVV

harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to f

/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak.

Aperture Delay

The amount of time from the leading edge of the sampling clock until the ADC actually takes the sample.

Aperture Jitter

The sample-to-sample variation in the effective point in time at which the actual sample is taken.

Full Power Bandwidth

The full power bandwidth of an ADC is the input frequency at which the amplitude of the reconstructed fundamental is reduced by 0.1 dB or 3 dB for a full-scale input.

Common-Mode Rejection Ratio (CMRR)

This is the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the common-mode voltage of V

CMRR(dB) = 10 log(Pf/Pf

Pf is the power at the frequency f in the ADC output; Pf

power at frequency f

in the ADC output.

IN+

and V

of frequency fS

IN–

)

is the

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at the sum and difference frequencies of mfa ± nfb where

Integral Nonlinearity (INL)

The maximum deviation from a straight line passing through the endpoints of the ADC transfer function.

m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second-order terms include (fa + fb) and (fa − fb), while the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb) and

Differential Nonlinearity (DNL)

The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.

(fa − 2fb).

Zero Code Error

The deviation of the midscale code transition (111…111 to

000...000) from the ideal V

IN+

Rev. B | Page 8 of 28

– V

(i.e., 0 LSB)

IN–

AD7452

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Positive Gain Error

This is the deviation of the last code transition (011...110 to

011...111) from the ideal V zero code error has been adjusted out.

Negative Gain Error

This is the deviation of the first code transition (100...000 to

100...001) from the ideal V the zero code error has been adjusted out.

IN+

– V

(i.e., V

IN–

(i.e., –V

IN–

– 1 LSB), after the

REF

+ 1 LSB), after

REF

Power Supply Rejection Ratio (PSRR)

The ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the ADC V varies from 1 kHz to 1 MHz.

Pf is t power at frequency f

supply of frequency fS. The frequency of this input

PSRR(dB) = 10log(Pf/Pf

he power at frequency f in the ADC output; Pfs is the

in the ADC output.

)

Track-and-Hold Acquisition Time

The minimum time required for the track-and-hold amplifier to remain in track mode for its output to reach and settle to within

0.5 LSB of the applied input signal.

Rev. B | Page 9 of 28

AD7452

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AD7452–TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, fS = 555 kSPS, f

SINAD (dB)

= 10 MHz, unless otherwise noted.

SCLK

VDD = 5.25V

= 3.6V

VDD = 4.75V

VDD = 2.7V

–20

–40

–60

–80

SNR (dB)

8192 POINT FFT

= 555kSPS

SAMPLE

= 100kSPS

SINAD = 71.7dB THD = –82dB SFDR = –83dB

10 100

FREQUENCY (kHz)

03154-A-005

277

Figure 5. SINAD vs. Analog Input Frequency for Various Supply Voltages

–10

–20

–30

–40

–50

CMRR (dB)

–60

–70

–80

–90

–100

10 100

Figure 6. CMRR vs. Freq uency fo r V

VDD = 3V

FREQUENCY (kHz)

VDD = 5V

1000

= 5 V and 3 V

03154-A-006

10000

100mV p-p SINE WAVE ON V

NO DECOUPLING ON V

–20

–40

–60

PSRR (dB)

–80

–100

–120

0 100 200 300 400 500

SUPPLY RIPPLE FREQUENCY (kHz)

VDD= 3V

VDD= 5V

600 700 800

03154-A-007

900 1000

Figure 7. PSRR vs. Supply Ripple Frequency without Supply Decoupling

–100

–120

–140

0 100 200

Figure 8. Dynamic Performance with V

FREQUENCY (kHz)

= 5 V

03154-A-008

277

1.0

0.8

0.6

0.4

0.2

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

10240 2048 3072 4096

CODE

Figure 9. Typical DNL for V

= 5 V

03154-A-009

1.0

0.8

0.6

0.4

0.2

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

10240 2048 3072 4096

CODE

Figure 10. Typical INL for V

= 5 V

03154-A-010

Rev. B | Page 10 of 28

AD7452

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3.0

2.0

2.5

2.0

1.5

1.0

0.5

CHANGE IN DNL (LSB)

–0.5

–1.0

0 0.5 1.0 1.5 2.0 2.5

Figure 11. Change in DNL vs. V

REF

POSITIVE DNL

NEGATIVE DNL

(V)

for VDD = 5 V

REF

2.5

2.0

1.5

1.0 POSITIVE DNL

0.5

CHANGE IN DNL (LSB)

–0.5

–1.0

0 0.5 1.0 1.5 2.0 2.5

Figure 12. Change in DNL vs. V

NEGATIVE DNL

(V)

REF

for VDD = 3 V

REF

4 3 2

0 –1

–2

CHANGE IN INL (LSB)

–3

–4 –5

0 0.5 1.0 1.5 2.0 2.5

Figure 13. Change in INL vs. V

REF

POSITIVE INL

NEGATIVE INL

(V)

for VDD = 5 V

REF

3.0 3.5

2.2

3.0 3.5

1.5

1.0

0.5

CHANGE IN INL (LSB)

–0.5

–1.5

03154-A-011

–2.0

0 0.5 1.0 1.5 2.0

Figure 14. Change in INL vs. V

POSITIVE INL

NEGATIVE INL

(V)

REF

03154-A-014

2.2 2.5

for VDD = 3 V

VDD= 5V

VDD= 3V

ZERO-CODE ERROR (LSB)

03154-A-012

Figure 15. Change in Zero-Code Error vs. Reference Voltage V

0 0.5 1.0 1.5 2.0 2.5

(V)

REF

3.0 3.5

03154-A-015

= 5 V and 3 V

12.0

11.5 VDD = 3V

11.0

10.5

10.0

9.5

9.0

8.5

EFFECTIVE NUMBER OF BITS

8.0

7.5

03154-A-013

7.0 0 0.5 1.0 1.5 2.0 2.5

Figure 16. Change in ENOB vs. Reference Voltage V

VDD = 5V

03154-A-016

3.5

(V)

REF

3.0

= 5 V and 3 V

Rev. B | Page 11 of 28

AD7452

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10,000

= V

IN+

IN–

10,000 CONVERSIONS

9,000

= 555kSPS

8,000

7,000

6,000

5,000

4,000

3,000

2,000 1,000

2044 2046 2047 2048 20492045

Figure 17. Histogram of 10,000 Conversions of a DC Input with V

10,000

CODES

CODE

03154-A-017

= 5 V

Rev. B | Page 12 of 28

AD7452

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CIRCUIT INFORMATION

The AD7452 is a 12-bit, low power, single-supply, successive approximation analog-to-digital converter (ADC). It can operate with a 5 V or 3 V power supply, and is capable of throughput rates up to 555 kSPS when supplied with a 10 MHz SCLK. It requires an external reference to be applied to the V

REF

pin, with the value of the reference chosen depending on the power supply and what suits the application.

When operated with a 5 V supply, the maximum reference that can be applied is 3.5 V. When operated with a 3 V supply, the maximum reference that can be applied is 2.2 V (see the Reference section).

The AD7452 has an on-chip differential track-and-hold amplifier, a successive approximation (SAR) ADC, and a serial interface, housed in an 8-lead SOT-23 package. The serial clock input accesses data from the part and provides the clock source for the successive approximation ADC. The AD7452 features a power-down option for reduced power consumption between conversions. The power-down feature is implemented across the standard serial interface as described in the Modes of Operation section.

CONVERTER OPERATION

The AD7452 is a successive approximation ADC based around two capacitive DACs. Figure 18 and Figure 19 show simplified schematics of the ADC in the acquisition and conversion phase, respectively. The ADC is comprised of control logic, an SAR, and two capacitive DACs. In Figure 18 (acquisition phase), SW3 is closed and SW1 and SW2 are in Position A, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input.

CAPACITIVE

DAC

IN+

IN–

SW1

SW2

REF

SW3

COMPARATOR

Figure 18. ADC Acquisition Phase

CONTROL

LOGIC

CAPACITIVE

DAC

03154-A-018

When the ADC starts a conversion (Figure 19), SW3 opens and SW1 and SW2 move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC’s output code. The output impedances of the sources driving the V

and the V

IN+

pins must be matched;

IN–

otherwise, the two inputs will have different settling times, resulting in errors.

CAPACITIVE

DAC

IN+

IN–

SW1

SW2

REF

SW3

COMPARATOR

CONTROL

LOGIC

CAPACITIVE

DAC

03154-A-019

Figure 19. ADC Conversion Phase

ADC TRANSFER FUNCTION

The output coding for the AD7452 is twos complement. The designed code transitions occur at successive LSB values (i.e., 1 LSB, 2 LSBs, and so on). The LSB size is 2 × V The ideal transfer characteristic of the AD7452 is shown in Figure 20.

1LSB = 2 × V

011...111

011...110

000...001

000...000

111...111

ADC CODE

100...010

100...001

100...000 1LSB

–V

REF

Figure 20. Ideal Transfer Characteristic

/4096

REF

IN+–VIN–

+ V

)

0 LSB

ANALOG INPUT

REF

– 1LSB

REF

/4096.

03154-A-020

Rev. B | Page 13 of 28

AD7452

www.BDTIC.com/ADI

TYPICAL CONNECTION DIAGRAM

Figure 21 shows a typical connection diagram for the AD7452 for both 5 V and 3 V supplies. In this setup, the GND pin is connected to the analog ground plane of the system. The V pin is connected to either a 2.5 V or a 2 V decoupled reference source, depending on the power supply, to set up the analog input range. The common-mode voltage has to be set up externally and is the value on which the two inputs are centered. The conversion result is output in a 16-bit word with four leading zeros followed by the MSB of the 12-bit result. For more details on driving the differential inputs and setting up the common mode, refer to the Driving Differential Inputs section.

3V/5V

0.1µF

REF

p-p

CM*

IN+

AD7452

REF

p-p

*CM IS THE COMMON-MODE VOLTAGE.

CM*

0.1µF

IN–

REF

2V/2.5V

10µF

REF

SUPPLY

SCLK

SDATA

GND

SERIAL

INTERFACE

Figure 21. Typical Connection Diagram

ANALOG INPUT

The analog input of the AD7452 is fully differential. Differential signals have a number of benefits over single-ended signals, including noise immunity based on the device’s common-mode rejection, improvements in distortion performance, doubling of the device’s available dynamic range, and flexibility in input ranges and bias points. Figure 22 defines the fully differential analog input of the AD7452.

REF

p-p

REF

COMMON-

MODE

VOLTAGE

p-p

Figure 22. Differential Input Definition

The amplitude of the differential signal is the difference between the signals applied to the V (i.e., V signals, each of amplitude V

IN+

– V

IN–

). V

IN+

and V

IN–

REF

amplitude of the differential signal is therefore –V peak-to-peak (i.e., 2 ×V

). This is true regardless of the

REF

common mode (CM).

IN+

AD7452

IN–

IN+

and V

IN–

pins

are simultaneously driven by two

, that are 180° out of phase. The

to +V

REF

µC/µP

03154-A-022

REF

03154-A-021

The common mode is the average of the two signals, i.e., (V

+ V

IN+

)/2, and is therefore the voltage upon which the two

IN–

inputs are centered. This results in the span of each input being CM ± V range varies with V

/2. This voltage has to be set up externally, and its

REF

. As the value of V

REF

increases, the

REF

common-mode range decreases. When driving the inputs with an amplifier, the actual common-mode range is determined by the amplifier’s output voltage swing.

Figure 23 and Figure 24 show how the common-mode range typically varies with V

for both 5 V and 3 V power supplies.

REF

The common mode must be in this range to guarantee the functionality of the AD7452.

For ease of use, the common mode can be set up to equal V resulting in the differential signal being ±V

centered on V

REF

When a conversion takes place, the common mode is rejected, resulting in a virtually noise-free signal of amplitude, –V

, corresponding to the digital codes of 0 to 4096.

REF

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

COMMON-MOD E VOLTAGE (V)

0.5

0 0.5 1.0 1.5 2.0 2.5

Figure 23. Input Common-Mode Range vs. V

2.5

2.0

1.5

1.0

COMMON-MODE VOLTAGE (V)

0.5

0 0.25 0.50 0.75 1.00 1.25

Figure 24. Input Common-Mode Range vs. V

COMMON-MODE RANGE

= 5 V and V

COMMON-MODE RANGE

= 3 V and V

(V)

REF

(Max) = 3.5 V)

REF

(V)

REF

(Max) = 2 V)

REF

3.0 3.5

REF

1.50 2.00

1.75

REF

3.25V

1.75V

REF

03154-A-023

03154-A-024

Rev. B | Page 14 of 28

AD7452

www.BDTIC.com/ADI

Figure 25 shows examples of the inputs to V different values of V

for VDD = 5 V. It also gives the maximum

REF

IN+

and V

IN–

for

and minimum common-mode voltages for each reference value according to Figure 23.

REFERENCE = 2V

COMMON-MODE (CM)

= 1V

MIN

= 4V

MAX

REFERENCE = 2.5V

= 1.25V

MIN

= 3.75V

MAX

Figure 25. Examples of the Analog Inputs to V

Different Values of V

IN–

IN+

IN–

IN+

for VDD = 5 V

REF

2V p-p

2.5V p-p

IN+

and V

03154-A-025

for

IN–

Analog Input Structure

Figure 26 shows the equivalent circuit of the analog input structure of the AD7452. The four diodes provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. This causes these diodes to become forward-biased and start conducting into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the part. The capacitors, C1 in Figure 26, are typically 4 pF and can primarily be attributed to pin capacitance. The resistors are lumped components made up of the on resistance of the switches. The value of these resistors is typically about 100 Ω. The capacitors C2 are the ADC’s sampling capacitors and have a typical capacitance of 16 pF.

IN+

For ac applications, removing high frequency components from the analog input signal through the use of an RC low-pass filter on the relevant analog input pins is recommended. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application.

When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD increases as the source impedance increases, and performance degrades. Figure 27 shows a graph of the THD versus the analog input signal frequency for different source impedances for V

TA = 25°C

= 5V

–20

–40

THD (dB)

–60

–80

–100

10 100

RIN = 10Ω

INPUT FREQUENCY (kHz)

Figure 27. THD vs. Analog Input Frequency for Various

Source Impedances for V

RIN= 510Ω

RIN = 1kΩ

= 5 V

RIN = 300Ω

= 5 V.

277

03154-A-027

Figure 28 shows a graph of the THD versus the analog input frequency for V

of 5 V ± 5% and 3 V +20%/–10%, while

sampling at 555 kSPS with an SCLK of 10 MHz. In this case, the source impedance is 10 Ω.

–50

TA = 25°C

–55

–60

IN–

Figure 26. Equivalent Analog Input Circuit

Conversion Phase—Switches Open; Track Phase—Switches Closed

03154-A-026

–65

–70

THD (dB)

–75

–80

–85

–90

10 100

Figure 28. THD vs. Analog Input Frequency for 3 V and 5 V Supply Voltages

Rev. B | Page 15 of 28

VDD = 3.6V

VDD = 4.75V

INPUT FREQUENCY (kHz)

VDD = 2.7V

VDD = 5.25V

03154-A-028

277

AD7452

www.BDTIC.com/ADI

DRIVING DIFFERENTIAL INPUTS

Differential operation requires that V ously driven with two equal signals that are 180° out of phase. The common mode must be set up externally and has a range determined by V

, the power supply, and the particular ampli-

REF

fier used to drive the analog inputs (see Figure 23 and Figure 24). Differential modes of operation with either an ac or a dc input provide the best THD performance over a wide frequency range. Since not all applications have a signal preconditioned for differential operation, there is often a need to perform single-ended-to-differential conversion.

Differential Amplifier

An ideal method of applying differential drive to the AD7452 is to use a differential amplifier such as the AD8138. This part can be used as a single-ended-to-differential amplifier or as a differential-to-differential amplifier. In both cases, the analog input needs to be bipolar. It also provides common-mode level shifting and buffering of the bipolar input signal. Figure 29 shows how the AD8138 can be used as a single-ended-todifferential amplifier. The positive and negative outputs of the AD8138 are connected to the respective inputs on the ADC via

IN+

and V

+2.5V

GND

–2.5V

be simultane-

IN–

51Ω

RG2

OCM

RF1

AD8138

RF2

a pair of series resistors to minimize the effects of switched capacitance on the front end of the ADCs. The RC low-pass filter on each analog input is recommended in ac applications to remove high frequency components of the analog input. The architecture of the AD8138 results in outputs that are very highly balanced over a wide frequency range without requiring tightly matched external components. If the analog input source being used has zero impedance, all four resistors (R R

2) should be the same. If, for example, the source has a 50 Ω

impedance and a 50 Ω termination, the value of R

1, RG2, RF1,

2 should be

increased by 25 Ω to balance this parallel impedance on the input and thus ensure that both the positive and negative analog inputs have the same gain (see Figure 29). The outputs of the amplifier are perfectly matched, balanced differential outputs of identical amplitude, and are exactly 180° out of phase.

The AD8138 is specified with +3 V, +5 V, and ±5 V power supplies, but the best results are obtained when it is supplied by ±5 V. The AD8132 is a lower cost device that could also be used in this configuration with slight differences in characteristics to the AD8138 but with similar performance and operation.

3.75V

2.5V

RS*

IN+

IN–

1.25V

AD7452

3.75V

2.5V

1.25V

REF

*MOUNT AS CLOSE TO THE AD7452 AS POSSIBLE AND ENSURE HIGH PRECISION Rs AND Cs ARE USED.

–50Ω; C–1nF

1 = RF1 = RF2 = 499Ω; RG2 = 523Ω

Figure 29. Using the AD8138 as a Single-Ended-to-Differential Amplifier

Rev. B | Page 16 of 28

EXTERNAL V

(2.5V)

REF

03154-A-029

AD7452

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Op Amp Pair

An op amp pair can be used to directly couple a differential signal to the AD7452. The circuit configurations shown in Figure 30 and Figure 31 show how a dual op amp can be used to convert a single-ended signal into a differential signal for both a bipolar and unipolar input signal, respectively.

The voltage applied to Point A sets up the common-mode voltage. In both diagrams, it is connected in some way to the reference, but any value in the common-mode range can be input here to set up the common mode. The AD8022 is a suitable dual op amp that could be used in this configuration to provide differential drive to the AD7452.

Care must be taken when choosing the op amp because the selection depends on the required power supply and the system performance objectives. The driver circuits in Figure 30 and Figure 31 are optimized for dc coupling applications that require optimum distortion performance.

The differential op amp driver circuit in Figure 30 is configured to convert and level shift a single-ended, ground-referenced (bipolar) signal to a differential signal centered at the V

REF

level

of the ADC.

The circuit configuration shown in Figure 31 converts a unipolar, single-ended signal into a differential signal.

220Ω

2 × V

p-p

GND

REF

390Ω

220Ω

V+

27Ω

V–

220Ω 220Ω

V+

27Ω

V–

IN+

IN–

AD7452

REF

0.1µF

220Ω

2 × V

p-p

REF

GND

REF

390Ω

V+

27Ω

V–

220Ω 220Ω

V+

10kΩ

27Ω

V–

IN+

IN–

AD7452

EXTERNAL

REF

0.1µF

REF

Figure 31. Dual Op Amp Circuit to Convert a Single-Ended

Unipolar Signal into a Differential Signal

RF Transformer

In systems that do not need to be dc-coupled, an RF transformer with a center tap offers a good solution for generating differential inputs. Figure 32 shows how a transformer is used for single-ended-to-differential conversion. It provides the benefits of operating the ADC in the differential mode without contributing additional noise and distortion. An RF transformer also has the benefit of providing electrical isolation between the signal source and the ADC. A transformer can be used for most ac applications. The center tap is used to shift the differential signal to the common-mode level required; in this case, it is connected to the reference so the common-mode level is the value of the reference.

3.75V

2.5V

1.25V

IN+

3.75V

2.5V

1.25V

AD7452

IN–

REF

03154-A-031

20kΩ

Figure 30. Dual Op Amp Circuit to Convert a Single-Ended

10kΩ

EXTERNAL

REF

03154-A-030

Figure 32. Using an RF Transformer to Generate Differential Inputs

Bipolar Signal into a Differential Signal

Rev. B | Page 17 of 28

EXTERNAL V

(2.5 V)

REF

03154-A-032

AD7452

www.BDTIC.com/ADI

DIGITAL INPUTS

The digital inputs applied to the AD7452 are not limited by the maximum ratings, which limit the analog limits. Instead the digital inputs applied, i.e., not restricted by the V

The main advantage of the inputs being unrestricted to the V

+ 0.3 V limit is that power supply sequencing issues are

avoided. If

and SCLK are applied before VDD, there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 V was applied prior to V

REFERENCE

An external reference source is required to supply the reference to the AD7452. This reference input can range from 100 mV to

3.5 V. With a 5 V power supply, the specified reference is 2.5 V and the maximum reference is 3.5 V. With a 3 V power supply, the specified reference is 2 V and the maximum reference is

2.2 V. In both cases, the reference is functional from 100 mV.

It is important to ensure that when choosing the reference value for a particular application, the maximum analog input range (V

max) is never greater than VDD + 0.3 V to comply with the

maximum ratings of the device. The following two examples calculate the maximum V operating the AD7452 at a V

Example 1

VIN max = VDD + 0.3 V

max = V

= 5 V, then VIN max = 5.3 V.

If V

Therefore 3 × V

REF

max = 3.5 V

REF

Thus, when operating at V from 100 mV to a maximum value of 3.5 V. When V

max = 3.17 V.

REF

Example 2

VIN max = VDD + 0.3 V

max = V

If V

= 3 V, then VIN max = 3.3 V.

Therefore 3 × V

REF

max = 2.2 V

REF

Thus, when operating at V from 100 mV to a maximum value of 2.2 V. When V

max = 2 V.

REF

+ V

REF

/2 = 5.3 V

+ V

REF

/2 = 3.3 V

and SCLK, can go to 7 V and are

+ 0.3 V limits as on the analog input.

input that can be used when

REF

of 5 V and 3 V, respectively.

REF

= 5 V, the value of V

REF

= 3 V, the value of V

REF

can range

= 4.75 V,

can range

= 2.7 V,

These examples show that the maximum reference applied to the AD7452 is directly dependent on the value applied to V

. The value of the reference sets the analog input span and the common-mode voltage range. Errors in the reference source result in gain errors in the AD7452 transfer function and add to specified full-scale errors on the part. A 0.1 µF capacitor should be used to decouple the V

Figure 33 shows a typical connection diagram for the V

10nF 0.1µF 0.1µF0.1µF

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 33. Typical V

pin to GND.

REF

AD780

TEMP

GND

NC = NO CONNECT

Connection Diagram for VDD = 5 V

REF

OPSEL

OUT

TRIM

8 7

2.5V

6 5

NC NC

REF

AD7452*

pin.

REF

Table 5. Examples of Suitable Voltage References

Reference

Output Voltage (V)

Initial Accuracy (%)

Operating Current (µA)

AD780 2.5/3 0.04 1000 ADR421 2.5 0.04 500 ADR420 2.048 0.05 500

SINGLE-ENDED OPERATION

When supplied with a 5 V power supply, the AD7452 can handle a single-ended input. The design of this part is optimized for differential operation, so with a single-ended input, performance degrades. Linearity degrades by 0.2 LSB typically, the full-scale errors degrade by 1 LSB typically, and ac performance is not guaranteed.

To operate the AD7452 in single-ended mode, the V coupled to the signal source, while the V

input is biased to the

IN–

appropriate voltage corresponding to the midscale code transition. This voltage is the common mode, which is a fixed dc voltage (usually the reference). The V

input swings around

IN+

this value and should have a voltage span of 2 × V use of the full dynamic range of the part. The input signal therefore has peak-to-peak values of common mode ± V the analog input is unipolar, an op amp in a noninverting unity gain configuration can be used to drive the V

IN+

the ADC operates from a single supply, it is necessary to level shift ground-based bipolar signals to comply with the input requirements. An op amp can be configured to rescale and level shift the ground-based bipolar signal so it is compatible with the selected input range of the AD7452 (see Figure 34).

input is

IN+

to make

REF

pin. Because

. If

03154-A-033

Rev. B | Page 18 of 28

AD7452

–

www.BDTIC.com/ADI

2.5V 0V

2.5V

Figure 34. Applying a Bipolar Single-Ended Input to the AD7452

0.1µF

EXTERNAL

(2.5V)

REF

2.5V

IN+

AD7452

IN–

REF

03154-A-034

SERIAL INTERFACE

Figure 2 shows a detailed timing diagram for the serial interface of the AD7452. The serial clock provides the conversion clock and also controls the transfer of data from the device during conversion. data transfer. The falling edge of into hold mode and takes the bus out of three-state. The analog input is sampled and the conversion is initiated at this point. The conversion requires 16 SCLK cycles to complete.

Once 13 SCLK falling edges have occurred, the track-and-hold goes back into track on the next SCLK rising edge, as shown at Point B in Figure 2. On the 16 line goes back into three-state. If the rising edge of before 16 SCLKs have elapsed, the conversion is terminated and the SDATA line goes back into three-state.

The conversion result from the AD7452 is provided on the SDATA output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream of the AD7452 consists of four leading zeros followed by 12 bits of conversion data provided MSB first. The output coding is twos complement.

Sixteen serial clock cycles are required to perform a conversion and access data from the AD7452. first leading zero to be read in by the microcontroller or DSP.

initiates the conversion process and frames the

puts the track-and-hold

SCLK falling edge, the SDATA

occurs

going low provides the

The remaining data is then clocked out on the subsequent SCLK falling edges beginning with the second leading zero. Thus, the first falling clock edge on the serial clock provides the second leading zero. The final bit in the data transfer is valid on

the 16

falling edge, having been clocked out on the previous

(15

) falling edge. Once the conversion is complete and the data has been accessed after the 16 clock cycles, it is important to ensure that before the next conversion is initiated, enough time is left to meet the acquisition, and quiet time specifications (see the Timing Example).

In applications with a slower SCLK, it may be possible to read in data on each SCLK rising edge, i.e., the first rising edge of SCLK after the and the 15

falling edge would have the leading zero provided

SCLK edge would have DB0 provided.

Timing Example

Having F

= 10 MHz and a throughput rate of 555 kSPS gives

SCLK

a cycle time of

1/Throughput = 1/555,000 = 1.8 µs

A cycle consists of

+ 12.5(1/F

Therefore, if t

= 10 ns

10 ns + 12.5(1/10 MHz) + t

This 540 ns satisfies the requirement of 290 ns for t

From Figure 35, t

comprises

ACQ

2.5(1/F

where t8 = 35 ns. This allows a value of 255 ns for t

SCLK

ACQ

SCLK

) + t

ACQ

= 540 ns

) + t8 + t

= 1.8 µs

ACQ

QUIET

ACQ.

QUIET

satisfying the minimum requirement of 60 ns.

SCLK

10ns

12345 13141516

12.5(1/F

Figure 35. Serial Interface Timing Example

SCLK

CONVERT

)

1/THROUGHPUT

ACQUISITION

Rev. B | Page 19 of 28

QUIET

03154-A-035

AD7452

www.BDTIC.com/ADI

MODES OF OPERATION

The mode of operation of the AD7452 is selected by controlling the logic state of the two possible modes of operation, normal and power-down. The point at which initiated determines whether or not the AD7452 enters the power-down mode. Similarly, if already in power-down, controls whether the device returns to normal operation or remains in power-down. These modes of operation are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for differing application requirements.

NORMAL MODE

This mode is intended for fastest throughput rate performance. The user does not have to worry about any power-up times with the AD7452 remaining fully powered up all the time. Figure 36 shows the general diagram of the AD7452’s operation in this mode. The conversion is initiated on the falling edge of described in the Serial Interface section. To ensure that the part remains fully powered up, SCLK falling edges have elapsed after the falling edge of

is brought high any time after the 10th SCLK falling edge, but before the 16 up but the conversion is terminated and SDATA goes back into three-state. Sixteen serial clock cycles are required to complete the conversion and access the complete conversion result. may idle high until the next conversion or may idle low until sometime prior to the next conversion. Once a data transfer is complete, i.e., whe n SDATA has returned to three-state, another conversion can be initiated after the quiet time, t elapsed by again bringing

SCLK

SDATA

signal during a conversion. There are

is pulled high after the conversion has been

must remain low until at least 10

SCLK falling edge, the part remains powered

, has

QUIET

low.

110

4 LEADING ZEROS + CONVERSION RESULT

Figure 36. Normal Mode Operation

, as

03154-A-036

POWER-DOWN MODE

This mode is intended for use in applications where slower throughput rates are required; either the ADC is powered down between each conversion, or a series of conversions may be performed at a high throughput rate and the ADC is then powered down for a relatively long duration between these bursts of several conversions. When the AD7452 is in powerdown mode, all analog circuitry is powered down. To enter power-down mode, the conversion process must be interrupted by bringing SCLK, and before the 10 Figure 37.

Once CS has been brought high in this window of SCLKs, the part enters power-down, the conversion that was initiated by the falling edge of three-state. The time from the rising edge of three-state enabled is never greater than t Specifications). If falling edge, the part remains in normal mode and does not power down. This avoids accidental power-down due to glitches on the

In order to exit this mode of operation and power up the AD7452 again, a dummy conversion is performed. On the falling edge of to power up as long as of the 10 elapsed and, as shown in Figure 38, valid data results from the next conversion.

If AD7452 again goes back into power-down. This avoids accidental power-up due to glitches on the burst of eight SCLK cycles while device may begin to power up on the falling edge of powers down on the rising edge of the 10

high anywhere after the second falling edge of

SCLK

SDATA

Figure 37. Entering Power-Down Mode

line.

SCLK. The device is fully powered up after 1 µs has

falling edge of SCLK, as shown in

is terminated, and SDATA goes back into

is brought high before the second SCLK

THREE-STATE

to SDATA

(refer to the Timing

03154-A-037

, the device begins to power up and continues

is held low until after the falling edge

is brought high before the 10th falling edge of SCLK, the

line or an inadvertent

is low. So although the

, it again

SCLK falling edge.

as long as it occurs before

Rev. B | Page 20 of 28

AD7452

www.BDTIC.com/ADI

POWER-UP TIME

The power-up time of the AD7452 is typically 1 µs, which means that with any SCLK frequency up to 10 MHz, one dummy cycle is always sufficient to allow the device to power up. Once the dummy cycle is complete, the ADC is fully powered up and the input signal will be acquired properly. The quiet time, t

, must still be allowed from the point at which

QUIET

the bus goes back into three-state after the dummy conversion

to the next falling edge of

When power supplies are first applied to the AD7452, the ADC may power up either in power-down mode or in normal mode. Because of this, it is best to allow a dummy cycle to elapse to ensure the part is fully powered up before attempting a valid conversion. Likewise, if the user wants the part to power up in power-down mode, the dummy cycle may be used to ensure the device is in power-down by executing a cycle such as the one shown in Figure 37.

When running at the maximum throughput rate of 555 kSPS, the AD7452 powers up and acquires a signal within ±0.5 LSB in one dummy cycle. When powering up from the power-down mode with a dummy cycle, as in Figure 38, the track-and-hold, which was in hold mode while the part was powered down, returns to track mode after the first SCLK edge the part receives after the falling edge of

. This is shown as Point A in

Figure 38.

Although at any SCLK frequency one dummy cycle is sufficient to power up the device and acquire V

, it does not necessarily

mean that a full dummy cycle of 16 SCLKs must always elapse to power up the device and acquire V

fully; 1 µs is sufficient to

power up the device and acquire the input signal.

For example, if a 5 MHz SCLK frequency is applied to the ADC, the cycle time is 3.2 µs (i.e., 1/(5 MHz) × 16). In one dummy cycle, 3.2 µs, the part is powered up and V

fully acquired.

However, after 1 µs with a 5 MHz SCLK, only five SCLK cycles would have elapsed. At this stage, the ADC is fully powered up and the signal acquired. So in this case, after the 10 time, t

SCLK falling edge and brought low again after a

, to initiate the conversion.

QUIET

PART BEGINS

SCLK

TO POWER UP

can be brought high

POWER-UP

10 16 1 10 16

Once supplies are applied to the AD7452, the power-up time is the same as that when powering up from power-down mode. It takes approximately 1 µs to power up fully if the part powers up in normal mode. It is not necessary to wait 1 µs before executing a dummy cycle to ensure the desired mode of operation. Instead, the dummy cycle can occur directly after power is supplied to the ADC. If the first valid conversion is performed directly after the dummy conversion, care must be taken to ensure that adequate acquisition time has been allowed.

As mentioned earlier, when powering up from the power-down mode, the part returns to track mode upon the first SCLK edge applied after the falling edge of

. However, when the ADC powers up initially after supplies are applied, the track-and-hold is already in track mode. This means if (assuming one has the facility to monitor the ADC supply current) the ADC powers up in the desired mode of operation, and thus a dummy cycle is not required to change the mode, and a dummy cycle is not required to place the track-and-hold into track mode.

THIS PART IS FULLY POWERED UP WITH V

FULLY ACQUIRED

SDATA

INVALID DATA VALID DATA

Figure 38. Exiting Power-Down Mode

Rev. B | Page 21 of 28

03154-A-038

AD7452

www.BDTIC.com/ADI

POWER VS. THROUGHPUT RATE

By using the power-down mode on the AD7452 when not converting, the average power consumption of the ADC decreases at lower throughput rates. Figure 39 shows how, as the throughput rate is reduced, the device remains in its power-down state longer and the average power consumption is reduced accordingly. It shows this for both 5 V and 3 V power supplies.

For example, if the AD7452 is operated in continuous sampling mode with a throughput rate of 100 kSPS and an SCLK of 10 MHz, and the device is placed in power-down mode between conversions, the power consumption is calculated as follows:

Power Dissipation during Normal Operation = 7.25 mW max (for V

= 5 V)

If the power-up time is one dummy cycle (1.06 µs if brought high after the 10

SCLK falling edge and then brought low after the quiet time) and the remaining conversion time is another cycle, i.e., 1.6 µs, the AD7452 can be said to dissipate

7.25 mW for 2.66 µs

∗

during each conversion cycle.

If the throughput rate = 100 kSPS, the cycle time = 10 µs and the average power dissipated during each cycle is

(2.66/10) × 7.25 mW = 1.92 mW

100

POWER (mW)

0.1

0.01 0 350

50 100 150 200 250 300

Figure 39. Power vs. Throughput Rate for Power-Down Mode

VDD = 5V

THROUGHPUT (kSPS)

= 3V

03154-A-039

MICROPROCESSOR AND DSP INTERFACING

The serial interface on the AD7452 allows the part to be directly connected to a range of different microprocessors. This section explains how to interface the AD7452 with some of the more common microcontroller and DSP serial interface protocols.

AD7452 to ADSP-21xx

The ADSP-21xx family of DSPs is interfaced directly to the AD7452 without any glue logic required.

For the same scenario, if V

= 3 V, the power dissipation during

normal operation is 3.3 mW max.

The AD7452 can now be said to dissipate 3.3 mW for 2.66 µs during each conversion cycle.

The average power dissipated during each cycle with a throughput rate of 100 kSPS is therefore

(2.66/10) × 3.3 mW = 0.88 mW

This is how the power numbers in Figure 39 are calculated.

For throughput rates above 320 kSPS, it is recommended that the serial clock frequency be reduced for optimum power performance.

∗

This figure assumes a very short time to enter power-down mode. This

increases as the burst of clocks used to enter the power-down mode is increased.

The SPORT control register should be set up as follows:

TFSW = RFSW = 1, Alternate Framing

∗

INVRFS = INVTFS = 1, Active Low Frame Signal DTYPE = 00, Right-Justify Data SLEN = 1111, 16-Bit Data-Words ISCLK = 1, Internal Serial Clock TFSR = RFSR = 1, Frame Every Word IRFS = 0 ITFS = 1

To implement power-down mode, SLEN should be set to 1001 to issue an 8-bit SCLK burst.

The connection diagram is shown in Figure 40. The ADSP-21xx has the TFS and RFS of the SPORT tied together, with TFS set as an output and RFS set as an input. The DSP operates in alternate framing mode and the SPORT control register is set up as described. The frame synchronization signal generated on the TFS is tied to

and, as with all signal processing applications, equidistant sampling is necessary. However in this example, the timer interrupt is used to control the sampling rate of the ADC; under certain conditions, equidistant sampling may not be achieved.

Rev. B | Page 22 of 28

AD7452

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AD7452*

SCLK

SDATA

*ADDITIONAL PINS REMOVED FOR CLARITY

Figure 40. Interfacing to the ADSP-21xx

ADSP-21xx*

SCLK DR

RFS TFS

The timer registers, for example, are loaded with a value that provides an interrupt at the required sample interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS and therefore the reading of data. The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given (i.e., AX0 = TX0), the state of the SCLK is checked. The DSP waits until the SCLK has gone high, low, and high again before the transmission starts. If the timer and SCLK values are chosen such that the instruction to transmit occurs on or near the rising edge of SCLK, the data may be transmitted or it may wait until the next clock edge.

For example, the ADSP-2111 has a master clock frequency of 16 MHz. If the SCLKDIV register is loaded with the value 3, an SCLK of 2 MHz is obtained and eight master clock periods elapse for every SCLK period. If the timer registers are loaded with the value 803, 100.5 SCLKs occur between interrupts and subsequently between transmit instructions. This situation results in nonequidistant sampling because the transmit instruction is occurring on an SCLK edge. If the number of SCLKs between interrupts is a whole integer figure of N, equidistant sampling is implemented by the DSP.

AD7452 to TMS320C5x/C54x

The serial interface on the TMS320C5x/C54x uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the AD7452. The

input allows easy interfacing between the TMS320C5x/C54x and the AD7452 without any glue logic required. The serial port of the TMS320C5x/C54x is set up to operate in burst mode with internal CLKx (Tx serial clock) and FSx (Tx frame sync). The serial port control register (SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1, and TxM = 1. The format bit, FO, may be set to 1 to set the word length to eight bits in order to implement the power-down mode on the AD7452. The connection diagram is shown in Figure 41. It should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the TMS320C5x/C54x provides equidistant sampling.

AD7452*

SCLK

SDATA

03154-A-040

*ADDITIONAL PINS REMOVED FOR CLARITY

Figure 41. Interfacing to the TMS320C5x/C54x

AD7452 to DSP56xxx

The connection diagram in Figure 42 shows how the AD7452 can be connected to the SSI (synchronous serial interface) of the DSP56xxx family of DSPs from Motorola. The SSI is operated in synchronous mode (SYN bit in CRB = 1) with internally generated 1-word frame sync for both Tx and Rx (Bits FSL1 = 0 and FSL0 = 0 in CRB). Set the word length to 16 by setting Bits WL1 = 1 and WL0 = 0 in CRA. To implement power-down mode on the AD7452, the word length can be changed to eight bits by setting Bits WL1 = 0 and WL0 = 0 in CRA. It should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the DSP56xxx provides equidistant sampling.

AD7452*

SCLK

SDATA

*ADDITIONAL PINS REMOVED FOR CLARITY

Figure 42. Interfacing to the DSP56xxx

TMS320C5x/

C54x*

CLKx CLKR DR

FSx FSR

DSP56xxx*

SCLK SRD

SR2

03154-A-041

03154-A-042

Rev. B | Page 23 of 28

AD7452

www.BDTIC.com/ADI

APPLICATION HINTS

Grounding and Layout

The printed circuit board that houses the AD7452 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should be joined in only one place, a star ground point established as close as possible to the GND pin on the AD7452. Avoid running digital lines under the device because this couples noise onto the die. The analog ground plane should be allowed to run under the AD7452 to avoid noise coupling. The power supply lines to the AD7452 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line.

Fast switching signals like clocks should be shielded with digital g

round to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board.

In this technique, the component side of the board is dedicated to g

round planes while signals are placed on the solder side. Good decoupling is also important. All analog supplies should be decoupled with 10 µF tantalum capacitors in parallel with

0.1 µF capacitors to GND. To achieve the best from these decoupling components, place them as close to the device as possible.

EVALUATING THE AD7452’S PERFORMANCE

The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the evaluation board controller. The evaluation board controller can be used in conjunction with the AD7452 evaluation board, as well as many other Analog Devices evaluation boards ending with the CB designator, to demonstrate/evaluate the ac and dc performance of the AD7452.

The software allows the user to perform ac (fast Fourier tra

nsform) and dc (histogram of codes) tests on the AD7452. For more information, see the AD7452 application note that accompanies the evaluation kit.

Rev. B | Page 24 of 28

AD7452

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OUTLINE DIMENSIONS

2.90 BSC

1.95 BSC

5 6

0.65 BSC

2.80 BSC

1.45 MAX

SEATING PLANE

0.22

0.08 8°

4° 0°

0.60

0.45

0.30

1.60 BSC

PIN 1

1.30

1.15

0.90

0.15 MAX

84 7

0.38

0.22

COMPLIANT TO JEDEC STANDARDS MO-178BA

Figure 43. 8-Lead Small Outline Transistor Package [SOT-23]

(RT-8)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Linearity Error (LSB)

Package Option

AD7452BRT-R2 –40°C to +85°C ± 1 RT-8 C07 AD7452BRT-REEL7 –40°C to +85°C ± 1 RT-8 C07 EVAL-AD7452CB EVAL-CONTROL BRD2

Evaluation Board Controller Board

Branding

Linearity error here refers to integral nonlinearity error.

RT = SOT-23.

This can be used as a standalone evaluation board or in conjunction with the evaluation board controller for evaluation/demonstration purposes.

Evaluation board controller. This board is a complete unit allowing a PC to control and communicate with all Analog Devices’ evaluation boards ending in the CB

designator. For a complete evaluation kit, you need to order the ADC evaluation board, i.e., EVAL-AD7452CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See the see the AD7452 application note that accompanies the evaluation kit for more information.

Rev. B | Page 25 of 28

AD7452

www.BDTIC.com/ADI

NOTES

Rev. B | Page 26 of 28

AD7452

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NOTES

Rev. B | Page 27 of 28

AD7452

www.BDTIC.com/ADI

NOTES

C03154–0–2/04(B)

Rev. B | Page 28 of 28

ANALOG DEVICES AD7452 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

AD7452–SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TERMINOLOGY

AD7452–TYPICAL PERFORMANCE CHARACTERISTICS

CIRCUIT INFORMATION

CONVERTER OPERATION

ADC TRANSFER FUNCTION

TYPICAL CONNECTION DIAGRAM

ANALOG INPUT

Analog Input Structure

DRIVING DIFFERENTIAL INPUTS

Differential Amplifier

Op Amp Pair

RF Transformer

DIGITAL INPUTS

REFERENCE

Example 1

Example 2

SINGLE-ENDED OPERATION

SERIAL INTERFACE

Timing Example

MODES OF OPERATION

NORMAL MODE

POWER-DOWN MODE

POWER-UP TIME

POWER VS. THROUGHPUT RATE

MICROPROCESSOR AND DSP INTERFACING

AD7452 to ADSP-21xx

AD7452 to TMS320C5x/C54x

AD7452 to DSP56xxx

APPLICATION HINTS

Grounding and Layout

EVALUATING THE AD7452’S PERFORMANCE

OUTLINE DIMENSIONS

ORDERING GUIDE