ANALOG DEVICES AD7451 Service Manual

Pseudo Differential Input, 1 MSPS,

V

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FEATURES

Fast throughput rate: 1 MSPS Specified for V Low power at maximum throughput rate:

4 mW maximum at 1 MSPS with V

9.25 mW maximum at 1 MSPS with V Pseudo differential analog input Wide input bandwidth:

70 dB SINAD at 100 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface:

SPI®-/QSPI™-/M Power-down mode: 1 μA maximum 8-lead SOT-23 and MSOP packages

APPLICATIONS

Transducer interface Battery-powered systems Data acquisition systems Portable instrumentation

of 2.7 V to 5.25 V

DD

= 3 V

DD

ICROWIRE™-/DSP-compatible

= 5 V

10-/12-Bit ADCs in an 8-Lead SOT-23

AD7441/AD7451

FUNCTIONAL BLOCK DIAGRAM

DD

V

IN+

V

IN–

V

REF

AD7441/AD7451

T/H

GND

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

CONTRO L LO GIC

Figure 1.

SCLK

SDATA

CS

03153-001

GENERAL DESCRIPTION

The AD7441/AD74511 are, respectively, 10-/12-bit high speed, low power, single-supply, successive approximation (SAR), analog-to-digital converters (ADCs) that feature a pseudo differential analog input. These parts operate from a single

2.7 V to 5.25 V power supply and achieve very low power dissipation at high throughput rates of up to 1 MSPS.

The AD7441/AD7451 contain a low noise, wide bandwidth, dif

ferential track-and-hold (T/H) amplifier that handles input frequencies up to 3.5 MHz. The reference voltage for these devices is applied externally to the V 100 mV to V

, depending on the power supply and what suits

DD

the application.

The conversion process and data acquisition are controlled

CS

and the serial clock, allowing the device to interface

g

usin with microprocessors or DSPs. The input signals are sampled on the falling edge of

CS

when the conversion is initiated. The SAR architecture of these parts ensures that there are no pipeline delays.

1

Protected by U.S. Patent Number 6,681,332.

pin and can range from

REF

PRODUCT HIGHLIGHTS

1. Operation with 2.7 V to 5.25 V Power Supplies.

2. H

igh Throughput with Low Power Consumption. With a 3 V supply, the AD7441/AD7451 offer 4 mW maximum power consumption for a 1 MSPS throughput rate.

3. P

seudo Differential Analog Input.

4. F

lexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the power to be reduced as the conversion time is reduced through the serial clock speed increase. These parts also feature a shutdown mode to maximize power efficiency at lower throughput rates.

5. V

ariable Voltage Reference Input.

6. No

Pipeline Delays.

ccurate Control of Sampling Instant via

7. A

Once-Off Conversion Control.

8. EN

OB > 10 Bits Typically with 500 mV Reference.

CS

Input and

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD7441/AD7451

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REVISION HISTORY

3/07—Rev. B to Rev. C

Changes to Table 5.................................................................................9

Updated Layout....................................................................................12

Changes to Terminology Section.......................................................12

Updated Outline Dimensions............................................................23

Changes to Ordering Guide...............................................................24

2/05—Rev. A to Rev. B

C

hanges to Ordering Guide...............................................................24

2/04—Rev. 0 to Rev. A

pdated Format.....................................................................Universal

U

Changes to General Description .......................................................1

Changes to Table 1 Footnotes ............................................................ 4

Changes to Table 2 Footnotes ............................................................ 6

Changes to Table 3 Footnotes ............................................................ 7

Changes to Table 5 .............................................................................. 9

Updated Figures 7, 8, and 9.............................................................. 13

Changes to Figure 23.........................................................................16

Changes to Reference Section.......................................................... 17

9/03—Revision 0: Initial Version

Rev. C | Page 2 of 24

AD7441/AD7451

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SPECIFICATIONS

VDD = 2.7 V to 5.25 V; f versions: −40°C to +85°C.

Table 1. AD7451

Parameter Test Conditions/Comments A Version B Version Unit

DYNAMIC PERFORMANCE fIN = 100 kHz

Signal-to-Noise Ratio (SNR)1 VDD = 2.7 V to 5.25 V 70 70 dB min Signal-to-(Noise + Distortion) (SINAD)1 VDD = 2.7 V to 3.6 V 69 69 dB min V Total Harmonic Distortion (THD) V Peak Harmonic or Spurious Noise V Intermodulation Distortion (IMD)1 fa = 90 kHz; fb = 110 kHz

Second-Order Terms −80 −80 dB typ

Third-Order Terms −80 −80 dB typ Aperture Delay Aperture Jitter

1

Full-Power Bandwidth @ −0.1 dB 2.5 2.5 MHz typ

DC ACCURACY

Resolution 12 12 Bits Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Offset Error Gain Error

1

ANALOG INPUT

Full-Scale Input Span V Absolute Input Voltage

V

IN+

3

V

VDD = 2.7 V to 3.6 V −0.1 to +0.4 −0.1 to +0.4 V

IN–

V

DC Leakage Current ±1 ±1 μA max Input Capacitance When in track-and-hold 30/10 30/10 pF typ

REFERENCE INPUT

V

Input Voltage

REF

DC Leakage Current ±1 ±1 μA max V

Input Capacitance When in track-and-hold 10/30 10/30 pF typ

REF

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, IIN Typically 10 nA, VIN = 0 V or VDD ±1 ±1 μA max Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, VOH VDD = 4.75 V to 5.25 V; I

V

Output Low Voltage, VOL I Floating-State Leakage Current ±1 ±1 μA max Floating-State Output Capacitance Output Coding

= 18 MHz; fS = 1 MSPS; V

SCLK

1

= 4.75 V to 5.25 V 70 70 dB min

DD

VDD = 2.7 V to 3.6 V; −78 dB typ −73 −73 dB max

= 4.75 V to 5.25 V; −80 dB typ −75 −75 dB max

DD

VDD = 2.7 V to 3.6 V; −80 dB typ −73 −73 dB max

= 4.75 V to 5.25 V; −82 dB typ −75 −75 dB max

DD

= 2.5 V; TA = T

REF

MIN

to T

, unless otherwise noted. Temperature ranges for A, B

MAX

5 5 ns typ 50 50 ps typ

1, 2

@ −3 dB 20 20 MHz typ

1

±1.5 ±1 LSB max Guaranteed no missed codes to 12 bits ±0.95 ±0.95 LSB max ±3.5 ±3.5 LSB max ±3 ±3 LSB max

− V

V

IN+

IN–

= 4.75 V to 5.25 V −0.1 to +1.5 −0.1 to +1.5 V

DD

4

2.4 2.4 V min

INH

0.8 0.8 V max

INL

5

IN

±1% tolerance for specified performance 2.5 2.5 V

10 10 pF max

= 200 μA 2.8 2.8 V min

SOURCE

= 2.7 V to 3.6 V; I

DD

= 200 μA 0.4 0.4 V max

SINK

5

10 10 pF max

= 200 μA 2.4 2.4 V min

SOURCE

V

REF

V

REF

Straight

tural) binary

(na

V

REF

V

REF

Straight (natural) binary

Rev. C | Page 3 of 24

AD7441/AD7451

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Test Conditions/Comments A Version B Version Unit Parameter

CONVERSION RATE

Conversion Time 888 ns with an 18 MHz SCLK 16 16 SCLK cycles Track-and-Hold Acquisition Time1 Sine wave input 250 250 ns max

Full-scale step input 290 290 ns max

Throughput Rate 1 1 MSPS max

POWER REQUIREMENTS

VDD 2.7/5.25 2.7/5.25 V min/max

6, 7

I

DD

Normal Mode (Static) SCLK on or off 0.5 0.5 mA typ Normal Mode (Operational) VDD = 4.75 V to 5.25 V 1.95 1.95 mA max

V

Full Power-Down Mode SCLK on or off 1 1 μA max

Power Dissipation

Normal Mode (Operational) VDD = 5 V; 1.55 mW typical for 100 ksps69.25 9.25 mW max V Full Power-Down VDD = 5 V; SCLK on or off 5 5 μW max

V

1

See Terminology section.

2

Analog inputs with slew rates exceeding 27 V/μs (full-scale input sine wave > 3.5 MHz) within the acquisition time can cause the converter to return an incorrect result.

3

A small dc input is applied to V

4

The AD7451 is functional with a reference input in the range of 100 mV to VDD.

5

Guaranteed by characterization.

6

See the Power vs. Throughput Rate section.

7

Measured with a full-scale dc input.

to provide a pseudo ground for V

IN–

= 2.7 V to 3.6 V 1.45 1.45 mA max

DD

= 3 V; 0.6 mW typical for 100 ksps

DD

= 3 V; SCLK on or off 3 3 μW max

DD

.

IN+

6

4 4 mW max

Rev. C | Page 4 of 24

AD7441/AD7451

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VDD = 2.7 V to 5.25 V; f B version: −40°C to +85°C.

Table 2. AD7441

Parameter Test Conditions/Comments B Version Unit

DYNAMIC PERFORMANCE fIN = 100 kHz

Signal-to-(Noise + Distortion) (SINAD)1 61 dB min Total Harmonic Distortion (THD)

4.75 V to 5.25 V; −79 dB typical −73 dB max Peak Harmonic or Spurious Noise

4.75 V to 5.25 V; −82 dB typical −74 dB max Intermodulation Distortion (IMD)1 fa = 90 kHz, fb = 110 kHz

Second-Order Terms −80 dB typ

Third-Order Terms −80 dB typ Aperture Delay

1

Aperture Jitter1 50 ps typ Full-Power Bandwidth1, 2 @ −3 dB 20 MHz typ

@ −0.1 dB 2.5 MHz typ DC ACCURACY

Resolution 10 Bits Integral Nonlinearity (INL)1 ±0.5 LSB max Differential Nonlinearity (DNL) Offset Error Gain Error

1

ANALOG INPUT

Full-Scale Input Span V Absolute Input Voltage

V

IN+

3

V

VDD = 2.7 V to 3.6 V −0.1 to +0.4 V

IN–

V DC Leakage Current ±1 μA max Input Capacitance When in track-and-hold 30/10 pF typ

REFERENCE INPUT

V

Input Voltage

REF

DC Leakage Current ±1 μA max V

Input Capacitance When in track-and-hold 10/30 pF typ

REF

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, IIN Typically 10 nA, VIN = 0 V or VDD ±1 μA max Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, VOH VDD = 4.75 V to 5.25 V; I

V

Output Low Voltage, VOL I Floating-State Leakage Current ±1 μA max Floating-State Output Capacitance Output Coding Straight (natural) binary

= 18 MHz; fS = 1 MSPS; V

SCLK

1

2.7 V to 3.6 V; −77 dB typical −72 dB max

2.7 V to 3.6 V; −80 dB typical −72 dB max

= 2.5 V; TA = T

REF

MIN

to T

, unless otherwise noted. Temperature range for

MAX

5 ns typ

1

Guaranteed no missed codes to 10 bits ±0.5 LSB max ±1 LSB max ±1 LSB max

− V

V

IN+

IN–

= 4.75 V to 5.25 V −0.1 to +1.5 V

DD

4

2.4 V min

INH

0.8 V max

INL

5

10 pF max

IN

±1% tolerance for specified performance 2.5 V

= 200 μA 2.8 V min

SOURCE

= 2.7 V to 3.6 V; I

DD

= 200 μA 0.4 V max

SINK

5

10 pF max

= 200 μA 2.4 V min

SOURCE

V

REF

V

REF

Rev. C | Page 5 of 24

AD7441/AD7451

www.BDTIC.com/ADI

Test Conditions/Comments B Version Unit Parameter

CONVERSION RATE

Conversion Time 888 ns with an 18 MHz SCLK 16 SCLK cycles Track-and-Hold Acquisition Time Step input 290 ns max Throughput Rate 1 MSPS max

POWER REQUIREMENTS

VDD 2.7/5.25 V min/max

6, 7

I

DD

Normal Mode (Static) SCLK on or off 0.5 mA typ Normal Mode (Operational) VDD = 4.75 V to 5.25 V 1.95 mA max V Full Power-Down Mode SCLK on or off 1 μA max

Power Dissipation

Normal Mode (Operational) VDD = 5 V; 1.55 mW typ for 100 ksps V Full Power-Down VDD = 5 V; SCLK on or off 5 μW max

V

1

See the Terminology section.

2

Analog inputs with slew rates exceeding 27 V/μs (full-scale input sine wave > 3.5 MHz) within the acquisition time can cause the converter to return an incorrect result.

3

A small dc input is applied to V

4

The AD7441 is functional with a reference input in the range 100 mV to VDD.

5

Guaranteed by characterization.

6

See the Power vs. Throughput Rate section.

7

Measured with a full-scale dc input.

IN–

1

Sine wave input 250 ns max

= 2.7 V to 3.6 V 1.25 mA max

DD

= 3 V; 0.6 mW typ for 100 ksps

DD

= 3 V; SCLK on or off 3 μW max

DD

to provide a pseudo ground for V

6

.

IN+

9.25 mW max 4 mW max

Rev. C | Page 6 of 24

AD7441/AD7451

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TIMING SPECIFICATIONS

VDD = 2.7 V to 5.25 V; f

Table 3.

Parameter Limit at T

f

SCLK

CONVER T

t

QUIET

t1 t2

3

t

3

2

10 kHz min

18 MHz max

16 × t

888 ns max 60 ns min 10 ns min 10 ns min

20 ns max t4 40 ns max Data access time after SCLK falling edge t5 0.4 t t6 0.4 t t7 10 ns min SCLK edge to data valid hold time

4

t

8

t

POWER-UP

1

Guaranteed by characterization. All input signals are specified with t

and the Serial Interface section.

2

Mark/space ratio for the SCLK input is 40/60 to 60/40.

3

Measured with the load circuit of Figure 4 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V and the time required for an output to

cross 0.4 V or 2.0 V for VDD = 3 V.

4

t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then extrapolated

10 ns min SCLK falling edge to SDATA, three-state enabled

35 ns max SCLK falling edge to SDATA, three-state enabled

5

1 μs max Power-up time from full power-down

back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time (t8) quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.

5

See the Power-Up Time section.

SCLK

MIN

SCLK

ns min SCLK high pulse width

SCLK

ns min SCLK low pulse width

SCLK

1

= 18 MHz; fS = 1 MSPS; V

, T

Unit Description

MAX

t

Minimum quiet time between end of a serial read and next falling edge of CS Minimum CS CS Delay from CS

= 2.5 V; TA = T

REF

= 1/f

SCLK

t

MIN

to T

, unless otherwise noted.

MAX

pulse width

falling edge to SCLK falling edge setup time

falling edge until SDATA three-state disabled

= t

= 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See Figure 2, Figure 3,

RISE

FALL

TIMING DIAGRAMS

CS

SCLK

SDATA

CS

t

SCLK

t

SDATA

t

2

12345 13141516

t

3

0 0 0 0 DB11 DB10 DB2 DB1 DB0

4 LEADING ZE ROS THREE-STATE

t

4

CONVERT

t

5

t

7

B

Figure 2. AD7451 Serial Interface Timing Diagram

t

CONVERT

2

12345 13141516

3

0 0 0 0 DB9 DB8 DB0 0 0

4 LEADING Z EROS 2 TRAILING ZEROS THREE-STAT E

t

4

t

5

t

7

B

Figure 3. AD7441 Serial Interface Timing Diagram

t

1

t

6

t

6

t

8

t

QUIET

03153-002

t

1

t

8

t

QUIET

03153-003

Rev. C | Page 7 of 24

AD7441/AD7451

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND −0.3 V to +7 V V

to GND −0.3 V to VDD + 0.3 V

IN+

V

to GND −0.3 V to VDD + 0.3 V

IN–

Digital Input Voltage to GND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to VDD + 0.3 V V

to GND −0.3 V to VDD + 0.3 V

REF

Input Current to any Pin Except Supplies1±10 mA Operating Temperature Range

Commercial (A, B Version) Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 205.9°C/W (MSOP)

θJC Thermal Impedance 43.74°C/W (MSOP)

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C ESD 1 kV

1

Transient currents of up to 100 mA do not cause SCR latch-up.

−40°C to +85°C

211.5°C/W (SOT-23)

91.99°C/W (SOT-23)

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

1.6mA I

TO OUTPUT

C

L

25pF

200µA I

Figure 4. Load Circuit for Digital Out

OL

1.6V

OH

put Timing Specifications

03153-004

ESD CAUTION

Rev. C | Page 8 of 24

ANALOG DEVICES AD7451 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION