Analog Devices AD7450 Datasheet

Differential Input, 1 MSPS

FEATURES Fast Throughput Rate: 1 MSPS Specified for V Low Power at Max Throughput Rate:

3.75 mW Max at 833 kSPS with 3 V Supplies

9 mW Max at 1 MSPS with 5 V Supplies Fully Differential Analog Input Wide Input Bandwidth:

70 dB SINAD at 300 kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High-Speed Serial Interface—SPI

MICROWIRETM/DSP Compatible Power-Down Mode: 1 A Max 8-Lead SOIC and SOIC Packages

APPLICATIONS Transducer Interface Battery-Powered Systems Data Acquisition Systems Portable Instrumentation Motor Control Communications

of 3 V and 5 V

/QSPI

12-Bit ADC in SOIC-8 and SO-8

AD7450

FUNCTIONAL BLOCK DIAGRAM

IN+

IN–

REF

T/H

AD7450

GND

12-BIT SUCCESSIVE

APPROXIMATION

ADC

CONTROL

LOGIC

SCLK

SDATA

GENERAL DESCRIPTION

The AD7450 is a 12-bit, high-speed, low power, successive approximation (SAR) analog-to-digital converter that features a

differential analog input. It operates from a single 3 V or 5 V

fully

supply and features throughput rates up to 833 kSPS or

power 1 MSPS,

This part contains a low noise, wide bandwidth, differential track

respectively.

and-hold amplifier (T/H) that can handle input frequencies in excess of 1 MHz with the –3 dB point typically being 20 MHz. The reference voltage for the AD7450 is applied externally to the V

pin and can be varied from 100 mV to 3.5 V, depending

REF

on the power supply and what suits the application. The value of the

reference voltage determines the common-mode voltage

range of

the part. With this truly differential input structure and variable reference input, the user can select a variety of input ranges and bias points.

The conversion and data acquisition processes are controlled

CS and the serial clock, allowing the device to interface

using with microprocessors or DSPs. The input signals are sampled

falling edge of CS, and the conversion is also initiated at

on the this point.

The SAR architecture of this part ensures that there are no pipeline delays.

SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation.

The AD7450 uses advanced design techniques to achieve low power dissipation at high throughput rates.

PRODUCT HIGHLIGHTS

1. Operation with either 3 V or 5 V power supplies.

2. High throughput with low power consumption. With a 3 V supply, the AD7450 offers 3.75 mW max power consumption for 833 kSPS throughput.

3. Fully differential analog input.

4. Flexible power/serial clock speed management. The conversion rate is determined by the serial clock, allowing the power to be reduced as the conversion time is reduced through the serial clock speed increase. This part also features a shutdown mode to maximize power efficiency at lower throughput rates.

5. Variable voltage reference input.

6. No pipeline delay.

7. Accurate control of the sampling instant via a CS input and once-off conversion control.

8. ENOB > 8 bits typically with 100 mV reference.

REV. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002

AD7450–SPECIFICATIONS

= 4.75 V to 5.25 V, f

Parameter Conditions/Comments A Version B Version Unit

DYNAMIC PERFORMANCE

Signal-to-(Noise + Distortion) Ratio VDD = 5 V 70 70 dB min (SINAD)

Total Harmonic Distortion (THD)3VDD = 5 V, –80 dB typ –75 –75 dB max

Peak Harmonic or Spurious Noise

Intermodulation Distortion (IMD)

Second Order Terms –85 –85 dB typ

Third Order Terms –85 –85 dB typ Aperture Delay Aperture Jitter

Full Power Bandwidth

Power Supply Rejection Ratio

(PSRR)

3, 4

DC ACCURACY

Resolution 12 12 Bits Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

Zero Code Error

Positive Gain Error

Negative Gain Error

ANALOG INPUT

Full-Scale Input Span 2 ⫻ V Absolute Input Voltage

IN+

IN–

DC Leakage Current ± 1 ± 1 µA max Input Capacitance When in Track 20 20 pF typ

REFERENCE INPUT

Input Voltage 5 V supply (±1% tolerance for

REF

DC Leakage Current ± 1 ± 1 µA max V

Input Capacitance 15 15 pF typ

REF

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I

Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, V

Output Low Voltage, V Floating-State Leakage Current ± 1 ± 1 µA max Floating-State Output Capacitance Output Coding Two’s Two’s

= 18 MHz, fS = 1 MSPS, V

SCLK

INH

INL

VDD = 3 V 68 68 dB min

V VDD = 5 V, –82 dB typ –75 –75 dB max VDD = 3 V, –80 dB typ –73 –73 dB max

@ –3 dB 20 20 MHz typ @ –0.1 dB 2.5 2.5 MHz typ

Guaranteed No Missed Codes to 12 Bits –1/+2 ± 1 LSB max VDD = 5 V ± 3 ± 3 LSB max V VDD = 5 V ± 3 ± 3 LSB max V VDD = 5 V ± 3 ± 3 LSB max VDD = 3 V ± 6 ± 6 LSB max

V V

When in Hold 6 6 pF typ

specified performance) 2.5 3 V supply (±1% tolerance for specified performance) 1.25

Typically 10 nA, V

VDD = 5 V, I V I

(VDD = 2.7 V to 3.3 V, f

= 2.5 V, FIN = 300 kHz; V

REF

= 3 V, –78 dB typ –73 –73 dB max

= 15 MHz, fS = 833 kSPS, V

SCLK

= V

REF

; TA = T

MIN

= 1.25 V, FIN = 200 kHz;

REF

to T

, unless otherwise noted.)

MAX

10 10 ns typ 50 50 ps typ

–87 –87 dB typ

± 2 ± 1 LSB max

= 3 V ± 6 ± 6 LSB max

= V

REF

– V

IN+

VCM ± V VCM ± V

IN–

/2 VCM ± V

REF

/2 VCM ± V

REF

IN+

2.5

1.25

– V

IN–

REF

/2 V /2 V

2.4 2.4 V min

0.8 0.8 V max

= 0 V or V

± 1 ± 1 µA max 10 10 pF max

= 200 µA 2.8 2.8 V min

= 3 V, I

= 200 µA 0.4 0.4 V max

SINK

SOURCE

= 200 µA 2.4 2.4 V min

SOURCE

10 10 pF max

Complement Complement

REV. 0–2–

AD7450

Parameter Conditions/Comments A Version B Version Unit

CONVERSION RATE

Conversion Time 888 ns with an 18 MHz SCLK 16 16 SCLK Cycles

1.07 µs with a 15 MHz SCLK Track-and-Hold Sine Wave Input 200 200 ns max Acquisition Time Throughput Rate

POWER REQUIREMENTS

10, 11

Normal Mode (Static) VDD = 3 V/5 V SCLK; ON or OFF 0.5 0.5 mA typ Normal Mode (Operational) V

Full Power-Down Mode SCLK ON or OFF 1 1 µA max

Power Dissipation

Normal Mode (Operational) V

Full Power-Down Mode VDD = 5 V; SCLK ON or OFF 5 5 µW max

NOTES

Temperature range is as follows: A and B Versions: –40°C to +85°C.

Common-mode voltage. The input signal can be centered on any choice of dc common-mode voltage as long as this value is in the range specified in Figures 8 and 9.

See Terminology section.

A 200 mV p-p sine wave, varying in frequency from 1 kHz to 200 kHz is coupled onto VDD. A 2.2 nF capacitor is used to decouple VDD to GND.

If the input spans of V

The AD7450 is functional with a reference input from 100 mV and for VDD = 5 V, the reference can range up to 3.5 V (see References section).

The AD7450 is functional with a reference input from 100 mV and for VDD = 3 V, the reference can range up to 2.2 V (see References section).

Sample tested @ 25°C to ensure compliance.

See Serial Interface section.

See Power Versus Throughput Rate section.

Measured with a midscale dc input.

3, 8

IN+

and V

are both V

IN–

VDD = 5 V 1 1 MSPS max VDD = 3 V 833 833 kSPS max

Range: 3 V ± 10%; 5 V ± 5% 3/5 3/5 V min/max

= 5 V; f

= 3 V; f

= 5 V; f

1.38 mW typ for 100 KSPS

VDD = 3 V; f

0.53 mW typ for 100 KSPS

= 1 MSPS 1.8 1.8 mA max

SAMPLE

= 833 kSPS 1.25 1.25 mA max

SAMPLE

= 1 MSPS; 9 9 mW max

SAMPLE

= 833 kSPS; 3.75 3.75 mW max

SAMPLE

VDD = 3 V; SCLK ON or OFF 3 3 µW max

, and they are 180° out of phase, the differential voltage is 2 ⫻ V

REF

REV. 0

–3–

AD7450

TIMING SPECIFICATIONS

= 18 MHz, fS = 1 MSPS, V

SCLK

Limit at T

REF

MIN

1, 2

= 2.5 V; V

, T

MAX

(VDD = 2.7 V to 3.3 V, f

= V

; TA = T

REF

MIN

= 15 MHz, fS = 833 kSPS, V

SCLK

to T

, unless otherwise noted.)

MAX

= 1.25 V; VDD = 4.75 V to 5.25 V,

REF

Parameter 3 V 5 V Unit Description

SCLK

50 50 kHz min 15 18 MHz max

CONVERT

16 ⫻ t

SCLK

16 ⫻ t

SCLK

= 1/f

SCLK

1.07 0.88 µs max SCLK = 15 MHz, 18 MHz

QUIET

POWER-UP

NOTES

Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

See Figure 1 and the Serial Interface section.

Common-mode voltage.

Mark/space ratio for the SCLK input is 40/60 to 60/40.

Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with V

0.4 V

or 2.0 V for VDD = 3 V.

t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t time of the part and is independent of the bus loading.

See Power-Up Time section.

Specifications subject to change without notice.

25 25 ns min Minimum Quiet Time between the End of a Serial Read and the Next

Falling Edge of

10 10 ns min Minimum CS Pulsewidth 10 10 ns min

Falling Edge to SCLK Falling Edge Setup Time 20 20 ns max Delay from CS Falling Edge until SDATA Three-State Disabled 40 40 ns max Data Access Time after SCLK Falling Edge

0.4 t

SCLK

0.4 t

SCLK

ns min SCLK High Pulsewidth

ns min SCLK Low Pulsewidth 10 10 ns min SCLK Edge to Data Valid Hold Time 10 10 ns min SCLK Falling Edge to SDATA Three-State Enabled 35 35 ns max SCLK Falling Edge to SDATA Three-State Enabled

11µs max Power-Up Time from Full Power-Down

= 5 V, and the time for an output to cross

, quoted in the timing characteristics is the true bus relinquish

SCLK

SDATA

CONVERT

1 2 345 13 161514

00 00DB11 DB10 DB2 DB1

4 LEADING ZEROS

Figure 1. Serial Interface Timing Diagram

DB0

THREE-STATE

QUIET

REV. 0–4–

AD7450

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted.)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to V

IN+

to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to V

IN–

Digital Input Voltage to GND . . . . . . . . –0.3 V to V

Digital Output Voltage to GND . . . . . –0.3 V to V

to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

REF

Input Current to Any Pin Except Supplies

. . . . . . . ±10 mA

Operating Temperature Range

Commercial (A and B Version) . . . . . . . . . –40

Storage Temperature Range . . . . . . . . . . . . –65

+ 0.3 V

C to +85oC

C to +150oC

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC

SOIC, µSOIC Package, Power Dissipation . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . 157°C/W (SOIC)

␪

. . . . . . . . . . . . . . . . . . . . . . . . . . . 205.9°C/W (µSOIC)

Thermal Impedance . . . . . . . . . . . . . . . . . 56°C/W (SOIC)

␪

. . . . . . . . . . . . . . . . . . . . . . . . . . . 43.74°C/W (µSOIC)

ORDERING GUIDE

Temperature Linearity Package Branding

Model Range Error (LSB)

AD7450AR –40°C to +85°C ± 2 LSB SO-8 AD7450AR AD7450ARM –40°C to +85°C ± 2 LSB RM-8 CPA AD7450BR –40°C to +85°C ± 1 LSB SO-8 AD7450BR AD7450BRM –40°C to +85°C ± 1 LSB RM-8 CPB EVAL-AD7450CB EVAL-CONTROL BRD2

NOTES

Linearity error here refers to integral nonlinearity error.

SO = SOIC; RM = µSOIC.

This can be used as a standalone evaluation board or in conjunction with the Evaluation Board Controller for evaluation/demonstration purposes.

Evaluation Board Controller ending in the CB designators. To order a complete evaluation kit, you will need to order the ADC evaluation board, i.e.. EVAL-AD7450CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See the AD7450 evaluation board technical note for more details.

. This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards

Evaluation Board

Controller Board

Lead Temperature, Soldering

Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . . 215

Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 kV

NOTES

Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Transient currents of up to 100 mA will not cause SCR latch up.

1.6V

OUTPUT

200A

50pF

200A

Figure 2. Load Circuit for Digital Output Timing Specifications

Option

Information

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the

WARNING!

AD7450 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended

avoid performance degradation or loss of functionality.

REV. 0

–5–

ESD SENSITIVE DEVICE

AD7450

PIN CONFIGURATION

REF

GND

IN+

IN–

AD7450

TOP VIEW

(Not to Scale)

SCLK

SDATA

PIN FUNCTION DESCRIPTION

Pin Number Mnemonic Function

REF

Reference Input for the AD7450. An external reference must be applied to this input. For a 5 V power supply, the reference is 2.5 V (±1%), and for a 3 V power supply, the reference is

1.25 V (± 1%) for specified performance. This pin should be decoupled to GND with a capacitor of at least 0.1 µF. See the References section for more details.

IN+

IN–

Positive Terminal for Differential Analog Input

Negative Terminal for Differential Analog Input

4 GND Analog Ground. Ground reference point for all circuitry on the AD7450. All analog input

signals and any external reference signal should be referred to this GND voltage.

5 CS Chip Select. Active low logic input. This input provides the dual function of initiating a

conversion on the AD7450 and framing the serial data transfer.

6 SDATA Serial Data. Logic output. The conversion result from the AD7450 is provided on this

output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists of four leading zeros followed by the 12 bits of conversion data that is provided MSB first. The output coding is two’s complement.

7 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part.

This clock input is also used as the clock source for the AD7450’s conversion process.

Power Supply Input. VDD is 3 V (± 10%) or 5 V (± 5%). This supply should be decoupled to GND with a 0.1 µF capacitor and a 10 µF tantalum capacitor.

REV. 0–6–

AD7450

TERMINOLOGY Signal-to-(Noise + Distortion) Ratio

This is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f

/2), excluding dc. The ratio is

dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by:

Signal–to–(Noise + Distortion) = (6.02 N + 1.76) dB

Thus, for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7450, it is defined as:

THD dB

()=

VVVVV

++++

223242526

log

where V1 is the rms amplitude of the fundamental and V2, V3,

, V5, and V6 are the rms amplitudes of the second to the sixth

harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to f

/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m and n = 0, 1, 2, or 3. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa – fb), while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa –2fb).

The AD7450 is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the second order terms are usually distanced in frequency from the original sine waves, while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs.

Aperture Delay

This is the amount of time from the leading edge of the sampling clock until the ADC actually takes the sample.

Aperture Jitter

This is the sample-to-sample variation in the effective point in time at which the actual sample is taken.

Full Power Bandwidth

The full power bandwidth of an ADC is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 0.1 dB or 3 dB for a full-scale input.

Common-Mode Rejection Ratio (CMRR)

The common-mode rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 200 mV p-p sine wave applied to the common-mode voltage of V

IN+

and V

of frequency fs:

IN–

CMRR dB Pf Pfs() log ( / )= 10

Pf is the power at the frequency f in the ADC output; Pfs is the

power at frequency fs in the ADC output.

Integral Nonlinearity (INL)

This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function.

Differential Nonlinearity (DNL)

This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.

Zero Code Error

This is the deviation of the midscale code transition (111...111

– V

to 000...000) from the ideal V

Positive Gain Error

IN+

(i.e., 0 LSB).

IN–

This is the deviation of the last code transition (011...110 to

011...111) from the ideal V

IN+

(i.e., +V

IN–

– 1 LSB),

REF

– V

after the zero code error has been adjusted out.

Negative Gain Error

This is the deviation of the first code transition (100...000 to

100...001) from the ideal V

IN+

(i.e., –V

IN–

+ 1 LSB), after

REF

– V

the zero code error has been adjusted out.

Track and Hold Acquisition Time

The track and hold acquisition time is the minimum time required for the track and hold amplifier to remain in track mode for its output to reach and settle to within 0.5 LSB of the applied input signal.

Power Supply Rejection Ratio (PSRR)

The power supply rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC V frequency f

PSRR dB log Pf /Pfs() ( )= 10

supply of

Pf is the power at frequency f in the ADC output; Pfs is the power at frequency fs in the ADC output.

REV. 0

–7–

AD7450–Typical Performance Characteristics

(Default Conditions: TA = 25C)

8192 POINT FFT

SAMPLE

–20

= 300kHz

SINAD = 71.7dB THD = –82.8dB

–40

PK NOISE = –85.3dB

–60

SNR – dBs

–80

= 1MSPS

8192 POINT FFT

SAMPLE

–20

= 300kHz

SINAD = 70.2dB THD = –82dB

–40

PK NOISE = –87.1dB

–60

SNR – dBs

–80

= 833kSPS

–63

–65

–67

–69

SINAD – dB

–71

VDD = 2.7V

VDD = 3.3V

–100

–120

050 500100 150 200 250 300 350 400 450

FREQUENCY – kHz

TPC 1. Dynamic Performance at 1 MSPS with VDD = 5 V

1.0

0.8

0.6

0.4

0.2

–0.2

–0.4

DNL ERROR – LSB

–0.6

–0.8

–1.0

0 1024 2048 3072 4096

CODE

TPC 4. Typical Differential Nonlinearity (DNL) V

= 5 V

–100

–120

050100 150 200 250 300 350

FREQUENCY – kHz

TPC 2. Dynamic Performance at 833 kSPS with V

1.0

0.8

0.6

0.4

0.2

–0.2

–0.4

DNL ERROR – LSB

–0.6

–0.8

–1.0

0 1024 2048 3072 4096

CODE

= 3 V

TPC 5. Typical Differential Nonlinearity (DNL) VDD = 3 V

–73

VDD = 4.75V

–75

10 100 1000

INPUT FREQUENCY – kHz

VDD = 5.25V

TPC 3. SINAD vs. Analog Frequency for Various Supply Voltages

1.0

0.8

0.6

0.4

0.2

–0.2

INL ERROR – LSB

–0.4

–0.6

–0.8

–1.0

0 1024 2048 3072 4096

CODE

TPC 6. Typical Integral Nonlinearity (INL) VDD = 5 V

1.0

0.8

0.6

0.4

0.2

–0.2

INL ERROR – LSB

–0.4

–0.6

–0.8

–1.0

0 1024 2048 3072 4096

CODE

TPC 7. Typical Integral Nonlinearity (INL) VDD = 3 V

1.0

REF

POSI TIVE DNL

NEGATIVE DNL

0.5

CHANGE IN DNL-LSB

–0.5

–1.0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

TPC 8. Change in DNL vs. Reference Voltage V

= 5 V

1.5

1.0

POSITIVE DNL

0.5

CHANGE IN DNL-LSB

–0.5

–1.0

0 0.6 1.2 1.8 2.4

NEGATIVE DNL

REF

TPC 9. Change in DNL vs. Reference Voltage VDD = 3.3 V*

REV. 0–8–

AD7450

1.5

1.0

REF

POSI TIVE INL

NEGATIVE INL

0.5

–0.5

CHANGE IN INL-LSB

–1.0

–1.5

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

TPC 10. Change in INL vs. Reference Voltage V

10,000

9,000

8,000

7,000

6,000

5,000

4,000

3,000

2,000

1,000

= 5 V

VIN = V

–

10,000 CONVERSIONS

= 1MSPS

2044 2046 2047 2048 20492045

10,000

CODES

CODE

TPC 13. Histogram of the Output Codes with a DC Input for V

= 5 V

2.0

1.5

1.0

0.5

CHANGE IN INL-LSB

–0.5

–1.0

–1.5

0 0.6 1.2 1.8 2.4

POSITIVE INL

NEGATIVE INL

REF

TPC 11. Change in INL vs. Reference Voltage V

10,000

9,000

8,000

7,000

6,000

5,000

4,000

3,000

2,000

1,000

= 3.3 V*

VIN = VIN– 10,000 CONVERSIONS

= 833kSPS

CODES

2044 2046 2047 2048 20492045

9,839

CODES

CODE

CODES

TPC 14. Histogram of the Output Codes with a DC Input for V

= 3 V

VDD = 5V

= 1MSPS

–1

–2

–3

–4

–5

–6

ZERO-CODE ERROR – LSB

–7

–8

–9

0.25 0.75 3.501.25 1.75 2.25 2.75 3.25

VDD = 3.3V

= 833kSPS

REF

TPC 12. Change in Zero-Code Error vs.

Reference Voltage VDD = 5 V and 3.3 V*

VDD = 3.3V

= 833kSPS

EFFECTIVE NUMBER OF BITS

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

VDD = 5V

= 1MSPS

REF

TPC 15. Change in ENOB vs. Reference Voltage VDD = 5 V and 3.3 V*

CMRR – dB

10 10,000100 1,000

VDD = 3V

FREQUENCY – kHz

= 5V

TPC 16. CMRR vs. Input Frequency for VDD = 5 V and 3 V

*See References section.

REV. 0

–9–

AD7450

CIRCUIT INFORMATION

The AD7450 is a fast, low power, single-supply, 12-bit successive approximation analog-to-digital converter (ADC). It can operate with a 5 V and 3 V power supply and is capable of throughput rates up to 1 MSPS and 833 kSPS when supplied with an 18 MHz or 15 MHz clock, respectively. This part requires an external reference to be applied to the V

pin, with the value

REF

of the reference chosen depending on the power supply and what suits the application.

When operated with a 5 V supply, the maximum reference that can be applied to the part is 3.5 V, and when operated with a 3 V supply, the maximum reference that can be applied to the part is 2.2 V. (See the References section.)

The AD7450 has an on-chip differential track-and-hold amplifier, a successive approximation (SAR) ADC, and a serial interface that is housed in either an 8-lead SOIC or µSOIC package. The serial clock input accesses data from the part and also provides the clock source for the successive approximation ADC. The AD7450 features a power-down option for reduced power consumption between conversions. The power-down feature is implemented across the standard serial interface as described in the Modes of Operation section.

CONVERTER OPERATION

The AD7450 is a successive approximation ADC based on capacitive DACs. Figures 3 and 4 show simplified schematics the ADC in acquisition and conversion phase, respectively.

two of

The ADC is comprised of control logic, a SAR, and two capacitive DACs. In Figure 3 (the acquisition phase), SW3 is closed and SW1 and SW2 are in Position A, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input.

CAPACITIVE

DAC

IN+

IN–

SW1

SW2

COMPARATOR

SW3

–

CONTROL

LOGIC

CAPACITIVE

DAC

Figure 3. ADC Acquisition Phase

When the ADC starts a conversion (Figure 4), SW3 will open and SW1 and SW2 will move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC’s output code. The output impedances of the sources driving the V

IN+

and V

pins must be matched; otherwise, the two inputs

IN–

will have different settling times, resulting in errors.

CAPACITIVE

DAC

IN+

IN–

A A

SW1

SW2

COMPARATOR

SW3

–

CONTROL

LOGIC

CAPACITIVE

DAC

Figure 4. ADC Conversion Phase

ADC TRANSFER FUNCTION

The output coding for the AD7450 is two’s complement. The designed code transitions occur at successive LSB values (i.e., 1 LSB, 2 LSB, and so on), and the LSB size is 2 ⫻ V

REF

/ 4096.

The ideal transfer characteristic of the AD7450 is shown in Figure 5.

011...111

011...110

000...001

000...000

111...111

ADC CODE

100...010

100...001

100...000

1LSB = 2  V

–V

+ 1LSB 0LSB +V

REF

/4096

REF

ANALOG INPUT

– V

)

IN+

IN–

REF

– 1LSB

Figure 5. Ideal Transfer Characteristics

TYPICAL CONNECTION DIAGRAM

Figure 6 shows a typical connection diagram for the AD7450 for both 5 V and 3 V supplies. In this setup, the GND pin is connected to the analog ground plane of the system. The V

REF

pin is connected to either a 2.5 V or a 1.25 V decoupled reference source, depending on the power supply, to set up the analog input range. The common-mode voltage has to be set up externally and is the value that the two inputs are centered on. For more details on driving the differential inputs and setting up the common mode, see the Driving Differential Inputs section. The conversion result for the ADC is output in a 16-bit word consisting of four leading zeros followed by the MSB of the 12-bit result. For applications where power consumption is of concern, the power-down mode should be used between conversions, or bursts of several conversions, to improve power performance. See Modes of Operation section.

REV. 0–10–

AD7450

REF

5.0

0.25 0.75 1.75 2.25 2.75 3.25 3.501.25

COMMON-MODE RANGE – V

4.5

2.0

1.5

1.0

0.5

3.5

2.5

4.0

3.0

COMMON-MODE RANGE

3.25V

1.75V

3V/5V SUPPLY

10F

0.1F

REF

p-p

CM*

IN+

AD7450

SCLK

SDATA

SERIAL INTERFACE

C/P

Figures 8 and 9 show how the common-mode range typically varies with V common mode must be in this range to guarantee the functionality of the AD7450.

For ease of use, the common mode can be set up to be equal to V on V rejected resulting in a virtually noise free signal of amplitude –V

p-p

REF

*CM = COMMON-MODE VOLTAGE

CM*

IN–

REF

1.25V/2.5V V

REF

0.1F

GND

Figure 6. Typical Connection Diagram

THE ANALOG INPUT

The analog input of the AD7450 is fully differential. Differential signals have a number of benefits over single-ended signals, including noise immunity based on the device’s common-mode rejection, improvements in distortion performance, doubling of the device’s available dynamic range, and flexibility in input ranges and bias points.

Figure 7 defines the fully differential analog input of the AD7450.

for both a 5 V and a 3 V power supply. The

REF

, resulting in the differential signal being ±V

REF

. When a conversion takes place, the common mode is

REF

to +V

corresponding to the digital codes of 0 to 4095.

REF

Figure 8. Input Common-Mode Range vs. V (VDD = 5 V and V

3.0

(Max) = 3.5 V)

REF

centered

REF

The amplitude of the differential signal is the difference between the signals applied to the V V amplitude V the differential signal is therefore –V (i.e., 2 ⫻ V The common mode is the average of the two signals, i.e., (V are centered on. This results in the span of each input being CM ± V range varies with V mon-mode range decreases. When driving the inputs with an amplifier, by the amplifier’s output voltage swing.

REV. 0

p-p

REF

IN+

AD7450

COMMON-MODE

VOLTA G E

p-p

REF

IN–

Figure 7. Differential Input Definition

IN+

and V

+ V

are simultaneously driven by two signals each of

IN–

that are 180° out of phase. The amplitude of

REF

). This is regardless of the common mode (CM).

REF

)/2, and is therefore the voltage that the two inputs

IN–

/2. This voltage has to be set up externally and its

REF

IN+

. As the value of V

pins (i.e., V

IN–

to +V

REF

increases, the com-

REF

the actual common-mode range will be determined

IN+

p-p

– V

IN–

2.5

2.0

1.5

1.0

COMMON-MODE RANGE – V

0.5

0.25 0.50 1.00 1.25 1.50 2.00 2.200.75 1.75

Figure 9. Input Common-Mode Range vs. V and V

(Max) = 2.2 V)

REF

Figure 10 shows examples of the inputs to V different values of V

COMMON-MODE RANGE

REF

REF (VDD

and V

for VDD = 5 V. It also gives the maxi-

REF

IN+

IN–

mum and minimum common-mode voltages for each reference value according to Figure 8.

–11–

= 3 V

for

AD7450

COMMON-MODE (CM)

MIN

MAX

MIN

MAX

= 0.625V

= 4.42V

= 1.25V = 3.75V

REFERENCE = 1.25V

REFERENCE = 2.5V

–

1.25V p-p



–

2.5V p-p



Figure 10. Examples of the Analog Inputs to V and V

for Different Values of V

IN–

for VDD = 5 V

REF

IN+

total harmonic will increase mance will degrade. the analog input signal frequency for different source impedances.

Analog Input Structure

Figure 11 shows the equivalent circuit of the analog input structure of the AD7450. The four diodes provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. This will cause these diodes to become forward biased and start conducting into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the part.

The capacitors, C1, in Figure 11 are typically 4 pF and can prima-

be attributed to pin capacitance. The resistors are lumped

rily components made up of the ON resistance of the switches. The value of these resistors is typically about 100 Ω. The capacitors, C2, are the ADC’s sampling capacitors and have a capacitance of 16 pF typically.

For ac applications, removing high-frequency components from

Figure 13 shows a graph of the THD versus the analog input frequency for V at 1 MSPS and 833 kSPS with a SCLK of 18 MHz and 15 MHz, respectively. In this case, the source impedance is 10 Ω.

the analog input signal is recommended by the use of an RC low-pass filter on the relevant analog input pins. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances will significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp will be a function of the particular application.

IN+

IN–

DRIVING DIFFERENTIAL INPUTS

Differential operation requires that V neously driven with two equal signals that are 180 The common mode must be set up externally and has a range that is determined by V

Figure 11. Equivalent Analog Input Circuit Conversion Phase—Switches Open Track Phase—Switches Closed

When no amplifier is used to drive the analog input, the source impedance should be limited to values lower than 1 kΩ. The maximum source

impedance will depend on the amount of

amplifier used to drive the analog inputs (see Figures 8 and 9). Differential modes of operation with either an ac or dc input provide the best THD performance over a wide frequency range. Since not all applications have a signal preconditioned for differential operation, there is often a need to perform singleended-to-differential conversion.

distortion (THD) that can be tolerated. The THD

as the source impedance increases and the perfor-

Figure 12 shows a graph of the THD versus

–70

TA = 25C

–72

–74

–76

THD – dBs

–78

–80

–82

10 1000100

INPUT FREQUENCY – kHz

VDD = 5V R

= 100

VDD = 3V

= 1k

VDD = 5V R

= 1k

VDD = 3V

= 100

Figure 12. THD vs. Analog Input Frequency for Various Source Impedances for VDD = 5 V and 3 V

of 5 V ± 5% and 3 V ± 10%, while sampling

–60

TA = 25C

–65

–70

–75

VDD = 3.3V

–80

THD – dBs

–85

–90

–95

10 1000100

VDD = 2.7V

VDD = 5.25V

INPUT FREQUENCY – kHz

VDD = 4.75V

Figure 13. THD vs. Analog Input Frequency for 3 V

10%

and 5 V ± 5% Supply Voltages

and V

IN+

, the power supply, and the particular

REF

be simulta-

IN–

out of phase.

REV. 0–12–

AD7450

Rf1

Rg1

51R

Rg2

OCM

AD8138

Rf2

+2.5V

GND

–2.5V

*MOUNT AS CLOSE TO THE AD7450 AS POSSIBLE AND ENSURE HIGH PRECISION Rs AND Cs ARE USED

Rs – 50R; C – 1nF; Rg1 = Rf1 = Rf2 = 499R; Rg2 = 523R

Figure 14. Using the AD8138 as a Single-Ended-to-Differential Amplifier

Differential Amplifier

An ideal method of applying differential drive to the AD7450 is to use a differential amplifier, such as the AD8138. This part can be used as a single-ended-to-differential amplifier or as a differentialto-differential amplifier. In both cases, the analog input needs to be bipolar. It also provides common-mode level shifting and buffering of the bipolar input signal. Figure 14 shows how the AD8138 can be used as a single-ended-to-differential amplifier. The positive and negative outputs of the AD8138 are connected to the respective inputs on the ADC via a pair of series resistors to minimize the effects of switched capacitance on the front end of the ADC. The RC low-pass filter on each analog input is recommended in ac applications to remove the high-frequency components of the analog input. The architecture of the AD8138 results in outputs that are highly balanced over a wide frequency range without requiring tightly matched external components.

If the analog input source being used has zero impedance then all four resistors (Rg1, Rg2, Rf1, and Rf2) should be the same. If the source has a 50 Ω impedance and a 50 Ω termination, for example, the value of Rg2 should be increased by 25 Ω to balance this parallel impedance on the input and thus ensure that both the positive and negative analog inputs have the same gain (see Figure 14). The outputs of the amplifier are perfectly matched, balanced differential outputs of identical amplitude and exactly 180

out

of phase.

The AD8138 is specified with 3 V, 5 V, and ±5 V power supplies, but the best results are obtained when it is supplied by ±5 V. A lower cost device that could also be used in this configuration with slight differences in characteristics to the AD8138, but with similar performance and operation, is the AD8132.

Op Amp Pair

An op amp pair can be used to directly couple a differential signal to the AD7450. The circuit configurations shown in Figures convert

15a and 15b show how a dual op amp can be used to

a single-ended signal into a differential signal for both a

bipolar and a unipolar input signal, respectively.

3.75V

2.5V

Rs*

1.25V

IN+

AD7450

Rs*

IN–

3.75V

2.5V

1.25V

EXTERNAL

REF

(2.5V)

The voltage applied to Point A sets up the common-mode voltage. In both diagrams, it is connected in some way to the reference, but any value in the common-mode range can be input here to set up the common mode. Examples of suitable dual op amps that could be used in this configuration to provide differential drive to the AD7450 are the AD8042, AD8056, and AD8022.

Care must be taken when choosing the op amp, since the selection will depend on the required power supply and the system performance objectives. The driver circuits in Figure 15a and Figure 15b are optimized for dc coupling applications requiring optimum distortion performance.

The differential op amp driver circuit in Figure 15a is configured to convert and level shift a single-ended, ground (bipolar) signal to a differential signal centered

referenced

at the V

REF

level

of the ADC.

GND

2  V

REF

p-p

390

220

20k

220

V+

27

V–

220

V+

V–

27

10k

IN+

IN–

AD7450

REF

EXTERNAL

REF

0.1F

Figure 15a. Dual Op Amp Circuit to Convert a

Single-Ended Bipolar Input into a Differential Input

REV. 0

–13–

AD7450

The circuit configuration shown in Figure 15b converts a unipolar,

Example 1:

single-ended signal into a differential signal.

VREF

GND

2  V

REF

p-p

390

220

V+

27

V–

220

V+

V–

27

10k

IN+

IN–

AD7450

REF

EXTERNAL

REF

0.1F

Therefore, when operating at VDD = 5 V, the value of V range from 100 mV to a maximum value of 3.5 V. When V

4.75 V, V

Example 2:

Figure 15b. Dual Op Amp Circuit to Convert a

Single-Ended Unipolar Input into a Differential Input

RF Transformer

In systems that do not need to be dc-coupled, an RF transformer with a center tap offers a good solution for generating differential inputs. Figure 16 shows how a transformer is used for singleended-to-differential conversion. It provides the benefits of operating the ADC in the differential mode without contributing additional noise and distortion. An RF transformer also has the benefit of providing electrical isolation between the signal source and the ADC. A transformer can be used for most ac applications. The center tap is used to shift the differential signal to the common-mode level required. In this case, it is connected to the reference so the common-mode level is the value of the reference.

3.75V

2.5V

1.25V

IN+

IN–

3.75V

2.5V

1.25V

AD7450

REF

Therefore, when operating at VDD = 3.3 V, the value of V can range from 100 mV to a maximum value of 2.4 V. When V

These examples show that the maximum reference applied to the AD7450 is directly dependant on the value of V

The performance of the part at different reference values is shown in TPC 8 to TPC 12 and in TPC 15. The value of the reference sets the analog input span and the common-mode voltage range. Errors in the reference source will result in gain errors in the AD7450 transfer function and will add to specified on the part. A capacitor of 0.1 µF should be used to the V references to be used that are available from Analog Devices, and Figure 17 shows a typical connection diagram for the V

Reference Voltage Accuracy (% Max) Current (A)

AD589 1.235 1.2–2.8 50 AD1580 1.225 0.08–0.8 50

EXTERNAL

(2.5V)

REF

Figure 16. Using an RF Transformer to Generate

REF192 2.5 0.08–0.4 45 REF43 2.5 0.06–0.1 600 AD780 2.5 0.04–0.2 1000

Differential Inputs

REFERENCES SECTION

An external reference source is required to supply the reference to the AD7450. This reference input can range from 100 mV to 3.5 V. With a 5 V power supply, the specified reference is 2.5 V and the maximum

reference is 3.5 V. With a 3.3 V power supply, the specified reference is 1.25 V and the maximum reference is 2.4 V. In both cases, the reference is functional from 100 mV. It is important to ensure that, when choosing the reference value for a particular application, the maximum analog input range (VIN max) is never greater than VDD + 0.3 V to comply with the maximum ratings of the part. The following two examples calculate the maximum V used when operating the AD7450 at V

of 5 V and 3.3 V, respectively.

input that can be

REF

max .=+03

IN DD

VVV

max =+ 2

IN REF REF

If V V

= 5

ThenV V

Therefore V V

REF

IN DD

VVV

IN REF REF

If V V

ThenV V

Therefore V V

REF

= 2.7 V, V

max .= 53

3253×=.

REF

max .= 35

max = 3.37 V.

REF

max .=+03

max =+ 2

= 33.

max .= 36

3236×=.

REF

max .= 24

max = 2 V.

REF

pin to GND. Table I lists examples of suitable voltage

REF

Table I. Examples of Suitable Voltage References

Output Initial Operating

AD780

10nF

0.1F

*ADDITIONAL PINS OMITTED FOR CLARITY

0.1F

Figure 17. Typical V

TEMP

GND

NC = NO CONNECT

Connection Diagram for VDD = 5 V

REF

O/P SEL

OUT

TRIM

REF

full-scale

decouple

REF

AD7450*

2.5V

can

REF

errors

pin.

REF

0.1F

REV. 0–14–

AD7450

–

SINGLE-ENDED OPERATION

When supplied with a 5 V power supply, the AD7450 can handle a single-ended input. The design of this part is optimized for differential operation, so with a single-ended input, performance will degrade. Linearity will typically degrade by 0.2 LSBs, zero code and full-scale errors will typically degrade by 2 LSBs, and ac performance is not guaranteed.

To operate the AD7450 in single-ended mode, the V coupled to the signal source, while the V

input is biased to the

IN–

input is

IN+

appropriate voltage corresponding to the midscale code transition. This voltage is the common mode, which is a fixed dc voltage (usually the reference). The V this value and should have voltage span of 2 ⫻ V

input swings around

IN+

to make use

REF

of the full dynamic range of the part. Therefore, the input signal will have peak-to-peak values of common mode ± V

REF

. If the analog input is unipolar then an op amp in a noninverting unity gain configuration can be used to drive the V

pin. Because

IN+

the ADC operates from a single supply, it is necessary to level shift ground based bipolar signals to comply with the input requirements. An op amp can be configured to rescale and level shift the ground based bipolar signal so it is compatible with the selected input range of the AD7450 (see Figure 18).

+2.5V

2.5V

–

2.5V

IN+

AD7450

IN–

REF

is valid on the 16th falling edge,

having been clocked out on the previous (15th) falling edge. Once the conversion is complete and the data has been accessed after the 16 clock cycles, it is important to ensure that before the next conversion is initiated, enough time is left to meet the acquisition and quiet time specifications (see timing examples). To achieve 1 MSPS with an 18 MHz clock for V

= 5 V, an 18 clock burst will perform the

conversion and leave enough time before the next conversion for the acquisition and quiet time. This is the same for achieving 833 kSPS with a 15 MHz clock for V

= 3 V.

In applications with a slower SCLK, it may be possible to read in data on each SCLK rising edge, i.e., the first rising edge of SCLK after the CS falling edge would have the leading zero provided and the 15th SCLK edge would have DB0 provided.

Timing Example 1

Having f

= 18 MHz and a throughput rate of 1 MSPS gives

SCLK

a cycle time of:

111000 000 1Throughput s==,, µ

A cycle consists of:

tft

12 5 1 1+

()

SCLK ACQ2

+=. µs

Therefore, if t2 = 10 ns then:

10 12 5 1 18 1ns MHz t s

tns

ACQ

()

= 296

This 296 ns satisfies the requirement of 200 ns for t Figure 20, t

is comprised of:

ACQ

+=. µ

ACQ

. From

EXTERNAL

(2.5V)

REF

0.1F

Figure 18. Applying a Bipolar Single-Ended Input to the AD7450

SERIAL INTERFACE

Figure 19 shows a detailed timing diagram for the serial interface of the AD7450. The serial clock provides the conversion clock and also controls the transfer of data from the AD7450 during

28.51f

()

where t8 = 35 ns. This allows a value of 122 ns for t fying the minimum requirement of 25 ns.

Timing Example 2

Having f

SCLK

a cycle time of:

11315 000 3 174Throughput s==,.µ

A cycle consists of:

++tt

SCLK

QUIET

, satis-

= 5 MHz and a throughput rate of 315 kSPS gives

conversion. CS initiates the conversion process and frames the

tft

12 5 1 3 174+

data transfer. The falling edge of CS puts the track-and-hold into hold mode and takes the bus out of three-state. The analog input is sampled and the conversion initiated at this point. The conversion will require 16 SCLK cycles to complete.

Once 13 SCLK falling edges have occurred, the track-and-hold will go back into track on the next SCLK rising edge as shown at Point B in Figure 19. On the 16th SCLK falling edge, the SDATA line will go back into three-state.

If the rising edge of CS occurs before 16 SCLKs have elapsed, the conversion will be terminated, and the SDATA line will go back into three-state. Sixteen serial

clock cycles are required to

perform a conversion and to access data from the AD7450. CS going low provides the first leading microcontroller or DSP. The remaining

zero to be read in by the

data is then clocked out on the subsequent SCLK falling edges beginning with the second leading zero. Thus, the first falling clock edge on the serial clock provides the second leading zero.

The final bit in the data transfer

Therefore if t2 is 10 ns then:

10 12 5 1 5 3 174ns MHz t s

tns

ACQ

This 664 ns satisfies the requirement of 200 ns for t Figure 20, t

28.51f

where t8 = 35 ns. This allows a value of 129 ns for t fying the minimum requirement of 25 ns.

As in this example and with other slower clock values, the signal may already be acquired before the conversion is complete, but it is still necessary to leave 25 ns minimum t sions. In Timing Example 2, the signal should be fully acquired at approximately Point C in Figure 20.

()

= 664

ACQ

()

SCLK

+=..µs

SCLK ACQ2

()

+=..µ

ACQ

is comprised of:

++tt

QUIET

. From

ACQ

, satis-

QUIET

between conver-

REV. 0

–15–

AD7450

CONVERT

SCLK

SDATA

SCLK

1 2 345 13 161514

00 0

4 LEADING ZEROS

DB11 DB10 DB2 DB1 DB0

QUIET

THREE-STATE

Figure 19. Serial Interface Timing Diagram

CONVERT

1 2 345 13 161514

12.5(1/f

10ns

SCLK

)

1/THROUGHPUT

ACQ

QUIET

Figure 20. Serial Interface Timing Example

MODES OF OPERATION

The mode of operation of the AD7450 is selected by controlling the logic state of the CS signal during a conversion. There are two possible modes of operation, normal mode and power-down mode. The point at which CS is pulled high after the conversion has been initiated will determine whether or not the AD7450 will enter the power-down mode. Similarly, if already in power-down, CS controls whether the device will return to normal operation or remain in power-down. These modes of operation are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for differing application requirements.

Normal Mode

This mode is intended for the fastest throughput rate performance. times since the

The user does not have to worry about any power-up

AD7450 is kept fully powered up. Figure 21

shows the general diagram of the operation of the AD7450 in this mode. The conversion is initiated on the falling edge of CS as described in the Serial Interface section. To ensure the part remains fully powered up, CS must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of CS.

If CS is brought high any time after the 10th SCLK falling edge, but before the 16th SCLK falling edge, the part will remain powered up, but the conversion will be terminated and SDATA will go back into three-state.

Sixteen serial clock cycles are required to complete the conversion and access the complete conversion result. CS may idle high until the next conversion or idle low until sometime prior to the next conversion. Once a data transfer is complete, i.e., when SDATA has returned to three-state, another conversion can be initiated after the quiet time, t

, has elapsed by again

QUIET

bringing CS low.

SCLK

SDATA

4 LEADING ZEROS AND CONVERSION RESULT

Figure 21. Normal Mode Operation

Power-Down Mode

This mode is intended for use in applications where slower throughput rates are required; either the ADC is powered down between each conversion or a series of conversions may be

formed at a high throughput rate, during which the ADC is

per powered several

down for a relatively long duration between these bursts of

conversions. When the AD7450 is in the power-down

mode, all analog circuitry is powered down. To enter power-down mode, the conversion process must be interrupted by bringing CS high anywhere after the second falling edge of SCLK and before the 10th falling edge of SCLK as shown in Figure 22.

REV. 0–16–

AD7450

track-andpowered edge the as Point A in Figure 23.

SCLK

Although at any SCLK frequency one dummy cycle is sufficient

SDATA

THREE-STATE

to power the device up and acquire V mean that a full dummy cycle of 16 SCLKs must always elapse to power up the device and acquire V

Figure 22. Entering Power-Down Mode

Once CS has been brought high in this window of SCLKs, the part will enter power-down, the conversion that was initiated by the falling edge of CS will be terminated, and SDATA will go back into three-state. The time from the rising edge of CS to SDATA three-state enabled will never be greater than t

(see

Timing Specifications). If CS is brought high before the second SCLK falling edge, the part will remain in normal mode and will not power down. This will avoid accidental power-down due to glitches on the CS line.

To exit this mode of operation and power the AD7450 up again, a dummy conversion is performed. On the falling edge of CS, the device will begin to power up and continue to power up as as CS is held low until after the falling edge of the 10th SCLK.

long

The device will be fully powered up after 1 µs has elapsed and, as shown in Figure 23, valid data will result from the next conversion.

If CS is brought high before the 10th falling edge of SCLK, the AD7450 will again go back into power-down. This avoids accidental power-up due to glitches on the CS line or an inadvertent burst of eight SCLK cycles while CS is low. So although the device may begin to power up on the falling edge of CS, it will again power down on the rising edge of CS as long as it occurs before the 10th SCLK falling edge.

Power-Up Time

The power-up time of the AD7450 is typically 1 µs, which means that with any frequency of SCLK up to 18 MHz, one dummy cycle will always be sufficient to allow the device to power up. Once the dummy cycle is complete, the ADC will be fully powered up and the input signal will be acquired properly. The quiet time,

, must still be allowed from the point at which the bus

QUIET

goes back into three-state after the dummy conversion to the next falling edge of CS.

When running at the maximum throughput rate of 1 MSPS, the AD7450 will power up and acquire a signal within ±0.5 LSB in one dummy cycle, i.e., 1 µs. When powering up from the

sufficient to power the device up and acquire the input signal.

For example, if a 5 MHz SCLK frequency was applied to the ADC, the cycle time would be 3.2 µs (i.e., 1/(5 MHz) ⫻ 16). In dummy cycle, 3.2 µs, the part would be powered up and V acquired fully. However, after 1 µs with a 5 MHz SCLK, only 5 SCLK cycles would have elapsed. At this stage, the ADC would be fully powered up and the signal acquired. So, in this case, the CS can be brought high after the 10th SCLK falling edge and brought low again after a time, t

When power supplies are first applied to the AD7450, the ADC may either power up in the power-down mode or normal mode. Because of this, it is best to allow a dummy cycle to elapse to ensure the part is fully powered up before attempting a valid conversion. Likewise, if the user wishes the part to power up in power-down mode, then the dummy cycle may be used to ensure the device is in power-down by executing a cycle such as that shown in Figure 22.

Once supplies are applied to the AD7450, the power-up time is the same as that when powering up from the power-down mode. It takes approximately 1 µs to power up fully if the part powers up in normal mode. It is not necessary to wait 1 µs before executing a dummy cycle to ensure the desired mode of operation. Instead, the dummy cycle can occur directly after power is supplied to the ADC. If the first valid conversion is then performed directly after the dummy conversion, care must be taken to ensure that adequate acquisition time has been allowed.

As mentioned earlier, when powering up from the power-down mode, the part will return to track upon the first SCLK edge applied after the falling edge of CS. However, when the ADC powers up initially after supplies are applied, the track-and-hold will already be in track. This means if (assuming one has the facility to monitor the ADC supply current) the ADC powers up in the desired mode of operation, and thus a dummy cycle is not required to change the mode, then a dummy cycle is not required to place the track-and-hold into track.

power-down mode with a dummy cycle, as in Figure 23, the

hold, which was in hold mode while the part was

down, returns to track mode after the first SCLK

part receives

after the falling edge of CS. This is shown

, it does not necessarily

fully; 1 µs will be

one

, to initiate the conversion.

QUIET

SCLK

SDATA

REV. 0

THE PART BEGINS TO POWER UP

POWER-UP

INVALID DATA

THE PART IS FULLY POWERED UP WITH V

116

Figure 23. Exiting Power-Down Mode

–17–

FULLY ACQUIRED

VA LID DATA

AD7450

POWER VERSUS THROUGHPUT RATE

By using the power-down mode on the AD7450 when not converting, the average power consumption of the ADC decreases

AD7450 to ADSP-21xx

The ADSP-21xx DSPs are interfaced directly to the AD7450

without any glue logic required. at lower throughput rates. Figure 24 shows how, as the throughput rate is reduced, the device remains in its power-down state longer, and the average power consumption reduces accordingly. It shows this for both 5 V and 3 V power supplies.

For example, if the AD7450 is operated in continuous sampling mode with a throughput rate of 100 kSPS and an SCLK of 18 MHz, and the device is placed in the power-down mode between conversions, then the power consumption is calculated as follows:

Power dissipation during normal operation = 9 mW max for VDD = 5 V.

If the power-up time is one dummy cycle, i.e., 1 µs, and the remaining conversion time is another cycle, i.e., 1 µs, then the AD7450 can be said to dissipate 9 mW for 2 µs* during each conversion cycle.

If the throughput rate = 100 kSPS, then the cycle time = 10 µs, and the average power dissipated during each cycle is:

(2/10) ⫻ 9 mW = 1.8 mW

For the same scenario, if V

= 3 V, the power dissipation

during normal operation is 3.75 mW max.

The AD7450 can now be said to dissipate 3.75 mW for 2 µs*

each conversion cycle.

during

The SPORT control register should be set up as follows:

TFSW = RFSW = 1, Alternate Framing

INVRFS = INVTFS = 1, Active Low Frame Signal

DTYPE = 00, Right Justify Data

SLEN = 1111, 16-Bit Data-Words

ISCLK = 1, Internal Serial Clock

TFSR = RFSR = 1, Frame Every Word

IRFS = 0

ITFS = 1

To implement the power-down mode, SLEN should be set to

1001 to issue an 8-bit SCLK burst.

The connection diagram is shown in Figure 25. The ADSP-21xx

has the TFS and RFS of the SPORT tied together, with TFS

set as an output and RFS set as an input. The DSP operates in

alternate framing mode and the SPORT control register is set

up as described. The frame synchronization signal generated on

the TFS is tied to CS and, as with all signal processing applica-

tions, equidistant sampling is necessary. However, in this example,

the timer interrupt is used to control the sampling rate of the

ADC

may not be achieved.

The average power dissipated during each cycle with a throughput rate of 100 kSPS is therefore:

(2/10) ⫻ 3.75 mW = 0.75 mW

This is how the power numbers in Figure 24 are calculated.

For throughput rates above 320 kSPS, it is recommended that the serial clock frequency is reduced for optimum power performance.

100

VDD = 5V SCLK = 18MHz

The timer registers are loaded with a value that provides an

interrupt at the required sample interval. When an interrupt is

POWER – mW

VDD = 3V SCLK = 15MHz

received, a value is transmitted with TFS/DT (ADC control word).

The TFS is used to control the RFS and hence the reading of

data. The frequency of the serial clock is set in the SCLKDIV

0.1

(i.e., AX0 = TX0), the state of the SCLK is checked. The DSP

will wait until the SCLK has gone High, Low, and High before

transmission will start. If the timer and SCLK values are chosen

0.01 0 350100 150 20050 250 300

THROUGHPUT – kSPS

Figure 24. Power vs. Throughput Rate for Power-Down Mode

MICROPROCESSOR AND DSP INTERFACING

The serial interface on the AD7450 allows the part to be directly connected to a range of different microprocessors. This section explains how to interface the AD7450 with some of the more common microcontroller and DSP serial interface protocols.

such that the instruction to transmit occurs on or near the rising edge of SCLK, then the data may be transmitted, or it may wait until the next clock edge.

For example, the ADSP-2111 has a master clock frequency of 16 MHz. If the SCLKDIV register is loaded with the value 3, then a SCLK of 2 MHz is obtained and eight master clock periods will elapse for every 1 SCLK period. If the timer registers are between tions. This situation will result in nonequidistant sampling as the transmit number of SCLKs

*This figure assumes a very small time to enter power-down mode. This will

increase as the burst of clocks used to enter the power-down mode is increased.

N, then equidistant

and, under certain conditions, equidistant sampling

AD7450*

SCLK

SDATA

*ADDITIONAL PINS OMITTED FOR CLARITY

ADSP-21xx*

SCLK

RFS

TFS

Figure 25. Interfacing to the ADSP-21xx

loaded with the value 803, then 100.5 SCLKs will occur interrupts and subsequently between transmit instruc-

instruction is occurring on a SCLK edge. If the

between interrupts is a whole integer figure of

sampling will be implemented by the DSP.

REV. 0–18–

AD7450

AD7450 to TMS320C5x/C54x

The serial interface on the TMS320C5x/C54x uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices, such as the AD7450.

The CS input allows easy interfacing between the

TMS320C5x/C54x and the AD7450 with no glue logic required. The serial burst mode

port of the TMS320C5x/C54x is set up to operate in

with internal CLKX (Tx serial clock) and FSX (Tx frame sync). The serial port control register (SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1,

and TXM = 1. The format bit, FO, may be set to 1 to set the word length to 8 bits in order to the AD7450. The connection signal processing applica synchronization signal

implement the power-down mode on

diagram is shown in Figure 26. For

tions, it is imperative that the frame

from the TMS320C5x/C54x provide equi-

AD7450 to DSP56xxx

The connection diagram in Figure 28 shows how the AD7450 can be connected to the SSI (synchronous serial interface) of the DSP56xxx family of DSPs from Motorola. The SSI is operated in synchronous mode (SYN bit in CRB = 1) with internally generated 1-bit clock period frame sync for both Tx and Rx (Bits FSL1 = 1 and FSL0 = 0 in CRB). Set the word length to 16 by setting Bits WL1 = 1 and WL0 = 0 in CRA. To implement can be CRA. It should be noted that for signal processing applications, from the

distant sampling.

AD7450*

SCLK

SDATA

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 26. Interfacing to the TMS320C5x/C54x

AD7450 to MC68HC16

The serial peripheral interface (SPI) on the MC68HC16 is configured for master mode (MSTR) = 1, clock polarity bit (CPOL) = 1, and clock phase bit (CPHA) = 0. The SPI is configured by writing to the SPI control register (SPCR)—see the 68HC16 user manual. The serial transfer will take place as a 16-bit operation when the SIZE bit in the SPCR register is set to SIZE = 1. To implement the power-down modes with an 8-bit transfer set SIZE = 0. A connection diagram is shown in Figure 27.

AD7450*

SCLK

TMS320C5x/C54x*

CLKX

CLKR

FSX

FSR

MC68HC16*

SCLK/PMC2

APPLICATION HINTS Grounding and Layout

The printed circuit board that houses the AD7450 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes since it gives the joined ground point established as close to the GND pin on the AD7450 as possible. Avoid running digital lines under the device, as this will couple noise onto the die. The analog ground plane should be allowed to run under the AD7450 to avoid noise coupling. The power supply lines to the AD7450 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line.

SDATA

MISO/PMC0

Fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the

SS/PMC3

board, and clock signals should never run near the analog inputs.

*ADDITIONAL PINS OMITTED FOR CLARITY

opposite other.

Figure 27. Interfacing to the MC68HC16

board. always possible with a double-sided board.

In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side.

Good decoupling is also important. All analog supplies should be decoupled with 10 µF tantalum capacitors in parallel with

0.1 µF capacitors to GND. To achieve the best from these decoupling components, they must be placed as close as possible to the device.

the power-down mode on the AD7450, the word length

changed to 8 bits by setting its WL1 = 0 and WL0 = 0 in

is imperative that the frame synchronization signal

DSP56xxx will provide equidistant sampling.

AD7450*

SCLK SCLK

SDATA SRD

*ADDITIONAL PINS OMITTED FOR CLARITY

DSP56xxx*

SR2

Figure 28. Interfacing to the DSP56xxx

best shielding. Digital and analog ground planes should be

in only one place, and the connection should be a star

Avoid crossover of digital and analog signals. Traces on

sides of the board should run at right angles to each

This reduces the effects of feedthrough through the

A microstrip technique is by far the best but is not

REV. 0

–19–

AD7450

EVALUATING THE AD7450 PERFORMANCE

The evaluation board package includes a fully assembled and tested evaluation board,

documentation, and software for controlling the board from a PC via the Evaluation Board Controller. The Evaluation Board Controller can be used in conjunction with the AD7450 evaluation board, as well as many

OUTLINE DIMENSIONS

Dimensions shown in millimeters and (inches)

8-Lead SOIC

(R-8)

5.00 (0.1969)

4.80 (0.1890)

4.00 (0.1575)

3.80 (0.1496)

COPLANARITY

0.25 (0.0098)

0.10 (0.0039)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

PIN 1

1.27 (0.0500)

0.49 (0.0193)

0.35 (0.0138)

BSC

6.20 (0.2441)

5.80 (0.2283)

1.75 (0.0689)

1.35 (0.0531)

SEATING PLANE

other Analog Devices evaluation boards ending with the CB designator, to demonstrate/evaluate the ac and dc performance of the AD7450.

The software allows the user to perform ac (fast Fourier Transform) and dc (Histogram of codes) tests on the AD7450. See the evaluation board technical note for more information.

0.25 (0.0098)

0.19 (0.0075)

0.50 (0.0197)

0.25 (0.0098)

8

1.27 (0.0500)

0

0.41 (0.0161)

 45

C02646–0–5/02(0)

0.122 (3.10)

0.114 (2.90)

0.006 (0.15)

0.002 (0.05)

SEATING

PLANE

Dimensions shown in inches and (mm)

8-Lead SOIC

(RM-8)

0.122 (3.10)

0.114 (2.90)

PIN 1

0.0256 (0.65) BSC

0.120 (3.05)

0.112 (2.84)

0.018 (0.46)

0.008 (0.20)

0.199 (5.05)

0.187 (4.75)

0.043 (1.09)

0.037 (0.94)

0.011 (0.28)

0.003 (0.08)

0.120 (3.05)

0.112 (2.84)

33 27

0.028 (0.71)

0.016 (0.41)

PRINTED IN U.S.A.

–20–

REV. 0

Analog Devices AD7450 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual