Analog Devices AD7450 Datasheet
Differential Input, 1 MSPS
a
FEATURES
Fast Throughput Rate: 1 MSPS
Specified for V
Low Power at Max Throughput Rate:
3.75 mW Max at 833 kSPS with 3 V Supplies
9 mW Max at 1 MSPS with 5 V Supplies
Fully Differential Analog Input
Wide Input Bandwidth:
70 dB SINAD at 300 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High-Speed Serial Interface—SPI
MICROWIRETM/DSP Compatible
Power-Down Mode: 1 A Max
8-Lead SOIC and SOIC Packages
APPLICATIONS
Transducer Interface
Battery-Powered Systems
Data Acquisition Systems
Portable Instrumentation
Motor Control
Communications
of 3 V and 5 V
DD
TM
/QSPI
TM
12-Bit ADC in SOIC-8 and SO-8
AD7450
FUNCTIONAL BLOCK DIAGRAM
V
DD
V
IN+
V
IN–
V
REF
T/H
AD7450
GND
12-BIT SUCCESSIVE
APPROXIMATION
ADC
CONTROL
LOGIC
SCLK
SDATA
CS
GENERAL DESCRIPTION
The AD7450 is a 12-bit, high-speed, low power, successive
approximation (SAR) analog-to-digital converter that features a
differential analog input. It operates from a single 3 V or 5 V
fully
supply and features throughput rates up to 833 kSPS or
power
1 MSPS,
This part contains a low noise, wide bandwidth, differential track
respectively.
and-hold amplifier (T/H) that can handle input frequencies in
excess of 1 MHz with the –3 dB point typically being 20 MHz.
The reference voltage for the AD7450 is applied externally to the
V
pin and can be varied from 100 mV to 3.5 V, depending
REF
on the power supply and what suits the application. The value of
the
reference voltage determines the common-mode voltage
range of
the part. With this truly differential input structure and
variable reference input, the user can select a variety of input
ranges and bias points.
The conversion and data acquisition processes are controlled
CS and the serial clock, allowing the device to interface
using
with microprocessors or DSPs. The input signals are sampled
falling edge of CS, and the conversion is also initiated at
on the
this point.
The SAR architecture of this part ensures that there are no
pipeline delays.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
The AD7450 uses advanced design techniques to achieve low
power dissipation at high throughput rates.
PRODUCT HIGHLIGHTS
1. Operation with either 3 V or 5 V power supplies.
2. High throughput with low power consumption. With a 3 V
supply, the AD7450 offers 3.75 mW max power consumption
for 833 kSPS throughput.
3. Fully differential analog input.
4. Flexible power/serial clock speed management. The conversion
rate is determined by the serial clock, allowing the power
to be reduced as the conversion time is reduced through
the serial clock speed increase. This part also features a
shutdown mode to maximize power efficiency at lower
throughput rates.
5. Variable voltage reference input.
6. No pipeline delay.
7. Accurate control of the sampling instant via a CS input and
once-off conversion control.
8. ENOB > 8 bits typically with 100 mV reference.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
AD7450–SPECIFICATIONS
V
= 4.75 V to 5.25 V, f
DD
Parameter Conditions/Comments A Version B Version Unit
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) Ratio VDD = 5 V 70 70 dB min
(SINAD)
3
Total Harmonic Distortion (THD)3VDD = 5 V, –80 dB typ –75 –75 dB max
Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)
Second Order Terms –85 –85 dB typ
Third Order Terms –85 –85 dB typ
Aperture Delay
Aperture Jitter
3
3
Full Power Bandwidth
Power Supply Rejection Ratio
(PSRR)
3, 4
DC ACCURACY
Resolution 12 12 Bits
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Zero Code Error
3
Positive Gain Error
Negative Gain Error
ANALOG INPUT
Full-Scale Input Span 2 ⫻ V
Absolute Input Voltage
V
IN+
V
IN–
DC Leakage Current ± 1 ± 1 µA max
Input Capacitance When in Track 20 20 pF typ
REFERENCE INPUT
V
Input Voltage 5 V supply (±1% tolerance for
REF
DC Leakage Current ± 1 ± 1 µA max
V
Input Capacitance 15 15 pF typ
REF
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
IN
Input Capacitance, C
LOGIC OUTPUTS
Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current ± 1 ± 1 µA max
Floating-State Output Capacitance
Output Coding Two’s Two’s
= 18 MHz, fS = 1 MSPS, V
SCLK
3
3
3
3
3
3
3
INH
INL
8
IN
OH
OL
8
VDD = 3 V 68 68 dB min
V
VDD = 5 V, –82 dB typ –75 –75 dB max
VDD = 3 V, –80 dB typ –73 –73 dB max
@ –3 dB 20 20 MHz typ
@ –0.1 dB 2.5 2.5 MHz typ
Guaranteed No Missed
Codes to 12 Bits –1/+2 ± 1 LSB max
VDD = 5 V ± 3 ± 3 LSB max
V
VDD = 5 V ± 3 ± 3 LSB max
V
VDD = 5 V ± 3 ± 3 LSB max
VDD = 3 V ± 6 ± 6 LSB max
V
V
When in Hold 6 6 pF typ
specified performance) 2.5
3 V supply (±1% tolerance for
specified performance) 1.25
Typically 10 nA, V
VDD = 5 V, I
V
I
(VDD = 2.7 V to 3.3 V, f
= 2.5 V, FIN = 300 kHz; V
REF
= 3 V, –78 dB typ –73 –73 dB max
DD
= 15 MHz, fS = 833 kSPS, V
SCLK
2
= V
REF
; TA = T
MIN
CM
= 1.25 V, FIN = 200 kHz;
REF
to T
, unless otherwise noted.)
MAX
10 10 ns typ
50 50 ps typ
–87 –87 dB typ
± 2 ± 1 LSB max
= 3 V ± 6 ± 6 LSB max
DD
= 3 V ± 6 ± 6 LSB max
DD
CM
CM
2
= V
2
= V
REF
5
REF
REF
V
– V
IN+
VCM ± V
VCM ± V
6
7
IN–
/2 VCM ± V
REF
/2 VCM ± V
REF
V
IN+
2.5
1.25
– V
IN–
REF
REF
6
7
V
/2 V
/2 V
V
V
2.4 2.4 V min
0.8 0.8 V max
= 0 V or V
IN
DD
± 1 ± 1 µA max
10 10 pF max
= 200 µA 2.8 2.8 V min
= 3 V, I
DD
= 200 µA 0.4 0.4 V max
SINK
SOURCE
= 200 µA 2.4 2.4 V min
SOURCE
10 10 pF max
Complement Complement
1
REV. 0–2–
AD7450
Parameter Conditions/Comments A Version B Version Unit
CONVERSION RATE
Conversion Time 888 ns with an 18 MHz SCLK 16 16 SCLK Cycles
1.07 µs with a 15 MHz SCLK
Track-and-Hold Sine Wave Input 200 200 ns max
Acquisition Time
Throughput Rate
POWER REQUIREMENTS
V
DD
10, 11
I
DD
Normal Mode (Static) VDD = 3 V/5 V SCLK; ON or OFF 0.5 0.5 mA typ
Normal Mode (Operational) V
Full Power-Down Mode SCLK ON or OFF 1 1 µA max
Power Dissipation
Normal Mode (Operational) V
Full Power-Down Mode VDD = 5 V; SCLK ON or OFF 5 5 µW max
NOTES
1
Temperature range is as follows: A and B Versions: –40°C to +85°C.
2
Common-mode voltage. The input signal can be centered on any choice of dc common-mode voltage as long as this value is in the range specified in Figures 8 and 9.
3
See Terminology section.
4
A 200 mV p-p sine wave, varying in frequency from 1 kHz to 200 kHz is coupled onto VDD. A 2.2 nF capacitor is used to decouple VDD to GND.
5
If the input spans of V
6
The AD7450 is functional with a reference input from 100 mV and for VDD = 5 V, the reference can range up to 3.5 V (see References section).
7
The AD7450 is functional with a reference input from 100 mV and for VDD = 3 V, the reference can range up to 2.2 V (see References section).
8
Sample tested @ 25°C to ensure compliance.
9
See Serial Interface section.
10
See Power Versus Throughput Rate section.
11
Measured with a midscale dc input.
3, 8
IN+
9
and V
are both V
IN–
VDD = 5 V 1 1 MSPS max
VDD = 3 V 833 833 kSPS max
Range: 3 V ± 10%; 5 V ± 5% 3/5 3/5 V min/max
= 5 V; f
DD
= 3 V; f
V
DD
= 5 V; f
DD
1.38 mW typ for 100 KSPS
VDD = 3 V; f
0.53 mW typ for 100 KSPS
= 1 MSPS 1.8 1.8 mA max
SAMPLE
= 833 kSPS 1.25 1.25 mA max
SAMPLE
= 1 MSPS; 9 9 mW max
SAMPLE
= 833 kSPS; 3.75 3.75 mW max
SAMPLE
10
10
VDD = 3 V; SCLK ON or OFF 3 3 µW max
, and they are 180° out of phase, the differential voltage is 2 ⫻ V
REF
REF
.
REV. 0
–3–
AD7450
TIMING SPECIFICATIONS
f
= 18 MHz, fS = 1 MSPS, V
SCLK
Limit at T
REF
MIN
1, 2
= 2.5 V; V
, T
MAX
(VDD = 2.7 V to 3.3 V, f
3
= V
CM
; TA = T
REF
MIN
= 15 MHz, fS = 833 kSPS, V
SCLK
to T
, unless otherwise noted.)
MAX
= 1.25 V; VDD = 4.75 V to 5.25 V,
REF
Parameter 3 V 5 V Unit Description
f
SCLK
4
50 50 kHz min
15 18 MHz max
t
CONVERT
16 ⫻ t
SCLK
16 ⫻ t
SCLK
t
SCLK
= 1/f
SCLK
1.07 0.88 µs max SCLK = 15 MHz, 18 MHz
t
QUIET
t
1
t
2
5
t
3
5
t
4
t
5
t
6
t
7
6
t
8
t
POWER-UP
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2
See Figure 1 and the Serial Interface section.
3
Common-mode voltage.
4
Mark/space ratio for the SCLK input is 40/60 to 60/40.
5
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with V
0.4 V
or 2.0 V for VDD = 3 V.
6
t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.
7
See Power-Up Time section.
Specifications subject to change without notice.
25 25 ns min Minimum Quiet Time between the End of a Serial Read and the Next
Falling Edge of
CS
10 10 ns min Minimum CS Pulsewidth
10 10 ns min
CS
Falling Edge to SCLK Falling Edge Setup Time
20 20 ns max Delay from CS Falling Edge until SDATA Three-State Disabled
40 40 ns max Data Access Time after SCLK Falling Edge
0.4 t
0.4 t
SCLK
SCLK
0.4 t
0.4 t
SCLK
SCLK
ns min SCLK High Pulsewidth
ns min SCLK Low Pulsewidth
10 10 ns min SCLK Edge to Data Valid Hold Time
10 10 ns min SCLK Falling Edge to SDATA Three-State Enabled
35 35 ns max SCLK Falling Edge to SDATA Three-State Enabled
7
11µs max Power-Up Time from Full Power-Down
= 5 V, and the time for an output to cross
DD
, quoted in the timing characteristics is the true bus relinquish
8
CS
SCLK
SDATA
t
CONVERT
t
2
1 2 345 13 161514
t
3
00 00DB11 DB10 DB2 DB1
4 LEADING ZEROS
t
5
t
7
t
4
t
6
Figure 1. Serial Interface Timing Diagram
t
8
DB0
THREE-STATE
t
QUIET
t
1
REV. 0–4–
AD7450
ABSOLUTE MAXIMUM RATINGS
(TA = 25°C, unless otherwise noted.)
1
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to V
V
IN+
to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to V
V
IN–
Digital Input Voltage to GND . . . . . . . . –0.3 V to V
Digital Output Voltage to GND . . . . . –0.3 V to V
to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
V
REF
Input Current to Any Pin Except Supplies
2
. . . . . . . ±10 mA
Operating Temperature Range
Commercial (A and B Version) . . . . . . . . . –40
Storage Temperature Range . . . . . . . . . . . . –65
+ 0.3 V
DD
+ 0.3 V
DD
+ 0.3 V
DD
+ 0.3 V
DD
o
C to +85oC
o
C to +150oC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
SOIC, µSOIC Package, Power Dissipation . . . . . . . . 450 mW
Thermal Impedance . . . . . . . . . . . . . . . . 157°C/W (SOIC)
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . 205.9°C/W (µSOIC)
Thermal Impedance . . . . . . . . . . . . . . . . . 56°C/W (SOIC)
JC
. . . . . . . . . . . . . . . . . . . . . . . . . . . 43.74°C/W (µSOIC)
ORDERING GUIDE
Temperature Linearity Package Branding
Model Range Error (LSB)
AD7450AR –40°C to +85°C ± 2 LSB SO-8 AD7450AR
AD7450ARM –40°C to +85°C ± 2 LSB RM-8 CPA
AD7450BR –40°C to +85°C ± 1 LSB SO-8 AD7450BR
AD7450BRM –40°C to +85°C ± 1 LSB RM-8 CPB
EVAL-AD7450CB
EVAL-CONTROL BRD2
NOTES
1
Linearity error here refers to integral nonlinearity error.
2
SO = SOIC; RM = µSOIC.
3
This can be used as a standalone evaluation board or in conjunction with the Evaluation Board Controller for evaluation/demonstration purposes.
4
Evaluation Board Controller
ending in the CB designators. To order a complete evaluation kit, you will need to order the ADC evaluation board, i.e.. EVAL-AD7450CB, the
EVAL-CONTROL BRD2, and a 12 V ac transformer. See the AD7450 evaluation board technical note for more details.
3
. This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards
Evaluation Board
4
Controller Board
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . . 215
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
o
C
o
C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 kV
NOTES
1
Stresses above those listed under the Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch up.
I
OL
1.6V
I
OH
OUTPUT
PIN
200A
TO
C
L
50pF
200A
Figure 2. Load Circuit for Digital Output Timing
Specifications
1
Option
2
Information
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
WARNING!
AD7450 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to
avoid performance degradation or loss of functionality.
REV. 0
–5–
ESD SENSITIVE DEVICE
AD7450
PIN CONFIGURATION
V
REF
V
V
GND
IN+
IN–
1
AD7450
2
TOP VIEW
3
(Not to Scale)
4
8
7
6
5
V
DD
SCLK
SDATA
CS
PIN FUNCTION DESCRIPTION
Pin Number Mnemonic Function
1V
REF
Reference Input for the AD7450. An external reference must be applied to this input. For a
5 V power supply, the reference is 2.5 V (±1%), and for a 3 V power supply, the reference is
1.25 V (± 1%) for specified performance. This pin should be decoupled to GND with a
capacitor of at least 0.1 µF. See the References section for more details.
2V
3V
IN+
IN–
Positive Terminal for Differential Analog Input
Negative Terminal for Differential Analog Input
4 GND Analog Ground. Ground reference point for all circuitry on the AD7450. All analog input
signals and any external reference signal should be referred to this GND voltage.
5 CS Chip Select. Active low logic input. This input provides the dual function of initiating a
conversion on the AD7450 and framing the serial data transfer.
6 SDATA Serial Data. Logic output. The conversion result from the AD7450 is provided on this
output as a serial data stream. The bits are clocked out on the falling edge of the SCLK
input. The data stream consists of four leading zeros followed by the 12 bits of conversion
data that is provided MSB first. The output coding is two’s complement.
7 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part.
This clock input is also used as the clock source for the AD7450’s conversion process.
8V
DD
Power Supply Input. VDD is 3 V (± 10%) or 5 V (± 5%). This supply should be decoupled to
GND with a 0.1 µF capacitor and a 10 µF tantalum capacitor.
REV. 0–6–
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