Analog Devices AD7440 50A b Datasheet

Differential Input, 1 MSPS

10-Bit and 12-Bit ADCs in an 8-Lead SOT-23

FEATURES

Fast throughput rate: 1 MSPS
Specified for V
Low power at max throughput rate:
4 mW max at 1 MSPS with 3 V supplies

9.25 mW max at 1 MSPS with 5 V supplies
Fully differential analog input
Wide input bandwidth:
70 dB SINAD at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface:
SPI®/QSPI™/MICROWIRE™/DSP compatible
Power-down mode: 1 µA max
8-lead SOT-23 and MSOP packages

APPLICATIONS

Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation
Motor control

GENERAL DESCRIPTION

The AD7440/AD7450A1 are 10-bit and 12-bit high speed, low
power, successive approximation (SAR) analog-to-digital
converters with a fully differential analog input. These parts
operate from a single 3 V or 5 V power supply and use advanced
design techniques to achieve very low power dissipation at
throughput rates up to 1 MSPS. The SAR architecture of these
parts ensures that there are no pipeline delays.

The parts contain a low noise, wide bandwidth, differential
track-and-hold amplifier (T/H) that can handle input
frequencies up to 3.5 MHz. The reference voltage is applied
externally to the V

3.5 V depending on the power supply and what suits the
application. The value of the reference voltage determines the
common-mode voltage range of the part. With this truly
differential input structure and variable reference input, the user
can select a variety of input ranges and bias points.

The conversion process and data acquisition are controlled

CS

using
with microprocessors or DSPs. The input signals are sampled

and the serial clock, allowing the device to interface

of 3 V and 5 V

DD

pin and can be varied from 100 mV to

REF

AD7440/AD7450A

FUNCTIONAL BLOCK DIAGRAM

V

DD

V

IN+

V

IN–

V

REF

AD7440/AD7450A

T/H

GND

on the falling edge of CS; the conversion is also initiated at this
point. The SAR architecture of these parts ensures that there are
no pipeline delays. The AD7440 and the AD7450A use ad­vanced design techniques to achieve very low power dissipation
at high throughput rates.

PRODUCT HIGHLIGHTS

1. Operation with either 3 V or 5 V power supplies.

2. High throughput with low power consumption.

With a 3 V supply, the AD7440/AD7450A offer 4 mW
max power consumption for 1 MSPS throughput.

3. Fully differential analog input.

4. Flexible power/serial clock speed management.

The conversion rate is determined by the serial clock,
allowing the power to be reduced as the conversion time
is reduced through the serial clock speed increase. These
parts also feature a shutdown mode to maximize power
efficiency at lower throughput rates.

5. Variable voltage reference input.

6. No pipeline delay.

7. Accurate control of the sampling instant via a

once-off conversion control.

8. ENOB > eight bits typically with 100 mV reference.

1

Protected by U.S. Patent Number 6,681,332.

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

CONTROL LOGIC

Figure 1.

SCLK
SDATA
CS

03051-A-001

CS

input and

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

AD7440/AD7450A

TABLE OF CONTENTS

AD7440–Specifications.................................................................... 3

Digital Inputs .............................................................................. 20

AD7450A–Specifications................................................................. 5

Timing Specifications....................................................................... 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configurations and Function Descriptions ........................... 9

Te r m in o l o g y .................................................................................... 10

AD7440/AD7450A–Typical Performance Characteristics ....... 12

Circuit Information........................................................................ 15

Converter Operation.................................................................. 15

ADC Transfer Function............................................................. 15

Typical C o n ne ction D i a g ram ................................................... 16

Analog Input ............................................................................... 16

Driving Differential Inputs........................................................ 18

REVISION HISTORY

2/04—Data Sheet changed from Rev. A to Rev. B

Reference ..................................................................................... 20

Single-Ended Operation............................................................ 20

Serial Interface............................................................................ 21

Modes of Operation ....................................................................... 23

Normal Mode.............................................................................. 23

Power-Down Mode .................................................................... 23

Power-Up Time .......................................................................... 24

Power vs. Throughput Rate ....................................................... 24

Microprocessor and DSP Interfacing ...................................... 25

Grounding and Layout Hints.................................................... 26

Evaluating the AD7440/AD7450A Performance................... 26

Outline Dimensions....................................................................... 27

Ordering Guide............................................................................... 28

Added Patent Note ..............................................................................1

1/04—Data Sheet changed from Rev. 0 to Rev. A

Updated Format.................................................................... Universal

Changes to General Description .......................................................1

Changes to Table 1 footnotes ............................................................. 3

Changes to Table 2 footnotes ............................................................. 5

Changes to Table 3 footnotes ............................................................. 7

Rev. B | Page 2 of 28

AD7440/AD7450A

AD7440–SPECIFICATIONS

Table 1. VDD = 2.7 V to 3.6 V, f

= 2.5 V; V

V

REF

CM

1

= V

; TA= T

REF

Parameter Test Conditions/Comments B Version Unit

DYNAMIC PERFORMANCE fIN = 100 kHz

Signal-to-(Noise + Distortion) (SINAD)2 61 dB min
Total Harmonic Distortion (THD)2 –82 dB typ –74 dB max
Peak Harmonic or Spurious Noise2 –82 dB typ –76 dB max
Intermodulation Distortion (IMD)2 fa = 90 kHz, fb = 110 kHz

Second-Order Terms –83 dB typ

Third-Order Terms –83 dB typ
Aperture Delay2 5 ns typ
Aperture Jitter2 50 ps typ
Full Power Bandwidth2, 3 @ –3 dB 20 MHz typ

@ –0.1 dB 2.5 MHz typ
DC ACCURACY

Resolution 10 Bits
Integral Nonlinearity (INL)2 ±0.5 LSB max
Differential Nonlinearity (DNL)2 Guaranteed no missed codes to 10 bits ±0.5 LSB max
Zero-Code Error2 ±2.5 LSB max
Positive Gain Error2 ±1 LSB max
Negative Gain Error2 ±1 LSB max

ANALOG INPUT

Full-Scale Input Span 2 × V
Absolute Input Voltage

V

VCM = V

IN+

V

VCM = V

IN–

DC Leakage Current ±1 µA max
Input Capacitance When in track-and-hold 30/10 pF typ

REFERENCE INPUT

V

Input Voltage

REF

DC Leakage Current ± 1 µA max
V

Input Capacitance When in track-and-hold 10/30 pF typ

REF

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V

2.4 V min

INH

0.8 V max

INL

Input Current, IIN Typically 10 nA, VIN = 0 V or VDD ±1 µA max
Input Capacitance, CIN 7 10 pF max

LOGIC OUTPUTS

Output High Voltage, VOH VDD = 4.75 V to 5.25 V; I

V
Output Low Voltage, VOL I
Floating-State Leakage Current ±1 µA max
Floating-State Output Capacitance7 10 pF max
Output Coding Twos Complement

= 18 MHz, fS = 1 MSPS, V

SCLK

MIN

to T

, unless otherwise noted. Temperature range for B Version –40°C to +85°C.

MAX

REF

= 4.75 V to 5.25 V (±1% tolerance for

V

DD

specified performance) 2.5

= 2.7 V to 3.6 V (±1% tolerance for specified

V

DD

performance)

= 2.7 V to 3.6 V; I

DD

= 200 µA 0.4 V max

SINK

= 2.0 V; VDD = 4.75 V to 5.25 V, f

REF

4

V

VCM ± V

REF

VCM ± V

REF

2.0

= 200 µA 2.8 V min

SOURCE

= 200 µA 2.4 V min

SOURCE

= 18 MHz, fS = 1 MSPS,

SCLK

– V

V

IN+

IN–

/2 V

REF

/2 V

REF

5

V

6

V

Rev. B | Page 3 of 28

AD7440/AD7450A

Parameter Test Conditions/Comments B Version Unit

CONVERSION RATE

Conversion Time 888 ns with an 18 MHz SCLK 16 SCLK cycles
Track-and-Hold Acquisition Time2 Sine wave input 200 ns max

Step input 290 ns max

Throughput Rate 1 MSPS max

POWER REQUIREMENTS

VDD Range: 3 V + 20%/–10%; 5 V ± 5% 2.7/5.25 V min/V max

8

I

DD

Normal Mode (Static) SCLK on or off 0.5 mA typ
Normal Mode (Operational) VDD = 4.75 V to 5.25 V 1.95 mA max

V

Full Power-Down Mode SCLK on or off 1 µA max

Power Dissipation

Normal Mode (Operational) VDD = 5 V, 1.55 mW typ for 100 kSPS9 9.25 mW max

V

Full Power-Down VDD = 5 V, SCLK on or off 5 µW max

V

= 2.7 V to 3.6 V 1.45 mA max

DD

= 3 V, 0.6 mW typ for 100 kSPS9 4 mW max

DD

= 3 V, SCLK on or off 3 µW max

DD

are both V

IN–

and are 180°out of phase, the differential voltage is 2 × V

REF

.

REF

1

Common-mode voltage. The input signal can be centered on a dc common-mode voltage in the range specified in Figure 28 and Figure 29.

2

See Terminology section.

3

Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause the converter to return an

incorrect result.

4

Because the input spans of V

5

The AD7440 is functional with a reference input from 100 mV and for VDD = 5 V; the reference can range up to 3.5 V.

6

The AD7440 is functional with a reference input from 100 mV and for VDD = 3 V; the reference can range up to 2.2 V.

7

Guaranteed by characterization.

8

Measured with a midscale dc input.

9

See Power vs. Throughput section.

IN+

and V

Rev. B | Page 4 of 28

AD7440/AD7450A

AD7450A–SPECIFICATIONS

Table 2. VDD = 2.7 V to 3.6 V, f

= 2.5 V; V

V

REF

CM

1

= V

; TA = T

REF

Parameter Test Conditions/Comments B Version Unit

DYNAMIC PERFORMANCE fIN = 100 kHz

Signal-to-(Noise + Distortion) (SINAD)2 70 dB min
Total Harmonic Distortion (THD)2 VDD = 4.75 V to 5.25 V, –86 dB typ –76 dB max
V
Peak Harmonic or Spurious Noise2 VDD = 4.75 V to 5.25 V, –86 dB typ –76 dB max
V
Intermodulation Distortion (IMD)2 fa = 90 kHz, fb = 110 kHz

Second-Order Terms –89 dB typ

Third-Order Terms –89 dB typ
Aperture Delay2 5 ns typ
Aperture Jitter2 50 ps typ
Full Power Bandwidth

2, 3

@ –3 dB 20 MHz typ
@ –0.1 dB 2.5 MHz typ
DC ACCURACY

Resolution 12 Bits
Integral Nonlinearity (INL)2 ±1 LSB max
Differential Nonlinearity (DNL)2 Guaranteed no missed codes to 12 bits ±0.95 LSB max
Zero-Code Error2 ±6 LSB max
Positive Gain Error2 ±2 LSB max
Negative Gain Error2 ±2 LSB max

ANALOG INPUT

Full-Scale Input Span 2 × V
Absolute Input Voltage

V

VCM = V

IN+

V

VCM = V

IN–

DC Leakage Current ±1 µA max
Input Capacitance When in track-and-hold 30/10 pF typ

REFERENCE INPUT

V

Input Voltage

REF

DC Leakage Current ±1 µA max
V

Input Capacitance When in track-and-hold 10/30 pF typ

REF

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V

2.4 V min

INH

0.8 V max

INL

Input Current, IIN Typically 10 nA, VIN = 0 V or VDD ±1 µA max
Input Capacitance, C

7

10 pF max

IN

LOGIC OUTPUTS

Output High Voltage, VOH V
V
Output Low Voltage, V

I

OL

Floating-State Leakage Current ±1 µA max
Floating-State Output Capacitance7 10 pF max
Output Coding Twos Complement

= 18 MHz, fS = 1 MSPS, V

SCLK

MIN

to T

, unless otherwise noted. Temperature range for B Version –40°C to +85°C.

MAX

= 2.7 V to 3.6 V, –84 dB typ –74 dB max

DD

= 2.7 V to 3.6 V, –84 dB typ –74 dB max

DD

= 4.75 V to 5.25 V

V

DD

(±1% tolerance for specified performance)

= 2.7 V to 3.6 V

V

DD

(±1% tolerance for specified performance)

= 4.75 V to 5.25 V; I

DD

= 2.7 V to 3.6 V; I

DD

= 200 µA 0.4 V max

SINK

= 2.0 V; VDD = 4.75 V to 5.25 V, f

REF

4 V

REF

VCM ± V

REF

VCM ± V

REF

= 200 µA 2.8 V min

SOURCE

= 200 µA 2.4 V min

SOURCE

= 18 MHz, fS = 1 MSPS,

SCLK

– V

V

IN+

IN–

/2 V

REF

/2 V

REF

5

V

2.5

6

V

2.0

Rev. B | Page 5 of 28

AD7440/AD7450A

Parameter Test Conditions/Comments B Version Unit

CONVERSION RATE

Conversion Time 888 ns with an 18 MHz SCLK 16 SCLK cycles
Track-and-Hold Acquisition Time2 Sine wave input 200 ns max
Step input 290 ns max
Throughput Rate 1 MSPS max

POWER REQUIREMENTS

VDD Range: 3 V + 20%/–10%; 5 V ± 5% 2.7/5.25 V min/V max

8

I

DD

Normal Mode (Static) SCLK on or off 0.5 mA typ
Normal Mode (Operational) VDD = 4.75 V to 5.25 V 1.95 mA max

V

Full Power-Down Mode SCLK on or off 1 µA max
Power Dissipation

Normal Mode (Operational) VDD = 5 V, 1.55 mW typ for 100 kSPS9 9.25 mW max

V

Full Power-Down VDD = 5 V, SCLK on or off 5 µW max

V

= 2.7 V to 3.6 V 1.45 mA max

DD

= 3 V, 0.6 mW typ for 100 kSPS9 4 mW max

DD

= 3 V, SCLK on or off 3 µW max

DD

are both V

IN–

and are 180° out of phase, the differential voltage is 2 × V

REF

.

REF

1

Common-mode voltage. The input signal can be centered on a dc common-mode voltage in the range specified in Figure 28 and Figure 29.

2

See Terminology section.

3

Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause the converter to return an

incorrect result.

4

Because the input spans of V

5

The AD7450A is functional with a reference input from 100 mV and for VDD = 5 V; the reference can range up to 3.5 V.

6

The AD7450A is functional with a reference input from 100 mV and for VDD = 3 V; the reference can range up to 2.2 V.

7

Guaranteed by characterization.

8

Measured with a midscale dc input.

9

See Power vs. Throughput section.

IN+

and V

Rev. B | Page 6 of 28

AD7440/AD7450A

S

A

S

A

TIMING SPECIFICATIONS

Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of

1.6 V. See Figure 2, Figure 3, and the Serial Interface section.

Table 3. V

= 2.5 V; V

V

REF

Parameter Limit at T

2

f

10 kHz min

SCLK

= 2.7 V to 3.6 V, f

DD

1

= V

CM

REF

; TA = T

MIN

18 MHz max
t

16 × t

CONVERT

t

SCLK

888 ns max
t

60 ns min

QUIET

t1 10 ns min
t2 10 ns min

3

t

20 ns max

3

3

t

40 ns max Data access time after SCLK falling edge

4

t

5

t

6

t

7

4

t

10 ns min SCLK falling edge to SDATA three-state enabled

8

0.4 t

ns min SCLK high pulse width

SCLK

0.4 t

ns min SCLK low pulse width

SCLK

10 ns min SCLK edge to data valid hold time

35 ns max SCLK falling edge to SDATA three-state enabled

5

t

POWER-UP

1 µs max Power-up time from full power-down

= 18 MHz, fS = 1 MSPS, V

SCLK

to T

MIN

, T

Unit Description

MAX

, unless otherwise noted.

MAX

Minimum quiet time between the end of a serial read and the next falling edge of
Minimum
CS

Delay from

= 2.0 V; VDD = 4.75 V to 5.25 V, f

REF

SCLK

= 1/f

SCLK

CS

pulse width

falling edge to SCLK falling edge setup time

CS

falling edge until SDATA three-state disabled

= 18 MHz, fS = 1 MSPS,

SCLK

CS

1

Common-mode voltage.

2

Mark/space ratio for the SCLK input is 40/60 to 60/40.

3

Measured with the load circuit of and defined as the time required for the output to cross 0.8 V or 2.4 V with VFigure 4

4

t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of The measured number is then extrapolated

back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.

5

See Power-Up Time section.

= 5 V or 0.4 V or 2.0 V for VDD = 3 V.

DD

Figure 4.

, quoted in the Timing Specifications is the true bus relinquish

8

t

1

CS

SCLK

DAT

CS

SCLK

DAT

t

2

12345 13141516

t

3

0 0 0 0 DB11 DB10 DB2 DB1 DB0

4 LEADING ZEROS THREE-STATE

t

4

Figure 2. AD7450A Serial Interface Timing Diagram

t

2

12345 13141516

t

3

0 0 0 0 DB9 DB8 DB0 0 0

4 LEADING ZEROS 2 TRAILING ZEROS

t

4

Figure 3. AD7440 Serial Interface Timing Diagram

t

CONVERT

t

5

t

7

B

t

6

t

8

t

QUIET

03051-A-002

t

1

t

CONVERT

t

5

t

7

B

t

6

t

8

t

QUIET

THREE-STATE

03051-A-003

Rev. B | Page 7 of 28

AD7440/AD7450A

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND –0.3 V to +7 V
V

to GND –0.3 V to VDD + 0.3 V

IN+

V

to GND –0.3 V to VDD + 0.3 V

IN–

Digital Input Voltage to GND –0.3 V to +7 V
Digital Output Voltage to GND –0.3 V to VDD + 0.3 V
V

to GND –0.3 V to VDD + 0.3 V

REF

Input Current to Any Pin Except Supplies1±10 mA
Operating Temperature Range

Commercial (B Version) –40°C to +85°C
Storage Temperature Range –65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance

MSOP 205.9°C/W

SOT-23 211.5°C/W
θJC Thermal Impedance

MSOP 43.74°C/W

SOT-23 91.99°C/W
Lead Temperature, Soldering

Vapor Phase (60 secs) 215°C

Infrared (15 secs) 220°C
ESD 1 kV

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Figure 4. Load Circuit for Digital Output Timing Specifications

TO OUTPUT

PIN

25pF

C

L

1.6mA I

200µAI

OL

OH

1.6V

03051-A-004

1

Transient currents of up to 100 mA do not cause SCR latch up.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. B | Page 8 of 28

AD7440/AD7450A

V

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

V

SCLK

SDATA

CS

DD

1

AD7440/

2

AD7450A

3

TOP VIEW

4

(Not to Scale)

V

8

REF

7

V

IN+

6

V

IN–

5

GND

03051-A-005

Figure 5. Pin Configuration for 8-Lead SOT-23

Table 5. Pin Function Descriptions

Mnemonic Function

V

REF

Reference Input for the AD7440/AD7450A. An external reference must be applied to this input. For a 5 V power supply, the
reference is 2.5 V (±1%) for specified performance. For a 3 V power supply, the reference is 2 V (±1%) for specified
performance. This pin should be decoupled to GND with a capacitor of at least 0.1 µF. See the Reference section for more
details.

V

Positive Terminal for Differential Analog Input.

IN+

V

Negative Terminal for Differential Analog Input.

IN–

GND

Analog Ground. Ground reference point for all circuitry on the AD7440/AD7450A. All analog input signals and any external
reference signal should be referred to this GND voltage.

CS

Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on the AD7440/AD7450A
and framing the serial data transfer.

SDATA

Serial Data. Logic output. The conversion result from the AD7440/AD7450A is provided on this output as a serial data stream.
The bits are clocked out on the falling edge of the SCLK input. The data stream of the AD7450A consists of four leading zeros
followed by the 12 bits of conversion data, which are provided MSB first; the data stream of the AD7440 consists of four
leading zeros, followed by the 10 bits of conversion data, followed by two trailing zeros. In both cases, the output coding is
twos complement.

SCLK

Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the
clock source for the conversion process.

VDD

Power Supply Input. V

is 3 V (+20%/–10%) or 5 V (±5%). This supply should be decoupled to GND with a 0.1 µF capacitor

DD

and a 10 µF tantalum capacitor in parallel.

REF

V
V

GND

IN+
IN–

1

AD7440/

2

AD7450A

3

TOP VIEW

(Not to Scale)

4

8
7
6
5

V

DD

SCLK
SDATA
CS

03051-A-006

Figure 6. Pin Configuration for 8-Lead MSOP

Rev. B | Page 9 of 28