ANALOG DEVICES AD7401A Service Manual

V

V

V

Isolated Sigma-Delta Modulator

FEATURES

20 MHz maximum external clock rate
Second-order modulator
16 bits, no missing codes
±2 LSB INL typical at 16 bits
1 μV/°C typical offset drift
On-board digital isolator
On-board reference
±250 mV analog input range
Low power operation: 17 mA typical at 5.5 V

−40°C to +125°C operating range
16-lead SOIC package
Internal clock version: AD7400A
Safety and regulatory approvals

UL recognition

3750 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12

V

= 891 V peak

IORM

APPLICATIONS

AC motor controls
Shunt current monitoring
Data acquisition systems
Analog-to-digital and opto-isolator replacements

AD7401A

GENERAL DESCRIPTION

The AD7401A1 is a second-order, sigma-delta (Σ-Δ) modulator
that converts an analog input signal into a high speed, 1-bit data
stream with on-chip digital isolation based on Analog Devices,
Inc., iCoupler® technology. The AD7401A operates from a 5 V
power supply and accepts a differential input signal of ±250 mV
(±320 mV full scale). The analog input is continuously sampled
by the analog modulator, eliminating the need for external
sample-and-hold circuitry. The input information is contained
in the output stream as a density of ones with a data rate up to
20 MHz. The original information can be reconstructed with
an appropriate digital filter. The serial I/O can use a 5 V or a 3 V
supply (V

The serial interface is digitally isolated. High speed CMOS,
combined with monolithic air core transformer technology,
means the on-chip isolation provides outstanding performance
characteristics, superior to alternatives such as optocoupler
devices. The part contains an on-chip reference. The AD7401A
is offered in a 16-lead SOIC and has an operating temperature
range of −40°C to +125°C.

DD2

).

FUNCTIONAL BLOCK DIAGRAM

DD1

+

IN

VIN–

1

Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Other patents pending.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

REF

H

/

T

U

B

F

Σ-Δ ADC

CONTROL LOG IC

GND

UPDATE

WATC HDOG

1

Figure 1.

DD2

AD7401A

WATCHDOG

ENCODE DECODE

UPDATE

DECODE

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

ENCODE

GND

MDAT

MCLKIN

2

07332-001

AD7401A

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Specifications .................................................................. 5

Insulation and Safety-Related Specifications ............................ 6

Regulatory Information ............................................................... 6

DIN V VDE V 0884-10 (VDE V 0884-10) Insulation

Characteristics .............................................................................. 7

Absolute Maximum Ratings ............................................................ 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ............................. 9

Typical Performance Characteristics ........................................... 10

Terminology .................................................................................... 13

Theory of Operation ...................................................................... 14

Circuit Information .................................................................... 14

Analog Input ............................................................................... 14

Differential Inputs ...................................................................... 15

Current Sensing Applications ................................................... 15

Voltage Sensing Applications .................................................... 15

Digital Filter ................................................................................ 16

Applications Information .............................................................. 18

Grounding and Layout .............................................................. 18

Evaluating the AD7401A Performance ................................... 18

Insulation Lifetime ..................................................................... 18

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 19

REVISION HISTORY

7/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 20

AD7401A

SPECIFICATIONS

V

= 4.5 V to 5.5 V, V

DD1

16 MHz maximum,

= 3 V to 5.5 V, VIN+ = −200 mV to +200 mV, and VIN− = 0 V (single-ended); TA = −40°C to +125°C, f

DD2

1

tested with sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted.

MCLKIN

=

Table 1.

1, 2

Y Version

Parameter

STATIC PERFORMANCE

Resolution
Integral Nonlinearity (INL)

3

16 Bits Filter output truncated to 16 bits

±1.5 ±7 LSB
±2 ±13 LSB
±1.5 ±11 LSB
±2 ±46 LSB

Differential Nonlinearity (DNL)

3

Offset Error
Offset Drift vs. Temperature
Offset Drift vs. V
Gain Error

3

DD1

3

3

±0.9 LSB Guaranteed no missed codes to 16 bits,

±.025 ±0.5 mV

1 3.5 μV/°C

120 μV/V

0.07 ±1.5 mV

3

±1 mV
Gain Error Drift vs. Temperature
Gain Error Drift vs. V

DD1

3

3

23 μV/°C

110 μV/V

ANALOG INPUT

Input Voltage Range

±200 ±250 mV For specified performance; full range ±320 mV

Dynamic Input Current ±13 ±18 μA
±10 ±15 μA

0.08 μA
DC Leakage Current ±0.01 ±0.6 μA
Input Capacitance 10 pF

DYNAMIC SPECIFICATIONS VIN+ = 5 kHz

3

Signal-to-(Noise + Distortion) Ratio (SINAD)

76 82 dB VIN+ = ±200 V, TA = −40°C to +85°C,

71 82 dB VIN+ = ±250 V, TA = −40°C to +85°C,

72 82 dB VIN+ = ±200 V, TA = −40°C to +125°C,

82 dB VIN+ = ±250 V, TA = −40°C to +125°C,

Signal-to-Noise Ratio (SNR)

3

81 83 dB VIN+ = ±250 V, TA = −40°C to +125°C,

80 82 dB VIN+ = ±200 V, TA = −40°C to +125°C,

Total Harmonic Distortion (THD)3
Peak Harmonic or Spurious Noise (SFDR)
Effective Number of Bits (ENOB)3
Isolation Transient Immunity

LOGIC INPUTS

3

Input High Voltage, VIH 0.8 × V

−90 dB

3

−92 dB

13.3 12.3 Bits

25 30 kV/μs

V

DD2

Input Low Voltage, VIL 0.2 × V
Input Current, IIN ±0.5 μA
Floating State Leakage Current 1 μA
Input Capacitance, C

4

10 pF

IN

Unit Test Conditions/Comments Min Typ Max

V

+ = ±200 V, TA = −40°C to +85°C, f

V

DD2

IN

V

+ = ±250 V, TA = −40°C to +85°C, f

IN

V

+ = ±200 V, TA = −40°C to +125°C, f

IN

V

+ = ±250 V, TA = −40°C to +125°C, f

IN

f

= 20 MHz max,1 VIN+ = −250 mV to +250 mV

MCLKIN

f

= 20 MHz max,1 VIN+ = −250 mV to +250 mV

MCLKIN

f

= 20 MHz max,1 VIN+ = −250 mV to +250 mV

MCLKIN

V

+ = 500 mV, VIN− = 0 V, f

IN

V

+ = 400 mV, VIN− = 0 V, f

IN

V

+ = 0 V, VIN− = 0 V, f

IN

f

= 5 MHz to 20 MHz

MCLKIN

f

= 5 MHz to 20 MHz

MCLKIN

f

= 5 MHz to 20 MHz

MCLKIN

f

= 5 MHz to 20 MHz

MCLKIN

f

= 5 MHz to 20 MHz

MCLKIN

f

= 5 MHz to 20 MHz

MCLKIN

f

= 20 MHz max1, VIN+ = −250 mV to +250 mV

MCLKIN

MCLKIN

1

1

1

1

1

1

MCLKIN

MCLKIN

= 20 MHz max

MCLKIN

= 20 MHz max

MCLKIN

= 20 MHz max

= 20 MHz max
= 20 MHz max

= 20 MHz max

MCLKIN

= 20 MHz max

MCLKIN

1

1

1

1

1

1

1

Rev. 0 | Page 3 of 20

AD7401A

1, 2

Y Version

Parameter

Unit Test Conditions/Comments Min Typ Max

LOGIC OUTPUTS

Output High Voltage, VOH V

− 0.1 V IO = −200 μA

DD2

Output Low Voltage, VOL 0.4 V IO = +200 μA

POWER REQUIREMENTS

V

4.5 5.5 V

DD1

V

3 5.5 V

DD2

5

I

10 12 mA V

DD1

6

I

DD2

7 9 mA V

3 4 mA V

Power Dissipation

1

For f

> 16 MHz to 20 MHz, mark space ratio is 48/52 to 52/48, V

MCLK

2

All voltages are relative to their respective ground.

3

See the section. Terminology

4

Sample tested during initial release to ensure compliance.

5

See . Figure 15

6

See . Figure 17

93.5 mW V

= V

= 5 V ± 5%, and TA = −40°C to +85°C.

DD1

DD2

= 5.5 V

DD1

= 5.5 V

DD2

= 3.3 V

DD2

= V

DD1

= 5.5 V

DD2

Rev. 0 | Page 4 of 20

AD7401A

TIMING SPECIFICATIONS

V

= 4.5 V to 5.5 V, V

DD1

= 3 V to 5.5 V, TA = −40°C to +125°C, unless otherwise noted.

DD2

Table 2.

1

2, 3

Limit at T

20 MHz max Master clock input frequency

MIN

, T

MAX

Unit Description

Parameter

f

MCLKIN

5 MHz min Master clock input frequency

4

t

1

4

t

2

t3 0.4 × t
t

4

1

Sample tested during initial release to ensure compliance.

2

Mark space ratio for clock input is 40/60 to 60/40 for f

3

V

= V

= 5 V ± 5% for f

DD1

DD2

4

Measured with the load circuit of and defined as the time required for the output to cross 0.8 V or 2.0 V. Figure 2

25 ns max Data access time after MCLKIN rising edge
15 ns min Data hold time after MCLKIN rising edge

ns min Master clock low time

MCLKIN

0.4 × t

ns min Master clock high time

MCLKIN

> 16 MHz to 20 MHz.

MCLKIN

≤ 16 MHz and 48/52 to 52/48 for 16 MHz < f

MCLKIN

MCLKIN

< 20 MHz.

200µA I

TO OUTPUT

PIN

C

L

25pF

200µA I

Figure 2. Load Circuit for Digital Output Timing Specifications

OL

1.6V

OH

07332-002

t

4

MCLKIN

MDAT

t

1

Figure 3. Data Timing

t

2

t

3

07332-003

Rev. 0 | Page 5 of 20

AD7401A

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 3.

Parameter Symbol Value Unit Conditions

Input-to-Output Momentary Withstand Voltage V
Minimum External Air Gap (Clearance) L(I01) 7.46 min mm

Minimum External Tracking (Creepage) L(I02) 8.1 min mm

Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table I)

REGULATORY INFORMATION

Table 4.

1

UL

CSA VDE

Recognized Under 1577
Component Recognition Program

3750 V rms Isolation Voltage

File E214100 File 205078 File 2471900-4880-0001

1

In accordance with UL 1577, each AD7401A is proof tested by applying an insulation test voltage ≥ 4500 V rms for 1 second (current leakage detection limit = 7.5 μA).

2

In accordance with DIN V VDE V 0884-10, each AD7400A is proof tested by applying an insulation test voltage ≥1671V peak for 1 sec (partial discharge detection limit = 5 pC).

Approved under CSA Component

1

Acceptance Notice #5A
Reinforced insulation per

CSA 60950-1-03 and IEC 60950-1,
630 V rms maximum working
voltage

3750 min V 1-minute duration

ISO

Measured from input terminals to output
terminals, shortest distance through air

Measured from input terminals to output
terminals, shortest distance path along body

2

Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-12

2

Reinforced insulation per DIN V VDE V 0884-10 (VDE V
0884-10):2006-12, 891 V peak

Rev. 0 | Page 6 of 20