Analog Devices AD7398 9 Datasheet

Quad, Serial-Input

CODE – Decimal

–0.50

0

512

DNL – LSB

0

–0.40

–0.30

–0.20

–0.10

0.10

0.20

0.30

0.40

0.50

1024 1536

2048

2560 3072 3584

4096

VDD = +5V
V

SS

= –5V

V

REF

= +2.5V

T

A

= 25ⴗC

a

FEATURES
AD7398—12-Bit Resolution
AD7399—10-Bit Resolution
Programmable Power Shutdown
Single (3 V to 5 V) or Dual (ⴞ5 V) Supply Operation
3-Wire Serial SPI-Compatible Interface
Internal Power ON Reset
Double Buffered Registers for Simultaneous
Multichannel DAC Update
Four Separate Rail-to-Rail Reference Inputs
Thin Profile TSSOP-16 Package Available
Low Tempco 1.5 ppm/ⴗC

APPLICATIONS
Automotive Output Voltage Span
Portable Communications
Digitally Controlled Calibration
PC Peripherals

GENERAL DESCRIPTION

The AD7398/AD7399 family of quad, 12-bit/10-bit, voltage­output digital-to-analog converters is designed to operate from a
single 3 V to 5 V or a dual ±5 V supply. Built with Analog’s robust
CBCMOS process, this monolithic DAC offers the user low
cost, and ease-of-use in single or dual-supply systems.

The applied external reference V
output voltage. Valid V

values include VSS < V

REF

result in a wide selection of full-scale outputs. For multiplying
applications ac inputs can be as large as ±5 V

A doubled-buffered serial-data interface offers high-speed,
3-wire, SPI and microcontroller-compatible inputs using serial­data-in (SDI), clock (CLK), and a chip-select (CS). A common
level-sensitive load-DAC strobe (LDAC) input allows simulta­neous update of all DAC outputs from previously loaded Input
Registers. Additionally, an internal power ON reset forces the
output voltage to zero at system turn ON. An external asynchro­nous reset (RS) also forces all registers to the zero code state. A
programmable power-shutdown feature reduces power dissipa­tion on unused DACs.

Both parts are offered in the same pinout to enable users to
select the appropriate resolution for their application without
redesigning the layout. For 8-bit resolution applications see the
pin compatible AD7304 product.

The AD7398/AD7399 is specified over the extended industrial
(–40°C to +125°C) temperature range. Parts are available in
wide body SOIC-16 and ultracompact thin 1.1 mm TSSOP­16 packages.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

determines the full-scale

REF

P

< V

DD

that

REF

.

12-Bit/10-Bit DACs

AD7398/AD7399

FUNCTIONAL BLOCK DIAGRAM

V

DD

CS

SDI

CLK

SERIAL

REGISTER

POWER

ON RESET

V

SS

12/10

INPUT
REG A

INPUT
REG B

INPUT
REG C

INPUT
REG D

REGISTER

REGISTER

REGISTER

REGISTER

Figure 1. AD7398 DNL vs. Code (TA = 25°C)

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

DAC A

DAC B

DAC C

DAC D

LDACRS

V

B

REF

V

REFCVREF

V

DAC A

DAC B

DAC C

DAC D

REF

A

V

A

OUT

B

V

OUT

C

V

OUT

D

V

OUT

D

GND

AD7398/AD7399–SPECIFICATIONS

(@ VDD = 5 V, VSS = 0 V; or VDD = +5 V, VSS = –5 V, V

AD7398 12-BIT VOLTAGE OUTPUT DAC

P

arameter Symbol Condition 3 V–5 V ⴞ 10% ⴞ5 V ⴞ 10% Unit

STATIC PERFORMANCE

Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error V
Full-Scale Voltage Error V
Full-Scale Tempco

REFERENCE INPUT

V

REF

Input Resistance
Input Capacitance

ANALOG OUTPUT

Output Current I
Capacitive Load

LOGIC INPUTS

Logic Input Low Voltage V

Logic Input High Voltage V

Input Leakage Current I
Input Capacitance

INTERFACE TIMING

Clock Frequency f
Clock Width High t
Clock Width Low t
CS to Clock Set Up t
Clock to CS Hold t
Load DAC Pulsewidth t
Data Setup t
Data Hold t
Load Setup to CS t
Load Hold to CS t

AC CHARACTERISTICS

Output Slew Rate SR Data = 000H to FFFH to 000
Settling Time
Shutdown Recovery t
DAC Glitch Q Code 7FF
Digital Feedthrough Q
Feedthrough V

SUPPLY CHARACTERISTICS

Shutdown Supply Current I
Positive Supply Current I
Negative Supply Current I
Power Dissipation P
Power Supply Sensitivity PSS ∆VDD = ±5% 0.006 0.006 %/% max

NOTES

1

One LSB = V

2

The first eight codes (000H, 007H) are excluded from the linearity error measurement in single supply operation.

3

These parameters are guaranteed by design and not subject to production testing.

4

When V
offset voltage of the output buffer, which is the same as the V

5

Input resistance is code-dependent.

6

Typicals represent average readings measured at 25°C.

7

All input control signals are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.

8

The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.

Specifications subject to change without notice.

1

IN Range

2

2

3

4

5

3

3

N 12 12 Bits
INL ±1.5 ±1.5 LSB max
DNL Monotonic ±1 ±1 LSB max

ZSE

FSE

TCV

V

REF

R

REF

C

REF

OUT

C

L

IL

FS

Data = 000
Data = FFF

Data = 555H, Worst-Case 35 35 kΩ typ

Data = 800H, ∆V
No Oscillation 200 400 pF max

VDD = 3 V 0.5 V max
V

IH

3

3, 7

8

IL

C

IL

CLK

CH

CL

CSS

CSH

LDAC

DS

DH

LDS

LDH

t

S

SDR

DF

OUT/VREFVREF

CLK Only 80% V

To ±0.1% of Full Scale 6 6 µs typ

Data = 000H, f = 100 kHz

DD_SD

DD

SS

DISS

/4096 V for the 12-bit AD7398.

REF

is connected to either the VDD or the VSS power supply the corresponding V

REF

No Load 30/60 30/60 µA typ/max
VIL = 0 V, No Load 1.5/2.5 1.6/2.7 mA typ/max
VIL = 0 V, No Load 1.5/2.5 1.6/2.7 mA typ/max
VIL = 0 V, No Load 5 16 mW typ

ZSE

< +125ⴗC, unless otherwise noted.)

H

H

= 4 LSB ±5 ± 5 mA typ

OUT

= 5 V 0.8 0.8 V max

DD

H

to 800H to 7FF

H

H

= 1.5 VDC + 1 V p-p, –63 –63 dB typ

voltage will program between ground and the supply voltage minus the

error specification. See additional discussion in the Operation section of the data sheet.

OUT

7 ±2.5 mV max
±2.5 ±2.5 mV max

1.5 1.5 ppm/°C typ

0/V

DD

5 5 pF typ

DD

2.1–2.4 2.4 V min
11µA max
10 10 pF max

11 16.6 MHz max
45 30 ns min
45 30 ns min
10 5 ns min
20 15 ns min
45 30 ns min
15 10 ns min
10 5 ns min
0 0 ns min
20 15 ns min

22V/µs typ

66µs typ
150 150 nVs typ
15 15 nVs typ

= +2.5 V, –40ⴗC < T

REF

VSS/V

DD

V min/max

4.0 V min

A

6

–2–

REV. 0

AD7398/AD7399

(@ VDD = 5 V, VSS = 0 V; or VDD = +5 V, VSS = –5 V, V

AD7399 10-BIT VOLTAGE OUTPUT DAC

P

arameter Symbol Condition 3 V–5 V ⴞ 10% ⴞ5 V ⴞ 10% Unit

STATIC PERFORMANCE

Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error V
Full-Scale Voltage Error V
Full-Scale Tempco

REFERENCE INPUT

V

REF

Input Resistance
Input Capacitance

1

IN Range

2

2

3

4

5

3

N 10 10 Bits
INL ±1 ± 1 LSB max
DNL Monotonic ±1 ±1 LSB max

ZSE

FSE

TCV

V

REF

R

REF

C

REF

FS

Data = 000
Data = 3FF

Data = 155H, Worst-Case 40 40 kΩ typ

< +125ⴗC, unless otherwise noted.)

H

H

7 ±4 mV max
±15 ± 15 mV max

1.5 1.5 ppm/°C typ

0/V

DD

5 5 pF typ

= +2.5 V, –40ⴗC < T

REF

VSS/V

DD

V min/max

ANALOG OUTPUT

Output Current I
Capacitive Load

3

C

OUT

L

Data = 200H, ∆V

= 1 LSB ± 5 mA typ

OUT

No Oscillation 200 400 pF max

LOGIC INPUTS

Logic Input Low Voltage V

Logic Input High Voltage V

IL

IH

VDD = 3 V 0.5 V max
V

= 5 V 0.8 0.8 V max

DD

CLK Only 80% V

DD

4.0 V min

2.1–2.4 2.4 V min
Input Leakage Current I
Input Capacitance

INTERFACE TIMING

3

3, 7

Clock Frequency f
Clock Width High t
Clock Width Low t
CS to Clock Set Up t
Clock to CS Hold t
Load DAC Pulsewidth t
Data Setup t
Data Hold t
Load Setup to CS t
Load Hold to CS t

IL

C

IL

CLK

CH

CL

CSS

CSH

LDAC

DS

DH

LDS

LDH

11µA max
10 10 pF max

11 16.6 MHz max
45 30 ns min
45 30 ns min
10 5 ns min
20 15 ns min
45 30 ns min
15 10 ns min
10 5 ns min
0 0 ns min
20 15 ns min

AC CHARACTERISTICS

Output Slew Rate SR Data = 000H to 3FFH to 000
Settling Time
Shutdown Recovery t
DAC Glitch Q Code 1FF
Digital Feedthrough Q
Feedthrough V

8

t

S

SDR

DF

OUT/VREFVREF

To ±0.1% of Full Scale 6 6 µs typ

to 200H to 1FF

H

= 1.5 VDC + 1 V p-p, –63 –63 dB typ

H

H

22V/µs typ

66µs typ
150 150 nVs typ
15 15 nVs typ

Data = 000H, f = 100 kHz

SUPPLY CHARACTERISTICS

Shutdown Supply Current I
Positive Supply Current I
Negative Supply Current I
Power Dissipation P

DD_SD

DD

SS

DISS

No Load 30/60 30/60 µA typ/max
VIL = 0 V, No Load 1.5/2.5 1.6/2.7 mA typ/max
VIL = 0 V, No Load 1.5/2.5 1.6/2.7 mA typ/max
VIL = 0 V, No Load 5 16 mW typ

Power Supply Sensitivity PSS ∆VDD = ±5% 0.006 0.006 %/% max

NOTES

1

One LSB = V

2

The first two codes (000H, 001H) are excluded from the linearity error measurement in single supply operation.

3

These parameters are guaranteed by design and not subject to production testing.

4

When V
offset voltage of the output buffer, which is the same as the V

5

Input resistance is code-dependent.

6

Typicals represent average readings measured at 25°C.

7

All input control signals are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.

8

The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.

Specifications subject to change without notice.

REV. 0

/1024 V for the 10-bit AD7399.

REF

is connected to either the VDD or the VSS power supply the corresponding V

REF

error specification. See additional discussion in the Operation section of the data sheet.

ZSE

–3–

voltage will program between ground and the supply voltage minus the

OUT

A

6

AD7398/AD7399

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –7 V

SS

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, V

V

REF

DD

Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V

V

to GND . . . . . . . . . . . . . . . . . V

OUT

Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . 50 mA

I

OUT

Thermal Resistance θ

JA

– 0.3 V, VDD + 0.3 V

SS

16-Lead SOIC Package (R-16) . . . . . . . . . . . . . . 158°C/W

16-Lead Thin Shrink Surface Mount (RU-16) . . . 180°C/W

Maximum Junction Temperature (T

Package Power Dissipation . . . . . . . . . . . . . (T

Max) . . . . . . . . 150°C

J

Max–TA)/θ

J

Operating Temperature Range . . . . . . . . . . –40°C to +125°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature

R-16 (Vapor Phase, 60 secs) . . . . . . . . . . . . . . . . . . 215°C

RU-16 (Infrared, 15 secs) . . . . . . . . . . . . . . . . . . . . 224°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

JA

ORDERING GUIDE

Resolution Temperature Package Package Container

Model (Bits) Range Description Option Quantity

AD7398BR 12 –40°C to +125°C SOL-16 R-16 48
AD7398BR-REEL7 12 –40°C to +125°C SOL-16 R-16 1,000
AD7398BRU-REEL7 12 –40°C to +125°C TSSOP-16 RU-16 1,000
AD7399BR 10 –40°C to +125°C SOL-16 R-16 48
AD7399BR-REEL7 10 –40°C to +125°C SOL-16 R-16 1,000
AD7399BRU-REEL7 10 –40°C to +125°C TSSOP-16 RU-16 1,000

The AD7398 contains 3254 transistors. The die size measures 108 mil × 144 millimeters.

SDI

CLK

CS

LDAC

CLK

LDAC

CS

SA

t

LDS

SD A1

t

CSS

D11A0 D10

D9 D8 D7 D6 D5 D4 D3 D2

t

t

DH

DS

t

CH

t

CL

Figure 2. AD7398 Timing Diagram (AD7399 with SDI = 14 Bits Only)

t

LDH

1/f

t

CLK

LDAC

t

CSS

t

CSS

t

CH

t

LDS

t

CL

t

CSH

Figure 3. Continuous Clock Timing Diagram

t

LDS

D1 D0

t

CSH

t

LDH

IN
REG
LD

t

LDAC

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7398/AD7399 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

–4–

REV. 0

AD7398/AD7399

PIN CONFIGURATION

V

BV

1

OUT

A

V

2

OUT

V

REF

V

REF

GND

LDAC

V

SS

A

B

RS

AD7398/

3

AD7399

4

TOP VIEW

5

(Not to Scale)

6

7

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1V
2V
3V
4V

5V

B DAC B Voltage Output.

OUT

A DAC A Voltage Output.

OUT

SS

A DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can

REF

B DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can

REF

Negative Power Supply Input. Specified range of operation 0 V to –5.5 V.

be tied to V

be tied to V

or VSS pin.

DD

or VSS pin.

DD

6 GND Ground Pin.
7 LDAC Load DAC Register Strobe, Level Sensitive Active Low. Transfers all Input Register data to

DAC registers. Asynchronous active low input. See Control Logic Truth Table for operation.

8 RS Resets Input and DAC Registers to All Zero Codes. Shift Register contents unchanged.
9 CS Chip Select, Active Low Input. Disables shift register loading when high. Transfers Serial Regis-

ter Data to the Input Register when CS returns High. Does not effect LDAC operation.

10 CLK Schmitt Triggered Clock Input, Positive Edge Clocks Data into Shift Register.
11 SDI Serial Data Input. Input data loads directly into the shift register.
12 V

13 V

14 V
15 V
16 V

D DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. Pin can

REF

be tied to V

C DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. Pin can

REF

be tied to V

DD

D DAC D Voltage Output.

OUT

C DAC C Voltage Output.

OUT

Positive Power Supply Input. Specified range of operation 3 V to 5 V ± 10%.

or VSS pin.

DD

or VSS pin.

DD

C

16

OUT

V

D

15

OUT

V

14

DD

C

13

V

REF

V

12

D

REF

SDI

11

CLK

10

98

CS

REV. 0

–5–