ANALOG DEVICES AD7376 Service Manual

+30 V/±15 V Operation

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FEATURES

128 positions
10 kΩ, 50 kΩ, 100 kΩ
5 V to 30 V single-supply operation
±5 V to ±15 V dual-supply operation
3-wire SPI®-compatible serial interface
THD 0.006% typical
Programmable preset
Power shutdown: less than 1 μA
iCMOS™

APPLICATIONS

High voltage DAC
Programmable power supply
Programmable gain and offset adjustment
Programmable filters, delays
Actuator control
Audio volume control
Mechanical potentiometer replacement

process technology

128-Position Digital Potentiometer

AD7376

FUNCTIONAL BLOCK DIAGRAM

AD7376

SDO

SDI

CLK

CS

Q

7-BIT

SERIAL

REGISTER

D

CK

GND

7 7

7-BIT

LATCH

R

RS

Figure 1.

SHDN

SHDN

V

DD

A

W

B

V

SS

01119-001

GENERAL DESCRIPTION

The AD73761 is one of the few high voltage, high performance
digital potentiometers
as a programmable resistor or resistor divider. The AD7376
performs the same electronic adjustment function as mechanical
potentiometers, variable resistors, and trimmers with enhanced
resolution, solid-state reliability, and programmability. With
digital rather than manual control, the AD7376 provides layout
flexibility and allows closed-loop dynamic controllability.

1

Patent number: 54952455.

2

The terms digital potentiometer and RDAC are used interchangeably.

2

on the market. This device can be used

The AD7376 features sleep-mode programmability in shutdown
th

at can be used to program the preset before device activation,

thus providing an alternative to costly EEPROM solutions.

The AD7376 is available in 14-lead TSSOP and 16-lead wide

dy SOIC packages in 10 kΩ, 50 kΩ, and 100 kΩ options. All

bo
parts are guaranteed to operate over the −40°C to +85°C
extended industrial temperature range.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©1997-2007 Analog Devices, Inc. All rights reserved.

AD7376

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TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics—10 kΩ Version................................ 3

Electrical Characteristics—50 kΩ, 100 kΩ Versions ............... 4

Timing Specifications .................................................................. 5

3-Wire Digital Interface................................................................... 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 12

Programming the Variable Resistor......................................... 12

Programming the Potentiometer Divider............................... 13

3-Wire Serial Bus Digital Interface.......................................... 13

Daisy-Chain Operation ............................................................. 14

ESD Protection ........................................................................... 14

Terminal Voltage Operating Range ......................................... 14

Power-Up and Power-Down Sequences.................................. 14

Layout and Power Supply Biasing............................................ 15

Applications Information.............................................................. 16

High Voltage DAC...................................................................... 16

Programmable Power Supply ................................................... 16

Audio Volume Control .............................................................. 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 19

REVISION HISTORY

3/07—Rev. A to Rev. B

Updated Format..................................................................Universal

Changes to Absolute Maximum Ratings....................................... 7

Changes to ESD Protection Section............................................. 14

Changes to Ordering Guide.......................................................... 19

11/05—Rev. 0 to Rev. A

pdated Format..................................................................Universal

U

Deleted DIP Package..........................................................Universal

Changes to Features.......................................................................... 1

Separated Electrical Characteristics into Table 1 and Table 2 .... 3

Separated Interface Timing into Table 3 ....................................... 5

Changes to Table 1 Through Table 3.............................................. 3

Added Table 4.................................................................................... 6

Added Figure 2.................................................................................. 6

Changes to Absolute Maximum Ratings Section......................... 7

Deleted Parametric Test Circuits Section...................................... 7

Changes to Typical Performance Characteristics......................... 9

Added Daisy-Chain Operation Section....................................... 14

Added ESD Protection Section..................................................... 14

Added Terminal Voltage Operating Range Section................... 14

Added Power-Up and Power-Down Sequences Section ........... 14

Added Layout and Power Supply Biasing Section...................... 15

Added Applications Section .......................................................... 16

Updated Outline Dimensions....................................................... 18

Changes to Ordering Guide.......................................................... 19

10/97—Revision 0: Initial Version

Rev. B | Page 2 of 20

AD7376

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SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—10 kΩ VERSION

VDD/VSS = ±15 V ± 10%, VA = VDD, VB = VSS/0 V, −40°C < TA < +85°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ1Max Unit

DC CHARACTERISTICS—

RHEOSTAT MODE
Resistor Differential Nonlinearity2R-DNL RWB, VA = NC, VDD/VSS = ±15 V −1 ±0.5 +1 LSB
Resistor Nonlinearity

2

Nominal Resistor Tolerance ∆RAB T
Resistance Temperature Coefficient3(∆RAB/RAB)/∆T × 106 V
Wiper Resistance RW V

DC CHARACTERISTICS—

POTENTIOMETER DIVIDER MODE
Integral Nonlinearity
Differential Nonlinearity

4

4

Voltage Divider Temperature

Coefficient
Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range

5

Capacitance6 A, B C

Capacitance

Shutdown Supply Current

6

7

Shutdown Wiper Resistance R
Common-Mode Leakage ICM V

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH V
Input Logic Low VIL V
Output Logic High VOH R
Output Logic Low VOL I
Input Current IIL V
Input Capacitance

6

POWER SUPPLIES

Power Supply Range VDD/VSS Dual-supply range ±4.5 ±16.5 V
Power Supply Range VDD Single-supply range, VSS = 0 4.5 33 V
Positive Supply Current IDD V
V
Negative Supply Current ISS V
V
Power Dissipation

8

Power Supply Rejection Ratio PSRR ΔVDD/ΔVSS = ±15 V ± 10% −0.2 ±0.05 +0.2 %/%

R-INL RWB, VA = NC, VDD/VSS = ±15 V −1 ±0.5 +1 LSB

= 25°C −30 +30 %

A

= VDD, wiper = no connect −300 ppm/°C

AB

= ±15 V 120 200 Ω

DD/VSS

VDD/VSS = ±5 V 260 Ω

INL VDD/VSS = ±15 V −1 ±0.5 +1 LSB
DNL VDD/VSS = ±15 V −1 ±0.5 +1 LSB
(∆V

V

CW

I

)/∆T × 106 Code = 0x40 5 ppm/°C

W/VW

Code = 0x7F, VDD/VSS = ±15 V −3 −1.5 0 LSB

WFSE

Code = 0x00, VDD/VSS = ±15 V 0 1.5 3 LSB

WZSE

V

A, B, W

A, B

f = 1 MHz, measured to GND,

ode = 0x40

c
f = 1 MHz, measured to GND,

ode = 0x40

c

A_SD

W_SD

= VDD, VB = 0 V, SHDN = 0

V

A

= VDD, VB = 0 V, SHDN = 0, VDD = 15 V

V

A

= VB = VW 1 nA

A

= 5 V or 15 V 2.4 V

DD

= 5 V or 15 V 0.8 V

DD

= 2.2 kΩ to 5 V 4.9 V

Pull-Up

= 1.6 mA, V

OL

= 0 V or 5 V ±1 μA

IN

= 5 V, VDD = 15 V 0.4 V

LOGI C

VDD V

SS

45 pF

60 pF

0.02 1 μA
170 400 Ω

CIL 5 pF

= 5 V or VIL = 0 V, VDD/VSS = ±15 V 2 mA

IH

= 5 V or VIL = 0 V, VDD/VSS = ±5 V 12 25 μA

IH

= 5 V or VIL = 0 V, VDD/VSS = ±15 V −0.1 mA

IH

= 5 V or VIL = 0 V, VDD/VSS = ±5 V −0.1 mA

IH

P

V

DISS

= 5 V or VIL = 0 V, VDD/VSS = ±15 V 31.5 mW

IH

Rev. B | Page 3 of 20

AD7376

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Parameter Symbol Conditions Min Typ1Max Unit

DYNAMIC CHARACTERISTICS

Bandwidth −3 dB BW Code = 0x40 470 kHz
Total Harmonic Distortion THDW V
VW Settling Time tS V
Resistor Noise Voltage e

1

Typical values represent average readings at 25°C, VDD = 15 V, and VSS = −15 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL

measures the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic.

3

Pb-free parts have a 35 ppm/°C temperature coefficient (tempco).

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider, similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

5

Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

Measured at the A terminal. A terminal is open circuit in shutdown mode.

8

P

is calculated from (IDD × VDD) + abs(ISS × VSS). CMOS logic level inputs result in minimum power dissipation.

DISS

9

Bandwidth, noise, and settling times are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest

bandwidth. The highest R value results in the minimum overall power consumption.

10

All dynamic characteristics use VDD = 15 V and VSS = −15 V.

ELECTRICAL CHARACTERISTICS—50 kΩ, 100 kΩ VERSIONS

VDD/VSS = ±15 V ± 10% or ±5 V ± 10%, VA = VDD, VB = VSS/0 V, −40°C < TA < +85°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ1Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity
Resistor Nonlinearity
R
Nominal Resistor Tolerance ∆RAB T
Resistance Temperature Coefficient

Wiper Resistance RW V

DC CHARACTERISTICS—

POTENTIOMETER DIVIDER MODE
Integral Nonlinearity
Differential Nonlinearity
Voltage Divider Temperature

Coefficient
Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range
Capacitance6 A, B C

Capacitance

Shutdown Supply Current
Shutdown Wiper Resistance R
Common-Mode Leakage ICM V

5

6

6, 9 ,10

2

= 1 V rms, VB = 0 V, f = 1 kHz 0.006 %

A

= 10 V, VB = 0 V, ±1 LSB error band 4 μs

A

R

N_WB

2

R-DNL RWB, VA = NC −1 ±0.5 +1 LSB

= 5 kΩ, f = 1 kHz 0.9 nV√Hz

WB

R-INL RWB, VA = NC, RAB = 50 kΩ −1.5 ±0.5 +1.5 LSB

, VA = NC, RAB = 100 kΩ −1 ±0.5 +1 LSB

WB

= 25°C −30 +30 %

3

(∆RAB/RAB)/∆T ×

6

10

A

= VDD, wiper = no connect −300 ppm/°C

V

AB

= ±15 V 120 200 Ω

DD/VSS

VDD/VSS = ±5 V 260 Ω

4

4

7

INL −1 ±0.5 +1 LSB
DNL −1 ±0.5 +1 LSB
(∆V

)/∆T × 106 Code = 0x40 5 ppm/°C

W/VW

Code = 0x7F −2 −0.5 0 LSB

WFSE

Code = 0x00 0 0.5 1 LSB

WZSE

V

V

A, B, W

CW

I

A_SD

A, B

W_SD

f = 1 MHz, measured to GND,

ode = 0x40

c
f = 1 MHz, measured to GND,

ode = 0x40

c

= VDD, VB = 0 V, SHDN = 0

V

A

= VDD, VB = 0 V, SHDN = 0, VDD = 15 V

V

A

= VB = VW 1 nA

A

VDD V

SS

45 pF

60 pF

0.02 1 μA
170 400 Ω

Rev. B | Page 4 of 20

AD7376

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Parameter Symbol Conditions Min Typ1Max Unit

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH V
Input Logic Low VIL V
Output Logic High VOH R
Output Logic Low VOL I
Input Current IIL V
Input Capacitance

6

CIL 5 pF

POWER SUPPLIES

Power Supply Range VDD/VSS Dual-supply range ±4.5 ±16.5 V
Power Supply Range VDD Single-supply range, VSS = 0 4.5 33 V
Positive Supply Current IDD V
V
Negative Supply Current ISS V
V
Power Dissipation

8

P

V

DISS

Power Supply Rejection Ratio PSRR −0.25 ±0.1 +0.25 %/%

DYNAMIC CHARACTERISTICS

6, 9 , 10

Bandwidth −3 dB BW RAB = 50 kΩ, code = 0x40 90 kHz
R
Total Harmonic Distortion THDW V
VW Settling Time tS V
Resistor Noise Voltage e

1

Typical values represent average readings at 25°C, VDD = 15 V, and VSS = −15 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL

measures the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic.

3

Pb-free parts have a 35 ppm/°C temperature coefficient.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider, similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

5

Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

Measured at the A terminal. A terminal is open circuit in shutdown mode.

8

P

is calculated from (IDD × VDD) + abs(ISS × VSS). CMOS logic level inputs result in minimum power dissipation.

DISS

9

Bandwidth, noise, and settling times are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest

bandwidth. The highest R value results in the minimum overall power consumption.

10

All dynamic characteristics use VDD = 15 V and VSS = −15 V.

R

N_WB

TIMING SPECIFICATIONS

= 5 V or 15 V 2.4 V

DD

= 5 V or 15 V 0.8 V

DD

= 2.2 kΩ to 5 V 4.9 V

Pull-Up

= 1.6 mA, V

OL

= 0 V or 5 V ±1 μA

IN

= 5 V or VIL = 0 V, VDD/VSS = ±15 V 2 mA

IH

= 5 V or VIL = 0 V, VDD/VSS = ±5 V 12 25 μA

IH

= 5 V or VIL = 0 V, VDD/VSS = ±15 V −0.1 mA

IH

= 5 V or VIL = 0 V, VDD/VSS = ±5 V −0.1 mA

IH

= 5 V or VIL = 0 V, VDD/VSS = ±15 V 31.5 mW

IH

= 100 kΩ, code = 0x40 50 kHz

AB

= 1 V rms, VB = 0 V, f = 1 kHz 0.002 %

A

= 10 V, VB = 0 V, ±1 LSB error band 4 μs

A

= 25 kΩ, f = 1 kHz 2 nV√Hz

WB

= 5 V, VDD = 15 V 0.4 V

LOGI C

Table 3.

Parameter Symbol Conditions Min Typ Max Unit

INTERFACE TIMING CHARACTERISTICS

Clock Frequency f

1, 2

CLK

Input Clock Pulse Width tCH, tCL Clock level high or low 120 ns
Data Setup Time tDS 30 ns
Data Hold Time tDH 20 ns
CLK to SDO Propagation Delay
CS Setup Time

CS High Pulse Width

3

tPD R
t

120 ns

CSS

t

150 ns

CSW

= 2.2 kΩ, CL < 20 pF 10

Pull-Up

Reset Pulse Width tRS 120 ns

t

CLK Fall to CS Fall Hold Time
CLK Rise to CS Rise Hold Time
CS Rise to Clock Rise Setup

1

Guaranteed by design and not subject to production test.

2

See for the location of the measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

Figure 3

Switching characteristics are measured using VDD = 15 V and VSS = −15 V.

3

Propagation delay depends on value of VDD, R

Pull-Up

10 ns

CSH0

t

120 ns

CSH

t

120 ns

CS1

, and CL.

Rev. B | Page 5 of 20

4 MHz

100 ns

AD7376

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3-WIRE DIGITAL INTERFACE

Table 4. AD7376 Serial Data-Word Format

1

MSB LSB
D6 D5 D4 D3 D2 D1 D0

6

2

1

Data is loaded MSB first.

2

0

1

CLK

V

SDI

OUT

CS

0

1

0

1

0

1

0

D6 D5 D4 D3 D2 D1 D0

RDAC REGISTER LOAD

01119-002

Figure 2. AD7376 3-Wire Digital Interface Timing Diagram

= VDD, VB = 0 V, VW = V

(V

A

OUT

)

1

SDI

(DATA IN)

SDO

(DATA OUT)

CLK

CS

V

OUT

t

V

CSH0

DD

0V

D

0

1

0

1

0

1

0

X

D'

X

t

CH

t

CSS

D

X

t

DS

t

DH

D'

X

t

PD_MAX

t

CS1

t

CL

t

CSH

t

CSW

t

S

±1 LSB ER ROR BAND

±1 LSB

01119-003

Figure 3. Detail Timing Diagram

Rev. B | Page 6 of 20