Analog Devices AD73460BB-80 Datasheet

Six-Input Channel

a

FEATURES
AFE PERFORMANCE
Six 16-Bit A/D Converters
Programmable Input Sample Rate
Simultaneous Sampling
72 dB SNR
64 kS/s Maximum Sample Rate

80 dB Crosstalk

–
Low Group Delay (25 ␮s Typ per ADC Channel)
Programmable Input Gain
Single Supply Operation
On-Chip Reference

DSP PERFORMANCE
19 ns Instruction Cycle Time @ 3.3 V, 52 MIPS

Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in

Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby

Power Dissipation with 400 Cycle Recovery from

Power-Down Condition
Low Power Dissipation in Idle Mode

DATA

ADDRESS

GENERATORS

DAG 1

DAG 2

ARITHMETIC UNITS

ADSP-2100 BASE

ARCHITECTURE

Analog Front End

AD73460

FUNCTIONAL BLOCK DIAGRAM

POWER-DOWN

CONTROL

MEMORY

PROGRAM

SEQUENCER

SHIFTERMACALU

ADC1 ADC2 ADC4 ADC5 ADC6

16K PM

(OPTIONAL

8K)

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

SERIAL PORTS

SPORT 0

REF

SERIAL PORT

ADC3

ANALOG FRONT END

(OPTIONAL

SPORT 1

16K DM

8K)

SPORT 2

SECTION

PROGRAMMABLE

I/O

AND

FLAGS

TIMER

FULL MEMORY

CONTROLLER

AD73460

MODE

EXTERNAL

ADDRESS

BUS

EXTERNAL

DATA

BUS

BYTE DMA

GENERAL DESCRIPTION

The AD73460 is a six-input channel analog front-end processor
for general-purpose applications including industrial power meter­ing or multichannel analog inputs. It features six 16-bit A/D
conversion channels, each of which provides 72 dB signal-to-noise
ratio over a dc-to-2 kHz signal bandwidth. Each channel also
features a programmable input gain amplifier (PGA) with gain
settings in eight stages from 0 dB to 38 dB.

The AD73460 is particularly suitable for industrial power metering
as each channel samples synchronously, ensuring that there is
no (phase) delay between the conversions. The AD73460 also
features low group delay conversions on all channels.

An on-chip reference voltage of 1.25 V is included. The sampling
rate of the device is programmable with separate settings
offering 64 kHz, 32 kHz, 16 kHz, and 8 kHz sampling rates (from
a master clock of 16.384 MHz), while the serial port (SPORT2)
allows easy expansion of the number of input channels by cas­cading an extra AFE external to the AD73460.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

The AD73460’s DSP engine combines the ADSP-2100 family
base architecture (three computational units, data address gen­erators, and a program sequencer) with two serial ports, a 16-bit
internal DMA port, a byte DMA port, a programmable timer,
Flag I/O, extensive interrupt capabilities, and on-chip program
and data memory.

The AD73460-80 integrates 80K bytes of on-chip memory
configured as 16K words (24-bit) of program RAM and 16K
(16-bit) of data RAM. The AD73460-40 integrates 40K bytes
of on-chip memory configured as 8K words (24-bit) of program
RAM and 8K (16-bit) of data RAM. Power-down circuitry is
also provided to meet the low power needs of battery-operated
portable equipment. The AD73460 is available in a 119-ball
PBGA package.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

AD73460

TABLE OF CONTENTS

Topic Page

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 5

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PBGA BALL CONFIGURATION . . . . . . . . . . . . . . . . . . . . 7

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 8

ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . 10

ANALOG FRONT END . . . . . . . . . . . . . . . . . . . . . . . . . . 10

FUNCTIONAL DESCRIPTION–AFE . . . . . . . . . . . . . . . 11

Encoder Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Signal Conditioner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . 11

ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Analog Sigma-Delta Modulator . . . . . . . . . . . . . . . . . . . . 12

Decimation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

ADC Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

AFE Serial Port (SPORT2) . . . . . . . . . . . . . . . . . . . . . . . 13

SPORT2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

SPORT Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Master Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Serial Clock Rate Divider . . . . . . . . . . . . . . . . . . . . . . . . . 14

Decimation Rate Divider . . . . . . . . . . . . . . . . . . . . . . . . . 14

Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Resetting the AFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Channel Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Cascade Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

FUNCTIONAL DESCRIPTION—DSP . . . . . . . . . . . . . . 20

Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DSP SECTION PIN DESCRIPTIONS . . . . . . . . . . . . . . . 21

Memory Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Terminating Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . 22

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Topic Page

LOW POWER OPERATION . . . . . . . . . . . . . . . . . . . . . . . 23

Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Slow Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

MODES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . 25

Setting Memory Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Passive Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Active Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

MEMORY ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . 25

PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Program Memory (Full Memory Mode) . . . . . . . . . . . . . 26

Program Memory (Host Mode) . . . . . . . . . . . . . . . . . . . . 26

DATA MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Data Memory (Full Memory Mode) . . . . . . . . . . . . . . . . 26

I/O Space (Full Memory Mode) . . . . . . . . . . . . . . . . . . . . 26

Composite Memory Select (CMS) . . . . . . . . . . . . . . . . . . 26

Boot Memory Select (BMS) Disable . . . . . . . . . . . . . . . . 27

Byte Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Byte Memory DMA (BDMA, Full Memory Mode) . . . . . 27

Internal Memory DMA Port (IDMA Port;

Host Memory Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Bootstrap Loading (Booting) . . . . . . . . . . . . . . . . . . . . . . 28

IDMA Port Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Bus Request and Bus Grant (Full Memory Mode) . . . . . . 28

Flag I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

INSTRUCTION SET DESCRIPTION . . . . . . . . . . . . . . . 29

DESIGNING AN EZ-ICE-COMPATIBLE

SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Target Board Connector for EZ-ICE Probe . . . . . . . . . . . 30

Target Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . 30

PM, DM, BM, IOM, and CM . . . . . . . . . . . . . . . . . . . . . 30

Target System Interface Signals . . . . . . . . . . . . . . . . . . . . 30

ANALOG FRONT END (AFE) INTERFACING . . . . . . . 30

DSP SPORT TO AFE INTERFACING . . . . . . . . . . . . . . 30

CASCADE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . 31

Interfacing to the AFE’s Analog Inputs . . . . . . . . . . . . . . 31

Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 32

–2–

REV. 0

AD73460

(AVDD = 3.0 V to 3.6 V; DVDD = 3.0 V to 3.6 V; DGND = AGND = 0 V, f

SPECIFICATIONS

fS = 8 kHz; TA = T

MIN

to T

, unless otherwise noted.)

MAX

AD73460B

Parameter Min Typ Max Unit Test Conditions/Comments

= 16.384 MHz, f

MCLK

= 8.192 MHz,

SCLK

1

REFERENCE

REFCAP

Absolute Voltage, V

REFCAP

1.125 1.25 1.375 V

REFCAP TC 50 ppm/°C 0.1 µF Capacitor Required from REFCAP

to AGND2

REFOUT

Typical Output Impedance 130 Ω
Absolute Voltage, V

REFOUT

1.125 1.25 1.375 V Unloaded
Minimum Load Resistance 1 kΩ
Maximum Load Capacitance 100 pF

ADC SPECIFICATIONS

Maximum Input Range at VIN

2, 3

1.644 V p-p Measured Differentially
–2.85 dBm

Nominal Reference Level at VIN 1.1413 V p-p Measured Differentially

(0 dBm0) –6.02 dBm

Absolute Gain

PGA = 0 dB –1.2 +0.6 dB 1.0 kHz

Signal to (Noise + Distortion)

PGA = 0 dB 71 dB 0 Hz to 4 kHz; f
PGA = 0 dB 70 72 dB 0 Hz to 2 kHz; f

= 8 kHz; fIN = 60 Hz

S

= 8 kHz; fIN = 60 Hz

S

Total Harmonic Distortion

PGA = 0 dB –77 –72 dB

Intermodulation Distortion –76 dB PGA = 0 dB
Idle Channel Noise –70 dB PGA = 0 dB
Crosstalk ADC-to-ADC –83 dB ADC1 Input at Idle

ADC2 to ADC6 Input Signal: 1.0 kHz

–95 dB ADC1 Input at Idle

ADC2 to ADC6 Input Signal: 60 Hz
DC Offset –30 +10 +45 mV PGA = 0 dB
Power Supply Rejection –55 dB Input Signal Level at AVDD and DVDD

Pins 1.0 kHz, 100 mV p-p Sine Wave
Group Delay

4, 5

25 µs 64 kHz Output Sample Rate
50 µs 32 kHz Output Sample Rate
95 µs 16 kHz Output Sample Rate

Input Resistance at VIN

2, 4

Phase Mismatch 0.15 Degrees f

190 µs 8 kHz Output Sample Rate
25 kΩ

6

DMCLK = 16.384 MHz

= 1 kHz

IN

0.01 Degrees fIN = 60 Hz

FREQUENCY RESPONSE

(ADC)7 Typical Output

Frequency (Normalized to f

)

S

00dB

0.03125 –0.1 dB

0.0625 –0.25 dB

0.125 –0.6 dB

0.1875 –1.4 dB

0.25 –2.8 dB

0.3125 –4.5 dB

0.375 –7.0 dB

0.4375 –9.5 dB
> 0.5 < –12.5 dB

REV. 0

–3–

(AVDD = 3.0 V to 3.6 V; DVDD = 3.0 V to 3.6 V; DGND = AGND = 0 V,

AD73460–SPECIFICATIONS

f

= 16.384 MHz, f

MCLK

= 64 kHz; TA = T

SAMP

MIN

to T

, unless otherwise noted.)

MAX

AD73460B

Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS

V

, Input High Voltage VDD – 0.8 V

INH

, Input Low Voltage 0 0.8 V

V

INL

I

, Input Current 10 µA

IH

DD

V

CIN, Input Capacitance 10 pF

LOGIC OUTPUTS

, Output High Voltage VDD – 0.4 V

V

OH

, Output Low Voltage 0 0.4 V |IOUT| ≤ 100 µA

V

OL

DD

V |IOUT| ≤ 100 µA

Three-State Leakage Current –10 +10 µA

POWER SUPPLIES

AVDD1, AVDD2 3.0 3.6 V
DVDD 3.0 3.6 V

8

I

DD

NOTES

1

Operating temperature range is as follows: –20°C to +85°C. Therefore, T

2

Test conditions: Input PGA set for 0 dB gain (unless otherwise noted).

3

At input to sigma-delta modulator of ADC.

4

Guaranteed by design.

5

Overall group delay will be affected by the sample rate and the external digital filtering.

6

The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 × 1011)/DMCLK.

7

Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier
bypassed and input gain of 0 dB.

8

Test Conditions: no load on digital inputs, analog inputs ac coupled to ground.

Specifications subject to change without notice.

= –20°C and T

MIN

= +85°C.

MAX

See Table I

Table I. AFE Section Current Summary (AVDD = DVDD = 3.3 V)

Total
Current MCLK

Conditions (Max) SE ON Comments

REFCAP Only On 1.0 0 No REFOUT Disabled
REFCAP and

REFOUT Only On 4.5 0 No
All Sections On 26.5 1 Yes REFOUT Enabled
All Sections Off 1.5 0 Yes MCLK Active Levels Equal to 0 V and DVDD
All Sections Off 0.1 0 No Digital Inputs Static and Equal to 0 V or DVDD

The above values are in mA. MCLK = 16.384 MHz; SCLK = 16.384 MHz.

–4–

REV. 0

AD73460

(AVDD = 3.0 V to 3.6 V; DVDD = 3.0 V to 3.6 V; DGND = AGND = 0 V, f

SPECIFICATIONS

TA = T

MIN

to T

, unless otherwise noted.)

MAX

Parameter Test Conditions Min Typ Max Unit

DSP SECTION

Hi-Level Input Voltage

V

IH

V

Hi-Level CLKIN Voltage @ VDD = max 2.2 V

IH

V

Lo-Level Input Voltage

IL

Hi-Level Output Voltage

V

OH

V

Lo-Level Output Voltage

OL

Hi-Level Input Current

I

IH

I

Lo-Level Input Current

IL

I

Three-State Leakage Current

OZH

Three-State Leakage Current

I

OZL

I

Supply Current (Idle)

DD

I

Supply Current (Dynamic)

DD

Input Pin Capacitance

C

I

COOutput Pin Capacitance

NOTES

1

Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.

2

Input only pins: RESET, BR, DR0, DR1, PWD.

3

Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.

4

Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH.

5

Although specified for TTL outputs, all AD73460 outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads.

6

Guaranteed but not tested.

7

Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.

8

0 V on BR.

9

Idle refers to AD73460 state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND.

10

VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.

11

IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2

and Type 6, and 20% are idle instructions.

12

Applies to PBGA package type.

13

Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

1, 2

1, 3

1, 4, 5

1, 4, 5

3

3

9

3, 6, 12

6, 7, 12, 13

@ VDD = max 2.0 V

@ VDD = min 0.8 V
@ VDD = min, IOH = –0.5 mA 2.4 V
@ V

= min, IOH = –100 µA

DD

6

@ VDD = min, IOL = 2 mA 0.4 V
@ VDD = max, VIN = VDD max 10 µA
@ VDD = max, VIN = 0 V 10 µA

7

@ VDD = max, VIN = VDD max

7

@ VDD = max, VIN = 0 V
@ VDD = 3.3 V
t

= 19 ns

CK

= 25 ns

t

CK

t

= 30 ns

11

CK

@ VDD = 3.3 V, T

= 19 ns

t

CK

t

= 25 ns

CK

t

= 30 ns

CK

10

10

10

= 25°C

AMB

10

10

10

@ VIN = 2.5 V, fIN = 1.0 MHz, T
@ VIN = 2.5 V, fIN = 1.0 MHz, T

8

8

= 25°C8pF

AMB

= 25°C8pF

AMB

= 16.384 MHz, f

MCLK

= 64 kHz;

SAMP

VDD–0.3 V

10 µA
10 µA

14 mA
12 mA
10 mA

54 mA
43 mA
37 mA

REV. 0

–5–

AD73460

WARNING!

ESD SENSITIVE DEVICE

(AVDD = 3 V to 3.6 V; DVDD = 3 V to 3.6 V; AGND = DGND = 0 V;

TIMING CHARACTERISTICS–AFE SECTION

Limit at

Parameter TA = –20ⴗC to +85ⴗC Unit Description

Clock Signals See Figure 1

t

1

t

2

t

3

Serial Port See Figures 3 and 4

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

t

13

NOTES

1

For details of the DSP section timing, please refer to the ADSP-2185L data sheet and the ADSP-2100 Family User’s Manual, Third Edition.

Specifications subject to change without notice.

61 ns min AMCLK Period

24.4 ns min AMCLK Width High

24.4 ns min AMCLK Width Low

t

1

0.4 × t

1

0.4 × t

1

20 ns min SDI/SDIFS Setup Before SCLK Low
0 ns min SDI/SDIFS Hold After SCLK Low
10 ns max SDOFS Delay from SCLK High
10 ns max SDOFS Hold After SCLK High
10 ns max SDO Hold After SCLK High
10 ns max SDO Delay from SCLK High
30 ns max SCLK Delay from AMCLK

1

TA = T

MlN

to T

, unless otherwise noted.)

MAX

ns min SCLK Period (SCLK = AMCLK)
ns min SCLK Width High
ns min SCLK Width Low

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C unless otherwise noted)

AVDD, DVDD to GND . . . . . . . . . . . . . . . –0.3 V to +4.6 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD + 0.3 V

Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . –20°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –20°C to +125°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C

PBGA, θ

Thermal Impedance . . . . . . . . . . . . . . . . . 25°C/W

JA

Reflow Soldering

Maximum Temperature . . . . . . . . . . . . . . . . . . . . . . 225°C

Time at Maximum Temperature . . . . . . . . . . . . . . . 15 sec

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ORDERING GUIDE

Temperature Package Package

Model Range Description Options

AD73460BB-80 –20°C to +85°C 119-Ball Plastic Grid Array B-119
AD73460BB-40 –20°C to +85°C 119-Ball Plastic Grid Array B-119

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD73460 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

–6–

REV. 0

AD73460

PBGA BALL CONFIGURATIONS

PBGA Ball PBGA Ball PBGA Ball PBGA Ball
Number Name Number Name Number Name Number Name

A1 IRQE/PF4 E3 RFS0 J5 D22 N7 D13
A2 DMS E4 A3/IAD2 J6 D21 P1 EBR
A3 VDD(INT) E5 A2/IAD1 J7 D20 P2 D0/IAD13
A4 CLKIN E6 A1/IAD0 K1 ELOUT P3 DVDD
A5 A11/IAD10 E7 A0 K2 ELIN P4 DGND
A6 A7/IAD6 F1 DR0 K3 EINT P5 ARESET
A7 A4/IAD3 F2 SCLK0 K4 D19 P6 SCLK2
B1 IRQL0/PF5 F3 DT1 K5 D18 P7 MCLK
B2 PMS F4 PWDACK K6 D17 R1 SDO
B3 WR F5 BGH K7 D16 R2 SDOFS
B4 XTAL F6 Mode A/PF0 L1 BG R3 SDIFS
B5 A12/IAD11 F7 Mode B/PF1 L2 D3/IACK R4 SDI
B6 A8/IAD7 G1 TFS1 L3 D5/IAL R5 SE
B7 A5/IAD4 G2 RFS1 L4 D8 R6 REFCAP
C1 IRQL1/PF6 G3 DR1 L5 D9 R7 REFOUT
C2 IOMS G4 GND L6 D12 T1 VINN2
C3 RD G5 PWD L7 D15 T2 VINP2
C4 VDD(EXT) G6 VDD(EXT) M1 EBG T3 VINN1
C5 A13/IAD12 G7 Mode C/PF2 M2 D2/IAD15 T4 VINP1
C6 A9/IAD8 H1 SCLK1 M3 D4/IS T5 VINN3
C7 GND H2 ERESET M4 D7/IWR T6 VINP3
D1 IRQ2/PF7 H3 RESET M5 VDD(EXT) T7 VINN4
D2 CMS H4 PF3 M6 D11 U1 AGND
D3 BMS H5 FL0 M7 D14 U2 AVDD
D4 CLKOUT H6 FL1 N1 BR U3 VINP6
D5 GND H7 FL2 N2 D1/IAD14 U4 VINN6
D6 A10/IAD9 J1 EMS N3 VDD(INT) U5 VINP5
D7 A6/IAD5 J2 EE N4 D6/IRD U6 VINN5
E1 DT0 J3 ECLK N5 GND U7 VINP4
E2 TFS0 J4 D23 N6 D10

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PBGA BALL CONFIGURATION

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–7–

AD73460

PIN FUNCTION DESCRIPTIONS

Mnemonic Function

VINP1 Analog Input to the Positive Terminal of Input Channel 1.
VINN1 Analog Input to the Negative Terminal of Input Channel 1.
VINP2 Analog Input to the Positive Terminal of Input Channel 2.
VINN2 Analog Input to the Negative Terminal of Input Channel 2.
VINP3 Analog Input to the Positive Terminal of Input Channel 3.
VINN3 Analog Input to the Negative Terminal of Input Channel 3.
VINP4 Analog Input to the Positive Terminal of Input Channel 4.
VINN4 Analog Input to the Negative Terminal of Input Channel 4.
VINP5 Analog Input to the Positive Terminal of Input Channel 5.
VINN5 Analog Input to the Negative Terminal of Input Channel 5.
VINP6 Analog Input to the Positive Terminal of Input Channel 6.
VINN6 Analog Input to the Negative Terminal of Input Channel 6.
REFOUT Buffered Reference Output, which has a nominal value of 1.25 V.
REFCAP A Bypass Capacitor to AGND2 of 0.1 µF is required for the on-chip reference. The capacitor should be fixed

to this pin. This pin can be overdriven by an external reference if required.
AVDD Analog Power Supply Connection
AGND Analog Ground/Substrate Connection
DGND Digital Ground/Substrate Connection
DVDD Digital Power Supply Connection
ARESET Active Low Reset Signal. This input resets the analog front end of the AD73460, resetting the control registers and

clearing the digital circuitry.
SCLK2 Output Serial Clock whose rate determines the serial transfer rate to/from the AFE. It is used to clock data or

control information to and from the serial port (SPORT2). The frequency of SCLK is equal to the frequency

of the master clock (MCLK) divided by an integer number—this integer number being the product of the

external master clock rate divider and the serial clock rate divider.
MCLK Master Clock Input of the analog front end. MCLK is driven from an external clock signal.
SDO Serial Data Output of the AD73460. Both data and control information may be output on this pin and are clocked

on the positive edge of SCLK2. SDO is in three-state when no information is being transmitted and when SE is low.
SDOFS Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and it is active one SCLK period

before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK2. SDOFS is in

three-state when SE is low.
SDIFS Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and it is valid one SCLK period before

the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK2 and is ignored when SE

is low.
SDI Serial Data Input of the AD73460. Both data and control information may be input on this pin and are clocked on

the negative edge of SCLK2. SDI is ignored when SE is low.
SE SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the output pins

of the SPORT are three-stated and the input pins are ignored. SCLK2 is also disabled internally in order to

decrease power dissipation. When SE is brought high, the control and data registers of the SPORT are

at their original values (before SE was brought low); however, the timing counters and other internal registers are

at their reset values.

RESET (Input) Processor Reset Input
BR (Input) Bus Request Input
BG (Output) Bus Grant Output
BGH (Output) Bus Grant Hung Output
DMS (Output) Data Memory Select Output
PMS (Output) Program Memory Select Output
IOMS (Output) Memory Select Output
BMS (Output) Byte Memory Select Output
CMS (Output) Combined Memory Select Output
RD (Output) Memory Read Enable Output

1

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AD73460

PIN FUNCTION DESCRIPTIONS1 (continued)

Mnemonic Function

WR (Output) Memory Write Enable Output
IRQ2/ (Input) Edge- or Level-Sensitive Interrupt

PF7 (Input/Output) Request.
IRQL0/ (Input) Level-Sensitive Interrupt Requests
PF6 (Input/Output) Programmable I/O Pin
IRQL1/ (Input) Level-Sensitive Interrupt Requests
PF5 (Input/Output) Programmable I/O Pin
IRQE/ (Input) Edge-Sensitive Interrupt Requests
PF4 (Input/Output) Programmable I/O Pin
Mode D/ (Input) Mode Select Input—Checked Only During RESET
PF3 (Input/Output) Programmable I/O Pin During Normal Operation
Mode C/ (Input) Mode Select Input—Checked Only During RESET
PF2 (Input/Output) Programmable I/O Pin During Normal Operation
Mode B/ (Input) Mode Select Input—Checked Only During RESET
PF1 (Input/Output) Programmable I/O Pin During Normal Operation
Mode A/ (Input) Mode Select Input—Checked Only During RESET
PF0 (Input/Output) Programmable I/O Pin During Normal Operation
CLKIN, (Inputs) Clock or Quartz Crystal Input

XTAL
CLKOUT (Output) Processor Clock Output
SPORT0 (Inputs/Outputs) Serial Port I/O Pins
SPORT1 (Inputs/Outputs) Serial Port I/O Pins
IRQ1:0 (Inputs) Edge- or Level-Sensitive Interrupts,
FI (Input) Flag In

3

FO (Output) Flag Out
PWD (Input) Power-Down Control Input
PWDACK (Output) Power-Down Control Output
FL0, FL1, (Outputs) Output Flags

FL2
A13 to A0 (Output) Address Output Pins for Program, Data, Byte, and I/O Space
D23 to D0 (Input/Output) Data I/O Pins for Program, Data, Byte, and I/O Space
VDD and Power and Ground

GND
EZ-ICE Port (Inputs/Outputs) For Emulation Use

ERESET

EMS

EE

ECLK

ELOUT

ELIN

EINT

EBR

EBG

NOTES

1

Refer to the ADSP-2185L data sheet for a detailed description of the DSP pins.

2

Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt
vector address when the pin is asserted, either by external devices, or set as a programmable flag.

3

SPORT configuration determined by the DSP System Control Register. Software configurable.

2

Programmable I/O Pin

3

2

2

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AD73460

ARCHITECTURE OVERVIEW

The AD73460 instruction set provides flexible data moves and
multifunction (one or two data moves with a computation) instruc­tions. Every instructions can be executed in a single processor
cycle. The AD73460 assembly language uses an algebraic syntax
for ease of coding and readability. A comprehensive set of devel­opment tools supports program development.

DATA

ADDRESS

GENERATORS

DAG 1

DAG 2

ARITHMETIC UNITS

ADSP-2100 BASE

ARCHITECTURE

POWER-DOWN

CONTROL

MEMORY

PROGRAM

SEQUENCER

PROGRAM MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

ADC1 ADC2 ADC4 ADC5 ADC6

16K PM

(OPTIONAL

8K)

DATA MEMORY ADDRESS

SERIAL PORTS

SPORT 0SHIFTERMACALU

REF

ANALOG FRONT END

(OPTIONAL

SPORT 1

SERIAL PORT

ADC3

16K DM

8K)

SPORT 2

SECTION

PROGRAMMABLE

I/O

AND

FLAGS

TIMER

AD73460

FULL MEMORY

MODE

EXTERNAL

ADDRESS

BUS

EXTERNAL

DATA

BUS

BYTE DMA

CONTROLLER

Figure 1. Functional Block Diagram

Figure 1 is an overall block diagram of the AD73460. The pro­cessor section contains three independent computational units:
the ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provi­sions to support multiprecision computations. The ALU performs
a standard set of arithmetic and logic operations; division primi­tives are also supported. The MAC performs single-cycle multiply,
multiply/add and multiply/subtract operations with 40 bits of
accumulation. The shifter performs logical and arithmetic shifts,
normalization, denormalization, and derive exponent operations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.

A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu­tational units. The sequencer supports conditional jumps,
sub routine calls and returns in a single cycle. With internal
loop counters and loop stacks, the AD73460 executes looped
code with zero overhead; no explicit jump instructions are
required to maintain loops.

Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.

The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.

An interface to low-cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.

The AD73460 can respond to eleven interrupts. There can be
up to six external interrupts (one edge-sensitive, two level-sensitive
and three configurable) and seven internal interrupts generated
by the timer, the serial ports (SPORTs), the Byte DMA port
and the power-down circuitry. There is also a master RESET
signal. The two serial ports provide a complete synchronous
serial interface with optional companding in hardware and a
wide variety of framed or frameless data transmit and receive
modes of operation.

ANALOG FRONT END

The analog front end (AFE) of the AD73460 is configured as a
separate block that is normally connected to either SPORT0 or
SPORT1 of the DSP section. As it is not hardwired to either
SPORT users have total flexibility in how they wish to allocate
system resources to support the AFE. It is also possible to
further expand the number of analog input channels connected
to the SPORT by cascading an AD73360 device external to
the AD73460.

The AFE is configured as six input channels. It comprises six
independent encoder channels each featuring signal condition­ing, programmable gain amplifier, sigma-delta A/D convertor
and decimator sections. Each of these sections is described in
further detail below. All channels share a common internal
reference whose nominal value is 1.25 V. Figure 2 shows a block
diagram of the AFE section of the AD73460. It shows six input
channels along with a common reference. Communication to all
channels is handled by the SPORT2 block which interfaces to
either SPORT0 or SPORT1 of the DSP section.

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