ANALOG DEVICES AD7329 Service Manual

1 MSPS, 8-Channel, Software-Selectable,

–

True Bipolar Input, 12-Bit Plus Sign ADC

FEATURES

12-bit plus sign SAR ADC True bipolar input ranges Software-selectable input ranges

±10 V, ±5 V, ±2.5 V, 0 V to +10 V 1 MSPS throughput rate Eight analog input channels with channel sequencer Single-ended true differential and pseudo differential

analog input capability High analog input impedance

and ADCIN pins allow separate access to mux and ADC

MUX

OUT

Low power: 21 mW Temperature indicator Full power signal bandwidth: 20 MHz Internal 2.5 V reference High speed serial interface iCMOS™ process technology 24-lead TSSOP package Power-down modes

GENERAL DESCRIPTION

The AD73291 is an 8-channel, 12-bit plus sign successive approximation ADC designed on the iCMOS (industrial CMOS) process. iCMOS is a process combining high voltage CMOS and low voltage CMOS. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts could achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can accept bipolar input signals while providing increased performance, dramatically reduced power consumption, and reduced package size.

The AD7329 can accept true bipolar analog input signals. The AD7329 has four software-selectable input ranges, ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V. Each analog input channel can be independently programmed to one of the four input ranges. The analog input channels on the AD7329 can be programmed to be single-ended, true differential, or pseudo differential.

The ADC contains a 2.5 V internal reference. The AD7329 also allows for external reference operation. If a 3 V reference is applied to the REF

IN

/REF bipolar ±12 V analog input. The ADC has a high speed serial interface that can operate at throughput rates up to 1 MSPS.

pin, the AD7329 can accept a true

OUT

AD7329

FUNCTIONAL BLOCK DIAGRAM

MUX

VIN0

V

+MUX

OUT

1

IN

2

IN

3

4

5

6

7

I/P

MUX

CHANNEL

SEQUENCER

OUT

AD7329

ADCIN– ADCIN+

V

T/H

SS

Figure 1.

PRODUCT HIGHLIGHTS

1. The AD7329 can accept true bipolar analog input signals,

±10 V, ±5 V, ±2.5 V, and 0 V to +10 V unipolar signals.

2. The eight analog inputs can be configured as eight single-

ended inputs, four true differential input pairs, four pseudo differential inputs, or seven pseudo differential inputs.

3. 1 MSPS serial interface. SPI®-/QSPI™-/DSP-/MICROWIRE™-

compatible interface.

4. Low power, 21 mW, at 1 MSPS.

5. MUX

the mux output prior to entering the ADC.

Table 1. Similar Devices

Device Number Throughput Rate Number of Channels

AD7328 1000 kSPS 8 AD7327 500 kSPS 8 AD7324 1000 kSPS 4 AD7323 500 kSPS 4 AD7322 1000 kSPS 2 AD7321 500 kSPS 2

1

Protected by U.S. Patent No. 6,731,232.

and ADCIN pins allow for signal conditioning of

OUT

REFIN/REF

DD

2.5V

VREF

13-BIT SUCCESSIVE

OUT

APPROXIMAT ION

ADC

CONTROL LOGIC AND REGISTERS

AGNDV

V

CC

DOUT

SCLK

CS

DIN

V

DRIVE

05402-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD7329

REVISION HISTORY

4/06—Revision 0: Initial Version

Microprocessor Interfacing........................................................... 36

AD7329 to ADSP-21xx.............................................................. 36

AD7329 to ADSP-BF53x........................................................... 36

Outline Dimensions....................................................................... 37

Ordering Guide .......................................................................... 37

Rev. 0 | Page 2 of 40

AD7329

SPECIFICATIONS

VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 4.75 V to 5.25 V, V

= 1 MSPS, TA = T

MHz, f

S

directly to ADC

−, which is connected to GND for single-ended mode.

IN

MAX

to T

, unless otherwise noted. MUX

MIN

Table 2.

B Version Parameter1 Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE f

Signal-to-Noise Ratio (SNR)

2

76 77 dB Differential mode

72.5 74 dB Single-ended/pseudo differential mode Signal-to-Noise + Distortion

(SINAD)

2

75 76.5 dB Differential mode; ±2.5 V and ±5 V ranges

76.5 dB Differential mode; 0 V to +10 V and ±10 V ranges 72 73.5 dB

73.5 dB

Total Harmonic Distortion (THD)2 −87 −80 dB Differential mode; ±2.5 V and ±5 V ranges

−85 dB Differential mode; 0 V to +10 V and ±10 V ranges

−82 −77 dB

−80 dB

Peak Harmonic or Spurious

Noise (SFDR)

2

−88 −80 dB Differential mode; ±2.5 V and ±5 V ranges

−86 dB Differential mode; 0 V to +10 V and ±10 V ranges

−84 −78 dB

−82 dB

Intermodulation Distortion

2

(IMD)

fa = 50 kHz, fb = 30 kHz

Second-Order Terms −88 dB Third-Order Terms Aperture Delay Aperture Jitter Common-Mode Rejection

(CMRR)

2

Channel-to-Channel Isolation

Full Power Bandwidth

3

−90 dB 7 ns 50 ps

−79 dB Up to 100 kHz ripple frequency; see

2

−75 dB

20 MHz At 3 dB

1.5 MHz At 0.1 dB

= 2.7 V to 5.25 V, V

DRIVE

+ is connected directly to ADCIN+ and MUX

OUT

= 50 kHz sine wave

IN

= 2.5 V internal/external, f

REF

Single-ended/pseudo differential mode; ±2.5 V and ±5 V ranges

Single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges

Single-ended/pseudo differential mode; ±2.5 V and ±5 V ranges

Single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges

Single-ended/pseudo differential mode; ±2.5 V and ±5 V ranges

Single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges

on unselected channels up to 100 kHz;

f

IN

Figure 14

see

SCLK

−is connected

OUT

Figure 17

= 20

Rev. 0 | Page 3 of 40

AD7329

B Version Parameter1 Min Typ Max Unit Test Conditions/Comments

DC ACCURACY4

Resolution 13 Bits No Missing Codes

12-bit

Bits Differential mode

plus sign 11-bit

Bits Single-ended/pseudo differential mode

plus sign

Integral Nonlinearity

2

±1.1 LSB Differential mode ±1 LSB Single-ended/pseudo differential mode

−0.7/+1.2 LSB

Differential Nonlinearity2 −0.9/+1.5 LSB

±0.9 LSB

−0.7/+1 LSB

Offset Error

2, 5

−4/+9 LSB Single-ended/pseudo differential mode

−7/+10 LSB Differential mode Offset Error Match

2, 5

±0.6 LSB Single-ended/pseudo differential mode ±0.5 LSB Differential mode Gain Error

2, 5

±8.0 LSB Single-ended/pseudo differential mode ±14 LSB Differential mode Gain Error Match

2, 5

±0.5 LSB Single-ended/pseudo differential mode ±0.5 LSB Differential mode Positive Full-Scale Error

2, 6

±4 LSB Single-ended/pseudo differential mode ±7 LSB Differential mode Positive Full-Scale Error Match

2, 6

±0.5 LSB Single-ended/pseudo differential mode ±0.5 LSB Differential mode Bipolar Zero Error

2, 6

±8.5 LSB Single-ended/pseudo differential mode ±7.5 LSB Differential mode Bipolar Zero Error Match

2, 6

±0.5 LSB Single-ended/pseudo differential mode ±0.5 LSB Differential mode Negative Full-Scale Error

2, 6

±4 LSB Single-ended/pseudo differential mode ±6 LSB Differential mode Negative Full-Scale Error Match

2, 6

±0.5 LSB Single-ended/pseudo differential mode

±0.5 LSB Differential mode

All dc accuracy specifications are typical for 0 V to 10 V mode.

Single-ended/pseudo differential mode (LSB = FSR/8192)

Differential mode; guaranteed no missing codes to 13 bits

Single-ended mode; guaranteed no missing codes to 12 bits

Single-ended/psuedo differential mode (LSB = FSR/8192)

Rev. 0 | Page 4 of 40

AD7329

B Version Parameter1 Min Typ Max Unit Test Conditions/Comments

ANALOG INPUT

Input Voltage Ranges Reference = 2.5 V; see Table 6

(Programmed via Range

±10 V V

Register) ±5 V VDD = 5 V min, VSS = −5 V min, VCC = 2.7 V to 5.25 V ±2.5 V VDD = 5 V min, VSS = − 5 V min, VCC = 2.7 V to 5.25 V 0 to 10 V VDD = 10 V min, VSS = AGND min, VCC = 2.7 V to 5.25 V

Pseudo Differential VIN−

Input Range ±3.5 V Reference = 2.5 V; range = ±10 V ±6 V Reference = 2.5 V; range = ±5 V ±5 V Reference = 2.5 V; range = ±2.5 V +3/−5 V Reference = 2.5 V; range = 0 V to +10 V DC Leakage Current ±100 nA VIN = VDD or VSS 3 nA Per channel, VIN = VDD or VSS Input Capacitance3 16 pF When in track, all ranges, single ended ADCIN± Capacitance3 7 pF When in track, ±10 V range, single ended 10 pF When in track, ±5 V range, single ended

14.5 pF When in track, ±2.5 V range, single ended

10.5 pF When in track, 0 V to +10 V range, single ended

4.0 pF When in hold, all ranges, single ended MUX

− Capacitance3 7.5 pF All ranges, single ended

OUT

MUX

+ Capacitance3 13 pF All ranges, single ended

OUT

REFERENCE INPUT/OUTPUT

Input Voltage Range 2.5 3 V Input DC Leakage Current ±1 μA Input Capacitance 10 pF Reference Output Voltage 2.5 V Reference Output Voltage Error

±5 mV

@ 25°C

Reference Output Voltage

to T

MAX

T

MIN

Reference Temperature

±10 mV

25 ppm/°C

Coefficient 3 ppm/°C Reference Output Impedance 7 Ω

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V

2.4 V

INH

0.8 V VCC = 4.75 V to 5.25 V

INL

0.4 V VCC = 2.7 to 3.6 V Input Current, IIN ±1 μA V Input Capacitance, C

3

IN

10 pF

LOGIC OUTPUTS

Output High Voltage, VOH

V

DRIVE

V I

−

0.2 V Output Low Voltage, VOL 0.4 V I Floating-State Leakage Current ±1 μA Floating-State Output

Capacitance

3

5 pF

Output Coding Straight natural binary Coding bit set to 1 in control register

Twos complement Coding bit set to 0 in control register

= 10 V min, VSS = −10 V min, VCC = 2.7 V to 5.25 V

DD

= 16.5 V, VSS = −16.5 V, VCC = 5 V; see Figure 43 and

V

DD

Figure 44

= 0 V or V

IN

= 200 μA

SOURCE

= 200 μA

SINK

DRIVE

Rev. 0 | Page 5 of 40

AD7329

B Version Parameter1 Min Typ Max Unit Test Conditions/Comments

CONVERSION RATE

Conversion Time 800 ns 16 SCLK cycles with SCLK = 20 MHz Track-and-Hold Acquisition

2, 3

Time

300 ns Full-scale step input; see the

Throughput Rate 1 MSPS See the Serial Interface section; VCC = 4.75 V to 5.25 V 770 kSPS VCC < 4.75 V POWER REQUIREMENTS Digital inputs = 0 V or V

VDD 12 16.5 V See Table 6

VSS −12 −16.5 V See Tab le 6

VCC 2.7 5.25 V See Table 6; typical specifications for VCC < 4.75 V

V

2.7 5.25 V

DRIVE

Normal Mode (Static) 0.9 mA VDD= 16.5, VSS = −16.5 V, VCC = V

Normal Mode (Operational) f

SAMPLE

= 1 MSPS IDD 360 μA VDD = 16.5 V ISS 410 μA VSS = −16.5 V ICC and I

Autostandby Mode (Dynamic) f

3.2 mA VCC = V

DRIVE

SAMPLE

= 5.25 V

DRIVE

= 250 kSPS IDD 200 μA VDD = 16.5 V ISS 210 μA VSS = −16.5 V ICC and I

1.3 mA VCC = V

DRIVE

= 5.25 V

Autoshutdown Mode (Static) SCLK on or off

IDD 1 μA VDD = 16.5 V ISS 1 μA VSS = −16.5 V ICC and I

1 μA VCC = V

DRIVE

= 5.25 V

Full Shutdown Mode SCLK on or off

IDD 1 μA VDD = 16.5 V ISS 1 μA VSS = −16.5 V ICC and I

1 μA VCC = V

DRIVE

= 5.25 V

POWER DISSIPATION

Normal Mode (Operational) 30 mW VDD = 16.5 V, VSS = −16.5 V, VCC = 5.25 V 21 mW VDD = 12 V, VSS = −12 V, VCC = 5 V Full Shutdown Mode 38.25 μW VDD = 16.5 V, VSS = −16.5 V, VCC = 5.25 V

1

Temperature range is −40°C to +85°C.

2

See the Terminology section.

3

Sample tested during initial release to ensure compliance.

4

For dc accuracy specifications, the LSB size for differential mode is FSR/8192. For single-ended mode/pseudo differential mode, the LSB size is FSR/4096, unless

otherwise noted.

5

Unipolar 0 V to 10 V range with straight binary output coding.

6

Bipolar range with twos complement output coding.

Terminology section

DRIVE

= 5.25 V

DRIVE

Rev. 0 | Page 6 of 40

AD7329

TIMING SPECIFICATIONS

VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 4.75 V to 5.25 V, V

. Timing specifications apply with a 32 pF load, unless otherwise noted. MUX

T

MIN

connected directly to ADC

−, which is connected to GND for single-ended mode.

IN

Table 3.

Limit at T

MIN

, T

MAX

Description

Parameter VCC < 4.75 V VCC = 4.75 V to 5.25 V Unit V

f

SCLK

50 50 kHz min 14 20 MHz max t

CONVER T

t

75 60 ns min

QUIET

t

1

t

2

16 × t

SCLK

ns max t

SCLK

12 5 ns min

25 20 ns min 45 35 ns min Unipolar input range (0 V to 10 V)

t

3

t

4

t5 0.4 × t t6 0.4 × t t

7

t

8

26 14 ns max

57 43 ns max Data access time after SCLK falling edge

SCLK

0.4 × t

SCLK

0.4 × t

SCLK

ns min SCLK high pulse width

SCLK

ns min SCLK low pulse width

13 8 ns min SCLK to data valid hold time

40 22 ns max SCLK falling edge to DOUT high impedance 10 9 ns min SCLK falling edge to DOUT high impedance t

9

t

10

t

POWER-UP

1

When using VCC = 4.75 V to 5.25 V and the 0 V to 10 V unipolar range, running at 1 MSPS throughput rate with t2 at 20 ns, the mark space ratio needs to be limited to 50:50.

4 4 ns min DIN set-up time prior to SCLK falling edge

2 2 ns min DIN hold time after SCLK falling edge

750 750 ns max Power-up from autostandby

500 500 μs max

25 25 μs typ

CS

t

CONVERT

t

6

t

7

t

4

t

10

Figure 2. Serial Interface Timing Diagram

SCLK

DOUT

DIN

THREE-

STATE

t

2

12345 13141516

3 IDENTIFICATION BITS

t

3

ADD1

ADD2

WRITE

ADD0 SIGN DB11 DB10 DB2 DB1 DB0

t

9

REG

SEL1

SEL2

= 2.7 V to 5.25 V, V

DRIVE

OUT

≤ VCC

DRIVE

SCLK

= 1/f

SCLK

+ is connected directly to ADCIN+ and MUX

= 2.5 V internal/external, TA = T

REF

MAX

OUT

to

−is

Minimum time between end of serial read and next falling edge of CS Minimum CS

to SCLK set-up time; bipolar input ranges (±10 V, ±5 V, ±2.5 V)

CS

Delay from CS

pulse width

until DOUT three-state disabled

Power-up from full shutdown/autoshutdown mode, internal reference

Power-up from full shutdown/autoshutdown mode, external reference

t

1

t

5

LSB 0MSB

t

8

THREE-STATE

t

QUIET

05402-002

Rev. 0 | Page 7 of 40

AD7329

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted

Table 4.

Parameter Rating

VDD to AGND, DGND −0.3 V to +16.5 V VSS to AGND, DGND +0.3 V to −16.5 V VDD to VCC V

− 0.3 V to +16.5 V

CC

VCC to AGND, DGND −0.3 V to +7 V V

to AGND, DGND −0.3 V to +7 V

DRIVE

AGND to DGND −0.3 V to +0.3 V Analog Input Voltage to AGND1 V

− 0.3 V to VDD + 0.3 V

SS

Digital Input Voltage to DGND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to V

DRIVE

+ 0.3 V REFIN to AGND −0.3 V to VCC + 0.3 V Input Current to Any Pin

Except Supplies

2

±10 mA

Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TSSOP Package

θJA Thermal Impedance 128°C/W θJC Thermal Impedance 42°C/W

Pb-Free Temperature, Soldering

Reflow 260(0)°C

ESD 2.5 kV

1

If the analog inputs are being driven from alternative VDD and VSS supply

circuitry, Schottky diodes should be placed in series with the AD7329’s VDD and VSS supplies.

2

Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 8 of 40

AD7329

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

REFIN/REF

ADC

MUX

DIN

DGND

AGND

OUT

V

OUT

V

CS

SS

IN

+

0

10

1

4

11

12

5

1

2

3

4

AD7329

5

TOP VIEW

(Not to Scale)

6

7

8

9

24

23

22

21

20

19

18

17

16

15

14

13

SCLK

DGND

DOUT

V

DRIVE

V

CC

V

DD

ADCIN–

MUX

OUT

V

2

IN

3

V

IN

6

V

IN

7

V

IN

–

05402-003

Figure 3. TSSOP Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Descriptions

24 SCLK

Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the AD7329. This clock is also used as the clock source for the conversion process.

22 DOUT

Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The data stream consists of three channel identification bits, the sign bit, and 12 bits of conversion data. The data is

Serial Interface section).

1

provided MSB first (see the

Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the

CS

AD7329 and frames the serial data transfer.

2 DIN

Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the register on the falling edge of SCLK (see the Registers section).

21 V

3, 23 DGND

DRIVE

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. This pin should be decoupled to DGND. The voltage at this pin can be different than that at V not exceed V

by more than 0.3 V.

CC

but should

CC

Digital Ground. Ground reference point for all digital circuitry on the AD7329. The DGND and AGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

4 AGND

Analog Ground. Ground reference point for all analog circuitry on the AD7329. All analog input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

5 REFIN/REF

Reference Input/Reference Output. The on-chip reference is available on this pin for use external to the

OUT

AD7329. Alternatively, the internal reference can be disabled and an external reference applied to this input. On power up, this is the default condition. The nominal internal reference voltage is 2.5 V, which appears at

Reference section).

20 VCC

this pin. A 680 nF capacitor should be placed on the reference pin (see the Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7329. This supply

should be decoupled to AGND. 19 VDD Positive Power Supply Voltage. This is the positive supply voltage for the analog input section. 6 VSS Negative Power Supply Voltage. This is the negative supply voltage for the analog input section. 7 ADCIN+

Positive ADC Input. This pin allows access to the on-chip track-and-hold. The voltage applied to this pin is still

a high voltage signal (±10 V, ±5 V, ±2.5 V, or 0 V to +10 V). 8 MUX

OUT

+

Positive Multiplexer Output. The output of the multiplexer appears at this pin. The voltage at this pin is still a

high voltage signal equivalent to the voltage applied to the V

+ input channel, as selected in the control

IN

register or sequence register. If no external filtering or buffering is required, this pin should be tied to the

ADCIN+ pin.

Rev. 0 | Page 9 of 40

AD7329

Pin No. Mnemonic Descriptions

17 MUX

18 ADCIN−

9 to 16 VIN0 to VIN7

OUT

−

Negative Multiplexer Output. This pin allows access to the on-chip track-and-hold. The voltage applied to this pin is still a high voltage signal when the AD7329 is in differential mode. When the AD7329 is in single-ended mode, this signal is AGND, and MUX pseudo differential mode, a small dc voltage appears at this pin, and this pin should be tied to the ADC

Negative ADC Input. This pin allows access to the track-and-hold. When the AD7329 is in single-ended mode, this pin can be tied to MUX mode, this pin should be connected to MUX applied to this pin is a high voltage signal (±10 V, ±5 V, ±2.5 V, or 0 V to +10 V).

Analog Input 0 Through Analog Input 7. The analog inputs are multiplexed into the on-chip track-and-hold. The analog input channel for conversion is selected by programming the channel address bits, ADD2 through ADD0, in the control register. The inputs can be configured as eight single-ended inputs, four true differential input pairs, four pseudo differential inputs, or seven pseudo differential inputs. The configuration of the analog inputs is selected by programming the mode bits, Mode 1 and Mode 0, in the control register. The input range on each input channel is controlled by programming the range registers. Input ranges of ±10 V, ±5 V, ±2.5 V, or 0 V to +10 V can be selected on each analog input channel (see the section). On power up, V

− can be connected directly to the ADCIN− pin. When the AD7329 is in

OUT

−, which is connected to AGND. When the AD7329 is in pseudo differential

OUT

−. When the AD7329 is in true differential mode, the voltage

OUT

Range Registers

0 is automatically selected and the voltage on this pin appears on MUX

IN

OUT

IN

+.

− pin.

Rev. 0 | Page 10 of 40

AD7329

TYPICAL PERFORMANCE CHARACTERISTICS

1.0 VCC = V

0.8

T

= 25°C

A

V

DD

0.6

0.4

0.2

0

–0.2

INL ERROR (L SB)

–0.4

–0.6

–0.8

–1.0

0 8192

512 1536 2560 3584 4608 5632 6656 7680

= 5V

DRIVE

= 15V, VSS = –15V

1024 2048 3072 4096 5120 6144 7168

INT/EXT 2.5V REFERENCE ±10V RANGE +INL = +0.55LSB –INL = –0.68L SB

CODE

Figure 7. Typical INL True Differential Mode

05402-007

SNR (dB)

–20

–40

–60

–80

–100

–120

–140

0

50 100 150 200 250 300 350 400 450

FREQUENCY (kHz)

4096 POINT FFT V

= V

CC

= 15V, VSS = –15V

V

DD

= 25°C

T

A

INT/EXT 2.5V REFERE NCE ±10V RANGE

f

= 50kHz

IN

SNR = 77.30dB SINAD = 76.85dB THD = –86.96dB SFDR = –88.22d B

Figure 4. FFT True Differential Mode

DRIVE

= 5V

500

05402-004

SNR (dB)

–20

–40

–60

–80

–100

–120

–140

0

50 100 150 200 250 300 350 400 450

FREQUENCY (kHz)

4096 POINT FFT

= V

V

CC

V

DD

T

A

INT/EXT 2.5V REFERE NCE ±10V RANGE

f

IN

SNR = 74.67dB SINAD = 74.03dB THD = –82.68dB SFDR = –85.40d B

= 5V

DRIVE

= 15V, VSS = –15V

= 25°C

= 50kHz

Figure 5. FFT Single-Ended Mode

1.0

0.8

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 8192

1024 2048 3072 4096 5120 6144 7168

512 1536 2560 3584 4608 5632 6656 7680

VCC = V

DRIVE

T

= 25°C

A

V

= 15V, VSS = –15V

DD

INT/EXT 2.5V REFERENCE ±10V RANGE +DNL = +0.72LSB –DNL = –0.22LSB

CODE

= 5V

Figure 6. Typical DNL True Differential Mode

500

1.0

0.8

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

VCC = V

–0.6

T

= 25°C

A

V

–0.8

DD

INT/EXT 2.5V REFERE NCE

–1.0

0 8192

05402-005

512 1536 2560 3584 4608 5632 6656 7680

= 5V

DRIVE

= 15V, VSS = –15V

1024 2048 3072 4096 5120 6144 7168

±10V RANGE +DNL = +0.79LSB –DNL = –0.38L SB

CODE

05402-008

Figure 8. Typical DNL Single-Ended Mode

1.0

0.8

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 8192

1024 2048 3072 4096 5120 6144 7168

05402-006

512 1536 2560 3584 4608 5632 6656 7680

VCC = V

DRIVE

T

= 25°C

A

V

= 15V, VSS = –15V

DD

INT/EXT 2.5V REFERENCE ±10V RANGE +INL = +0.87LSB –INL = –0.49L SB

CODE

= 5V

05402-009

Figure 9. Typical INL Single-Ended Mode

Rev. 0 | Page 11 of 40

AD7329

–

50

VCC= V V

DD

–55

T

A

f

= 1MSPS

S

–60

INTERNAL REFERENCE AD8021 BETWEEN MUX AND ADC

–65

–70

0V TO +10V RANG E

–75

THD (dB)

–80

–85

–90

–95

10

Figure 10. THD vs. Analog Input Frequency for Single-Ended Mode (SE) at 5 V V

50

VCC= V V

DD

–55

T

A

f

= 1MSPS

S

–60

INTERNAL REFERENCE AD8021 BETWEEN MUX AND ADCIN PINS

–65

–70

–75

0V TO +10V RANG E

THD (dB)

–80

–85

–90

–95

10

= 5V

DRIVE

= 12V, VSS = –12V

= 25°C

PINS

IN+

ANALOG INPUT FREQUENCY (kHz)

= 5V

DRIVE

= 12V, VSS = –12V

= 25°C

ANALOG INPUT FREQUENCY (kHz)

OUT+

OUT

100

±10V RANGE

±5V RANGE

±2.5V RANGE

±10V RANGE

±5V RANGE

±2.5V RANGE

1000

05402-010

CC

05402-011

Figure 11. THD vs. Analog Input Frequency for True Differential Mode (Diff) at

5 V V

CC

80

75

70

65

SINAD (dB)

60

VCC= V

DRIVE

= 12V, VSS = –12V

V

DD

= 25°C

T

A

f

= 1MSPS

S

55

INTERNAL REFERENCE AD8021 BETWEEN MUX AND ADCIN PINS

50

10

Figure 13. SINAD vs. Analog Input Frequency for True Differential Mode (Diff)

50

–55

–60

–65

–70

–75

–80

–85

–90

CHANNEL-TO -CHANNEL ISO LATION (dB)

–95

–100

0

100 200 300 400 500

±10V RANGE

= 5V

OUT

100

ANALOG INPUT FREQUENCY (kHz)

at 5 V V

CC

WIRE LINK

VDD = 12V, VSS = –12V

= V

V

CC

DRIVE

SINGLE-E NDED MODE 50kHz ON SELECT ED CHANNE L

f

= 1MSPS

S

= 25°C

T

A

FREQUENCY O F INPUT NO ISE (kHz)

±2.5V RANGE

±5V RANGE

0V TO +10V RANG E

WITH AD8021

= 5V

1000

600

05402-013

05402-014

Figure 14. Channel-to-Channel Isolation with and Without AD8021 Between

the MUX

+ and ADCIN + Pins

OUT

74

73

72

71

0V TO +10V RANG E

70

SINAD (dB)

69

VCC= V

= 12V, VSS = –12V

V

DD

68

= 25°C

T

A

f

= 1MSPS

S

INTERNAL REFERENCE

67

AD8021 BETWEEN MUX AND ADC

66

10

= 5V

DRIVE

PINS

IN+

ANALOG INPUT FREQUENCY (kHz)

±2.5V RANGE

OUT+

100

±5V RANGE

±10V RANGE

1000

05402-012

Figure 12. SINAD vs. Analog Input Frequency for Single-Ended Mode (SE) at 5 V V

CC

10k

9k

8k

7k

6k

5k

4k

3k

NUMBER OF OCCURRENCES

2k

1k

0

–2

228

–1012

9469

CODE

VCC = 5V

= 12V, VSS = –12V

V

DD

RANGE = ±10V 10k SAMPLES

= 25°C

T

A

303

Figure 15. Histogram of Codes, True Differential Mode

0

05402-015

Rev. 0 | Page 12 of 40

ANALOG DEVICES AD7329 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS