Analog Devices AD7324 pri Datasheet
4-Channel, Software Selectable True bipolar
Preliminary Technical Data
Input, 12-Bit Plus Sign ADC
AD7324*
FUNCTIONAL BLOCK DIAGRAM
FEATURES
• 12-Bit plus Sign SAR ADC
• True Bipolar Input Ranges
• Software Selectable Input Ranges
± 10V, ± 5V, ± 2.5V, 0 to 10V
• 1 MSPS Throughput Rate
• Four Analog Input Channels with Channel Sequencer
• Single Ended, True Differential and Pseudo Differential
Analog Input Capability
• High Analog Input Impedance
• Low Power:- 12 mW
• Full Power Signal Bandwidth: 7 MHz
• Internal 2.5 V Reference
• High Speed Serial Interface
• Power Down Modes
• 16-Lead TSSOP package
• iCMOS
• For eight and two channel equivalent devices see
TM
Process Technology
AD7328 and AD7322 respectively.
Figure 1.
PRODUCT HIGHLIGHTS
GENERAL DESCRIPTION
The AD7324 is a 4-Channel, 12-Bit plus Sign Successive
Approximation ADC. The ADC has a high speed serial interface
that can operate at throughput rates up to 1 Msps.
The AD7324 can accept true bipolar Analog Input signals. The
AD7324 has four software selectable inputs Ranges, ±10V, ±5V,
±2.5V and 0 to 10V. Each analog input channel can be
independently programmed to one of the four input ranges.
The Analog input channels on the AD7324 can be programmed
to be Single-Ended, true Differential or Pseudo Differential.
The AD7324 contains a 2.5V Internal reference. The AD7324
also allows for external Reference operation. If a 3V reference is
applied the REF
±12V Analog Input. Minimum V
pin the AD7324 can accept a true Bipolar
IN/OUT
and VSS supplies of ±12V are
DD
required for the ±12V Input Range.
* Protected by U.S. Patent No. 6,731,232
TM
Process Technology
iCMOS
For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher-voltage levels, iCMOS is a technology platform
that enables the development of analog ICs capable of 30V and operating at +/- 15V supplies while allowing dramatic reductions in power consumption and package size, and
increased AC and DC performance.
1. The AD7324 can accept True Bipolar Analog Input signals,
±10V, ±5V, ±2.5V and 0 to 10V unipolar signals.
2. The Four Analog Inputs can be configured as 4 Single-Ended
inputs, 2 True Differential, 2 Pseudo Differential or 3 Pseudo
Differential Inputs. The AD7324 has high Impedance Analog
Inputs.
3. The AD7324 features a High Speed Serial Interface.
Throughput Rates up to 1 MSPS can be achieved on the
AD7324.
4. Low Power, 26 mW at maximum throughput rate of 1 MSPS.
Device Number Number of Bits Number of Channels
AD7328 12-Bits Plus Sign 8
AD7322 12-Bits Plus Sign 2
Rev. PrI
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
www.analog.com
AD7324 Preliminary Technical Data
TABLE OF CONTENTS
AD7324—Specifications.................................................................. 3
Absolute Maximum Ratings............................................................ 6
Pin Functional Descriptions ....................................................... 7
Terminology ...................................................................................... 8
REVISION HISTORY
Revision PrI: Preliminary Version
Theory of Operation.....................................................................9
AD7324 Registers ........................................................................... 12
Serial interface ................................................................................ 20
OUTLINE DIMENSIONS.................................................................. 21
Rev. PrI| Page 2 of 21
AD7324 Preliminary Technical Data
AD7324—SPECIFICATIONS
Table 1. Unless otherwise noted, VDD = + 12V to +16.5V, VSS = -12V to –16.5V, VCC = 2.7V to 5.25V, V
2.5V Internal/External, f
Parameter Specification Units Test Conditions/Comments
DYNAMIC PERFORMANCE F
Signal to Noise Ratio (SNR)
Signal to Noise + Distortion (SINAD)2 75 dB min Differential Mode
71.5 dB min Single-Ended/Pseudo Differential Mode
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
2
(SFDR)
Intermodulation Distortion (IMD)
Second Order Terms -88 dB typ
Third Order Terms
Aperature Delay
Aperature Jitter2
2
Common Mode Rejection (CMRR)
Channel-to-Channel Isolation
Full Power Bandwidth
DC ACCURACY
Resolution 12+Sign Bits
Integral Nonlinearity
Differential Nonlinearity
Offset Error3 ±8 LSB max Unipolar Range with Straight Binary output coding
Offset Error Match2 ±0.5 LSB max
Gain Error
Gain Error Match
2
2
Positive Full-Scale Error
Positive Full Scale Error Match
Bipolar Zero Error
2
Bipolar Zero Error Match
Negative Full Scale Error2 ±4 LSB max
Negative Full Scale Error Match
ANALOG INPUT
Input Voltage Ranges
(Programmed via Range Register)
DC Leakage Current ±10 nA max
Input Capacitance 12 pF typ When in Track, ±10V Range
15 pF typ When in Track, ±5V, 0 to 10V Range
20 pF typ When in Track, ±2.5V Range
3 pF typ When in Hold
REFERENCE INPUT/OUTPUT
Input Voltage Range +2.5 to +3V V min to max
Input DC Leakage Current ±1 µA max
Input Capactiance 20 pF typ
Reference Output Voltage 2.49/2.51 Vmin/max
Reference Temperature Coefficient 25 ppm/°C max 10 ppm/°C typ
Reference Output Impedance 25
= 20 MHz, fS = 1 MSPS TA = T
SCLK
2
2
2
2
2
2
2
2
2
2
2
1
= 2.7V to 5.25V, V
DRIVE
to T
MAX
MIN
= 50 kHz Sine Wave
IN
76 dB min Differential Mode
72 dB min Single-Ended /Pseudo Differential Mode
-80 dB max
-80
F
dB max
= 40.1 kHz, Fb = 41.5 kHz
a
-88 dB typ
10 ns max
50 ps typ
2
TBD dB typ
-80 dB typ F
7
1.5
MHz typ
MHz typ
= 400 kHz
IN
@ 3 dB
@ 0.1 dB
±1.5 LSB max
± 0.95 LSB max Guaranteed No Missing Codes to 13-Bits
±6 LSB max
±0.6 LSB max
±3 LSB max Bipolar Range with Twos Complement Output Coding
±0.6 LSB max
±8 LSB max
±0.5 LSB max
±0.5 LSB max
±10V
±5V
±2.5V
0 to 10V
Volts V
= +10V min , VSS = -10V min, VCC = 2.7V to 5.25V
DD
V
= +5V min, VSS = -5V min, VCC = 2.7V to 5.25V
DD
V
= +5V min, VSS = - 5V min, VCC = 2.7V to 5.25V
DD
V
= +10V min, VSS = 0 V min, VCC = 2.7V to 5.25V
DD
See Table 5
Ω typ
REF
=
Rev. PrI | Page 3 of 21
AD7324 Preliminary Technical Data
Parameter Specification Units Test Conditions/Comments
LOGIC INPUTS
Input High Voltage, V
Input High Voltage, V
0.4 V max V
Input Current, IIN ± 1 µA max VIN = 0V or VCC
Input Capacitance, C
LOGIC OUTPUTS
Output High Voltage, VOH V
Output Low Voltage, VOL 0.4 V max I
Floating State Leakage Current ±1 µA max
Floating State Output Capacitance
Output Coding
CONVERSION RATE
Conversion Time 800 ns max 16 SCLK Cycles with SCLK = 20 MHz
Track-and-Hold Acquisition Time 200 ns max Sine Wave Input
200 ns max Full Scale Step input
Throughput Rate 1 MSPS max See Serial Interface section
POWER REQUIREMENTS Digital Inputs = 0V or VCC
4
V
DD
4
V
SS
V
CC
V
2.7V/5.25V V min/max
DRIVE
Normal Mode
IDD 300 µA max V
ISS 370 µA max V
ICC 2 mA max V
Auto-Standby Mode F
IDD TBD µA max
ISS TBD µA max
ICC 1.6 mA typ
Auto-Standby Mode F
IDD TBD µA max
ISS TBD µA max
ICC 1 mA typ
Full Shutdown Mode
IDD 0.9 µA max
ISS 0.9 µA max
ICC 0.9 µA max SCLK On or Off
POWER DISSIPATION
Normal Mode 26 mW max V
12 mW typ V
Full Shutdown Mode 35 µW max V
NOTES
1
Temperature ranges as follows: -40°C to +85°C
2
See Terminology
3
Guaranteed by Characterization
4
Functional from VDD = +4.75V and VSS = -4.75V
Specifications subject to change without notice.
2.4 V min
INH
0.8 V max V
INL
3
IN
10 pF max
- 0.2V V min I
DRIVE
3
10 pF max
Straight
Coding bit set to 1 in Control Register
= 4.75 to 5.25 V
CC
= 2.7 to 3.6 V
CC
= 200 µA
SOURCE
= 200 µA
SINK
Natural
Binary
Two’s
Coding bit set to 0 in Control Register
Complement
12V/+16.5V V min/max See Table 5
-12V/16.5V V min/max See Table 5
2.7V / 5.25V V min/max See Table 5
= +16.5V
DD
= -16.5V
SS
= 5.25V
CC
= TBD
SAMPLE
= TBD
SAMPLE
= +16.5V, VSS = -16.5V, V
DD
= +5V, VSS = -5V, V
DD
= +16.5V, VSS = -16.5V, V
DD
CC
= 5V,
= 5.25V,
CC
= 5.25V,
CC
Rev. PrI| Page 4 of 21
AD7324 Preliminary Technical Data
TIMING SPECIFICATIONS
Table 2. Unless otherwise noted,
2.5V Internal/External, T
Parameter Limit at T
f
SCLK
10 kHz min
20 MHz max
t
CONVERT
t
50 ns max
QUIET
16×t
t1 10 ns min
t
2
t
3
t
4
10 ns min
20 ns max
TBD ns max Data Access Time after SCLK Falling Edge.
t5 0.4t
t6 0.4t
t
7
t
8
10 ns min SCLK to Data Valid Hold Time
25 ns max SCLK Falling Edge to D
10 ns min SCLK Falling Edge to D
t
9
t
10
TBD ns min DIN set-up time prior to SCLK falling edge
5 ns min DIN hold time after SCLK falling edge
1 µs max Power up from Auto Standby
TBD µs max Power up from Full Shutdown/Auto Shutdown Mode
MIN
ns max T
SCLK
SCLK
ns min SCLK High Pulsewidth
SCLK
VDD = +12V to + 16.5V, VSS = -12V to –16.5V, V
= T
to T
MIN
Unit Description
SCLK
= 1/f
SCLK
Minimum Time between End of Serial Read and Next Falling Edge of CS
Minimum CS Pulse width
CS
to SCLK Setup Time
Delay from CS until D
ns min SCLK Low Pulsewidth
OUT
, T
A
MAX
MAX
=2.7V to 5.25, V
CC
Three-State Disabled
High Impedance
OUT
High Impedance
OUT
=2.7V to 5.25, V
DRIVE
REF
=
Rev. PrI | Page 5 of 21
Figure 2. Serial Interface timing Diagram
AD7324 Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 3. TA = 25°C, unless otherwise noted
VDD to AGND, DGND -0.3 V to +16.5 V
VSS to AGND, DGND +0.3 V to –16.5 V
VCC to AGND, DGND -0.3V to +7V
V
to VCC -0.3 V to VCC + 0.3V
DRIVE
AGND to DGND -0.3 V to +0.3 V
Analog Input Voltage to AGND
Digital Input Voltage to DGND -0.3 V to +7 V
Digital Output Voltage to GND -0.3 V to V
REFIN to AGND -0.3 V to VCC +0.3V
Input Current to Any Pin Except Supplies
Operating Temperature Range -40°C to +85°C
Storage Temperature Range -65°C to +150°C
Junction Temperature +150°C
TSSOP Package
θJA Thermal Impedance 143 °C/W
θJC Thermal Impedance 45 °C/W
Pb-free Temperature, Soldering
Reflow 260(+0)°C
ESD TBD
2
-0.5V to VDD +
V
SS
DRIVE
±10mA
0.5V
+0.3V
Rev. PrI | Page 6 of 21
AD7324 Preliminary Technical Data
Pin Functional Descriptions
CS
DIN
DGND
AGND
REFIN/OUT
V
SS
VIN0
VIN1
1
2
AD7324
3
4
5
TOP VIEW
6
7
8
(Not to
Scale)
SCLK
16
15
DGND
14
DOUT
V
13
DRIVE
V
12
CC
V
11
DD
VIN2
10
VIN3
9
Figure 3. AD7324 Pin Configuration TSSOP
Table 4. AD7324 Pin Function Descriptions
Pin Mnemonic Pin Number Description
SCLK 16
Serial Clock. Logic Input. A serial clock input provides the SCLK used for accessing the data
from the AD7324. This clock is also used as the clock source for the conversion process.
D
14
OUT
Serial Data Output. The conversion output data is supplied to this pin as a serial data stream.
The bits are clocked out on the falling edge of the SCLK input and 16 SCLKs are required to
access the data. The data stream consists of one leading zero followed by two channel
identification bits, followed by the sign bit followed by the 12 bits of conversion data. The data
is provided MSB first. See the Serial Interface section.
CS
1
Chip Select. Active low logic input. This input provides the dual function of initiating
conversions on the AD7324 and frames the serial data transfer.
DIN 2
Data In. Data to be written to the on-chip registers is provided on this input and is clocked into
the register on the falling edge of SCLK. See Register section.
AGND 4
Analog Ground. Ground reference point for all analog circuitry on the AD7324. All analog input
signals and any external reference signal should be referred to this AGND voltage.
REF
REF
IN/
5
OUT
Reference Input/ Reference Output pin. The on-chip reference is available on this pin for use
external to the AD7324. Alternativley, the internal reference can be disabled and an external
reference applied to this input. When using the AD7324 with an external reference, the
internal reference must be disabled via the control register. The nominal reference voltage is
2.5 V, which appears at the pin. A 470 nF decoupling capacitor sgould be placed on the
Reference pin.
VCC 12
Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the
AD7324. This supply should be decoupled to AGND.
VDD 11 Positive power supply voltage. This is the positive supply voltage for the Analog Input section.
VSS 6
Negative power supply voltage. This is the negavtive supply voltage for the Analog Input
section.
V
13 The voltage applied to this pin determines the voltage at which the serial interface operates.
DRIVE
DGND 3,15 This is the Digital Ground Connection.
Vin0-Vin3 7,8,9,10
Analog input 0 through Analog Input 3. The analog inputs are multiplexed into the on-chip
track-and-hold. The analog input channel for conversion is selected by programming the
channel address bits, ADD1 through ADD0, in the control register. The inputs can be
configured as 4 Single-Ended Inputs, 2 True Differential Input pairs, 2 Pseudo Differential
inputs or 3 Pseudo Differential Inputs. The configuration of the Analog inputs is selected by
programming the Mode bits, Mode1 and Mode0, in the Control Register. The input range on
each input channel is controlled by programming the range register. Input ranges of ±10V,
±5V, ±2.5V and 0 to 10V can be selected on each analog input channel. See Register section.
Rev. PrI | Page 7 of 21
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