Datasheet AD7323 Datasheet (ANALOG DEVICES)

500 kSPS, 4-Channel, Software-Selectable,

True Bipolar Input, 12-Bit Plus Sign ADC

FEATURES

12-bit plus sign SAR ADC True bipolar input ranges Software-selectable input ranges

±10 V, ±5 V, ±2.5 V, 0 V to +10 V 500 kSPS throughput rate Four analog input channels with channel sequencer Single-ended, true differential, and pseudo differential

analog input capability High analog input impedance Low power: 17 mW Full power signal bandwidth: 22 MHz Internal 2.5 V reference High speed serial interface Power-down modes 16-lead TSSOP package

™

iCMOS

GENERAL DESCRIPTION

process technology

FUNCTIONAL BLOCK DIAGRAM

AD7323

I/P

MUX

CHANNEL

SEQUENCER

AGND V

T/H

PRODUCT HIGHLIGHTS

2.5V

VREF

Figure 1.

REFIN/OUT

SUCCESSIVE

APPROXIMATION

CONTROL LO GIC AND REGISTE RS

DGND

AD7323

13-BIT

ADC

DOUT

SCLK

DIN

DRIVE

5400-001

The AD73231 is a 4-channel, 12-bit plus sign successive approximation ADC designed on the iCMOS (industrial CMOS) process. iCMOS is a process combining high voltage silicon with submicron CMOS and complementary bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts could achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can accept bipolar input signals while providing increased performance, dramatically reduced power consumption, and reduced package size.

The AD7323 can accept true bipolar analog input signals. The AD7323 has four software selectable input ranges, ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V. Each analog input channel can be independently programmed to one of the four input ranges. The analog input channels on the AD7323 can be programmed to be single-ended, true differential, or pseudo differential.

The ADC contains a 2.5 V internal reference. The AD7323 also allows for external reference operation. If a 3 V reference is applied to the REFIN/OUT pin, the AD7323 can accept a true bipolar ±12 V analog input. Minimum ±12 V V

and VSS

supplies are required for the ±12 V input range. The ADC has a high speed serial interface that can operate at throughput rates up to 500 kSPS.

1. The AD7323 can accept true bipolar analog input signals,

±10 V, ±5 V, ±2.5 V, and 0 V to +10 V unipolar signals.

2. The four analog inputs can be configured as four single-

ended inputs, two true differential input pairs, two pseudo differential inputs, or three pseudo differential inputs.

3. 500 kSPS serial interface. SPI®-/QSPI™-/DSP-/MICROWIRE™-

compatible interface.

4. Low power, 17 mW, at a maximum throughput rate of

500 kSPS.

5. Channel sequencer.

Table 1. Similar Devices

Device Number

Throughput Rate

Number of bits

Number of Channels

AD7329 1000 kSPS 12-bit plus sign 8 AD7328 1000 kSPS 12-bit plus sign 8 AD7327 500 kSPS 12-bit plus sign 8 AD7324 1000 kSPS 12-bit plus sign 4 AD7322 1000 kSPS 12-bit plus sign 2 AD7321 500 kSPS 12-bit plus sign 2

Protected by U.S. Patent No. 6,731,232.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD7323

TABLE OF CONTENTS

Features.............................................................................................. 1

Control Register ......................................................................... 23

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 10

Terminology .................................................................................... 14

Theory of Operation ...................................................................... 16

Circuit Information.................................................................... 16

Converter Operation.................................................................. 16

Analog Input Structure.............................................................. 17

Sequence Register....................................................................... 25

Range Register ............................................................................ 25

Sequencer Operation ..................................................................... 26

Reference ..................................................................................... 28

............................................................................................ 28

DRIVE

Modes of Operation ....................................................................... 29

Normal Mode.............................................................................. 29

Full Shutdown Mode.................................................................. 29

Autoshutdown Mode................................................................. 30

Autostandby Mode..................................................................... 30

Power vs. Throughput Rate....................................................... 31

Serial Interface ................................................................................ 32

Microprocessor Interfacing........................................................... 33

AD7323 to ADSP-21xx.............................................................. 33

AD7323 to ADSP-BF53x........................................................... 33

Typical Connection Diagram ................................................... 19

Analog Input............................................................................... 19

Driver Amplifier Choice............................................................ 21

Registers........................................................................................... 22

Addressing Registers.................................................................. 22

REVISION HISTORY

1/06—Revision 0: Initial Version

Application Hints ........................................................................... 34

Layout and Grounding .............................................................. 34

Outline Dimensions....................................................................... 35

Ordering Guide .......................................................................... 35

Rev. 0 | Page 2 of 36

AD7323

SPECIFICATIONS

VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 2.7 V to 5.25 V, V f

= 10 MHz, fS = 500 kSPS, TA = T

SCLK

MAX

to T

, unless otherwise noted.

MIN

Table 2.

B Version Parameter

Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE F

Signal-to-Noise Ratio (SNR)

76 dB Differential mode, VCC = 4.75 V to 5.25 V

75.5 dB Differential mode, VCC < 4.75 V

72.5 dB

72 dB

Signal-to-Noise + Distortion

(SINAD)

75 dB Differential mode; ±2.5 V and ±5 V ranges

74 Differential mode; 0 V to 10 V 76 dB Differential mode; ±10 V range 72 dB

72.5 dB

Total Harmonic Distortion (THD)2 −80 dB Differential mode; ±2.5 V and ±5 V ranges

−79 dB Differential mode; 0 V to 10 V ranges

−82 dB Differential mode; ±10 V range

−77 dB Single-ended/pseudo differential mode; ±5 V range

−79 dB Single-ended/pseudo differential mode; ±2.5 V range

−80 dB

Peak Harmonic or Spurious Noise

(SFDR)

−81 dB Differential mode; ±2.5 V and ±5 V ranges

−80 dB Differential mode; 0 V to 10 V ranges

−82 dB Differential mode; ±10 V ranges

−78 dB Single-ended/pseudo differential mode; ±5 V range

−80 Single-ended/pseudo differential mode; ±2.5 V range

−79 dB

Intermodulation Distortion (IMD)2 fa = 50 kHz, fb = 30 kHz Second-Order Terms −88 dB Third-Order Terms Aperture Delay Aperture Jitter Common-Mode Rejection

(CMRR)

Channel-to-Channel Isolation Full Power Bandwidth

−90 dB 7 ns 50 ps

−79 dB Up to 100 kHz ripple frequency; see Figure 17

−72 dB FIN on unselected channels up to 100 kHz; see Figure 14 22 MHz At 3 dB

5 MHz At 0.1 dB

= 2.7 V to 5.25 V, V

DRIVE

= 2.5 V to 3.0 V internal/external,

REF

= 50 kHz sine wave

Single-ended/pseudo differential mode; ±10 V, ±2.5 V and ±5 V ranges, V

= 4.75 V to 5.25 V

Single-ended/pseudo differential mode ; 0 V to 10 V

= 4.75 V to 5.25 V and all ranges at VCC < 4.75 V

Single-ended/pseudo differential mode; ±2.5 V and ±5 V ranges

Single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges

Rev. 0 | Page 3 of 36

AD7323

B Version Parameter

DC ACCURACY

Resolution 13 Bits No Missing Codes

Integral Nonlinearity

−0.7/+1.2 LSB

Differential Nonlinearity

±0.9 LSB

−0.7/+1 LSB

Offset Error

−7/+10 LSB Differential mode Offset Error Match ±0.5 LSB Differential mode Gain Error ±14 LSB Differential mode Gain Error Match ±0.5 LSB Differential mode Positive Full-Scale Error ±7 LSB Differential mode Positive Full-Scale Error Match ±0.5 LSB Differential mode Bipolar Zero Error ±7.5 LSB Differential mode Bipolar Zero Error Match ±0.5 LSB Differential mode Negative Full-Scale Error ±6 LSB Differential mode Negative Full-Scale Error Match

±0.5 LSB Differential mode

Min Typ Max Unit Test Conditions/Comments

12-bit

Bits Differential mode

plus sign 11-bit

Bits Single-ended/pseudo differential mode

plus sign

±1.1 LSB Differential mode; VCC = 3 V to 5.25 V, typ for VCC = 2.7 V ±1 LSB

Single-ended/pseudo differential mode, V

5.25 V, typ for V

= 2.7 V

= 3 V to

Single-ended/pseudo differential mode (LSB = FSR/8192)

−0.9/+1.2 LSB

Differential mode; guaranteed no missing codes to 13 bits

Single-ended mode; guaranteed no missing codes to 12 bits

Single-ended/psuedo differential mode (LSB = FSR/8192)

2, 5

2, 6

−4/+9 LSB Single-ended/pseudo differential mode

±0.6 LSB Single-ended/pseudo differential mode

±8 LSB Single-ended/pseudo differential mode

±0.5 LSB Single-ended/pseudo differential mode

±4 LSB Single-ended/pseudo differential mode

2, 6

±0.5 LSB Single-ended/pseudo differential mode

±8.5 LSB Single-ended/pseudo differential mode

±0.5 LSB Single-ended/pseudo differential mode

±4 LSB Single-ended/pseudo differential mode

2, 6

±0.5 LSB Single-ended/pseudo differential mode

Rev. 0 | Page 4 of 36

AD7323

B Version Parameter

ANALOG INPUT

Input Voltage Ranges Reference = 2.5 V; see Table 6

±5 V VDD = 5 V min, VSS = −5 V min, VCC = 2.7 V to 5.25 V ±2.5 V VDD = 5 V min, VSS = −5 V min, VCC = 2.7 V to 5.25 V 0 to 10 V VDD = 10 V min, VSS = AGND min, VCC = 2.7 V to 5.25 V

±3.5 V Reference = 2.5 V; range = ±10 V ±6 V Reference = 2.5 V; range = ±5 V ±5 V Reference = 2.5 V; range = ±2.5 V +3/−5 V Reference = 2.5 V; range = 0 V to +10 V DC Leakage Current ±80 nA VIN = VDD or VSS 3 nA Per input channel, VIN = VDD or VSS Input Capacitance

16.5 pF When in track, ±5 V and 0 V to +10 V ranges

21.5 pF When in track, ±2.5 V range 3 pF When in hold, all ranges REFERENCE INPUT/OUTPUT

Input Voltage Range 2.5 3 V Input DC Leakage Current ±1 μA Input Capacitance 10 pF Reference Output Voltage 2.5 V Reference Output Voltage Error

Reference Output Voltage

Reference Temperature

3 ppm/°C Reference Output Impedance 7 Ω

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V

0.4 V VCC = 2.7 to 3.6 V Input Current, IIN ±1 μA V Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, VOH

Output Low Voltage, VOL 0.4 V I Floating-State Leakage Current ±1 μA Floating-State Output

Output Coding Straight natural binary Coding bit set to 1 in control register Twos complement Coding bit set to 0 in control register CONVERSION RATE

Conversion Time 1.6 μs 16 SCLK cycles with SCLK = 10 MHz

Track-and-Hold Acquisition

Throughput Rate 500 kSPS See the Serial Interface section

(Programmed via Range

Pseudo Differential VIN(−)

Input Range

@ 25°C

to T

MAX

MIN

Coefficient

2.4 V

INH

0.8 V VCC = 4.75 V to 5.25 V

INL

Capacitance

Time

2, 3

Min Typ Max Unit Test Conditions/Comments

±10 V V

= 10 V min, VSS = −10 V min, VCC = 2.7 V to 5.25 V

= 16.5 V, VSS = −16.5 V, VCC = 5 V; see Figure 40 and

Figure 41

13.5 pF When in track, ±10 V range

±5 mV

±10 mV

25 ppm/°C

= 0 V or V

DRIVE

10 pF

DRIVE

V I

−

SOURCE

= 200 μA

0.2 V = 200 μA

SINK

5 pF

305 ns Full-scale step input; see the Terminology section

Rev. 0 | Page 5 of 36

AD7323

B Version Parameter

POWER REQUIREMENTS Digital inputs = 0 V or V

V VSS −12 −16.5 V See Ta ble 6 VCC 2.7 5.25 V See Table 6 V Normal Mode (Static) 0.9 mA VDD/VSS = ±16.5 V, VCC/V Normal Mode (Operational) f

Autostandby Mode (Dynamic) f

Autoshutdown Mode (Static) SCLK on or off

Full Shutdown Mode SCLK on or off

POWER DISSIPATION

Normal Mode (Operational) 17 mW VDD = 16.5 V, VSS = −16.5 V, VCC = 5.25 V Full Shutdown Mode 38.25 μW VDD = 16.5 V, VSS = −16.5 V, VCC = 5.25 V

Temperature range is −40°C to +85°C.

See the Terminology section.

Sample tested during initial release to ensure compliance.

For dc accuracy specifications, the LSB size for differential mode is FSR/8192. For single-ended mode/pseudo differential mode, the LSB size is FSR/4096, unless

otherwise noted.

Unipolar 0 V to 10 V range with straight binary output coding.

Bipolar range with twos complement output coding.

12 16.5 V See Table 6

2.7 5.25 V

DRIVE

Min Typ Max Unit Test Conditions/Comments

= 500 kSPS

SAMPLE

IDD 180 μA VDD = 16.5 V ISS 205 μA VSS = −16.5 V ICC and I

2 mA V

DRIVE

CC/VDRIVE

SAMPLE

= 5.25 V

= 250 kSPS IDD 100 μA VDD = 16.5 V ISS 110 μA VSS = −16.5 V ICC and I

0.75 mA VCC/V

DRIVE

= 5.25 V

IDD 1 μA VDD = 16.5 V ISS 1 μA VSS = −16.5 V ICC and I

1 μA VCC/V

DRIVE

= 5.25 V

IDD 1 μA VDD = 16.5 V ISS 1 μA VSS = −16.5 V ICC and I

1 μA VCC/V

DRIVE

= 5.25 V

DRIVE

= 5.25 V

DRIVE

Rev. 0 | Page 6 of 36

AD7323

TIMING SPECIFICATIONS

VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 2.7 V to 5.25 V, V T

= T

to T

MAX

. Timing specifications apply with a 32 pF load, unless otherwise noted.

MIN

Table 3.

Limit at T

MIN

, T

MAX

Description

Parameter VCC < 4.75 V VCC = 4.75 V to 5.25 V Unit V

SCLK

50 50 kHz min 10 10 MHz max t

CONVER T

75 60 ns min

QUIET

16 × t

SCLK

ns max t

SCLK

12 5 ns min

25 20 ns min 45 35 ns min Unipolar input range (0 V to 10 V)

t5 0.4 × t t6 0.4 × t t

26 14 ns max

57 43 ns max Data access time after SCLK falling edge

SCLK

0.4 × t

SCLK

0.4 × t

SCLK

ns min SCLK high pulse width

SCLK

ns min SCLK low pulse width

13 8 ns min SCLK to data valid hold time

40 22 ns max SCLK falling edge to DOUT high impedance 10 9 ns min SCLK falling edge to DOUT high impedance t

POWER-UP

Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V

When using the 0 V to 10 V unipolar range, running at 500 kSPS throughput rate with t2 at 20 ns, the mark space ratio needs to be limited to 50:50.

4 4 ns min DIN set-up time prior to SCLK falling edge

2 2 ns min DIN hold time after SCLK falling edge

750 750 ns max Power-up from autostandby

500 500 μs max

25 25 μs typ

CONVERT

Figure 2. Serial Interface Timing Diagram

SCLK

DOUT

DIN

THREE-

STATE

1 2 3 4 5 13 14 15 16

2 IDENTIFICATION BITS

ADD1

ZERO

WRITE

ADD0 SI GN DB11 DB10 DB2 DB1 DB0

REG

SEL1

SEL2

= 2.7 V to 5.25 V, V

DRIVE

≤ VCC

DRIVE

SCLK

= 1/f

SCLK

= 2.5 V to 3.0 V internal/external,

REF

Minimum time between end of serial read and next falling edge of Minimum CS pulse width CS

to SCLK set-up time; bipolar input ranges (±10 V, ±5 V, ±2.5 V)

Delay from

until DOUT three-state disabled

Power-up from full shutdown/autoshutdown mode, internal reference

Power-up from full shutdown/autoshutdown mode, external reference

) and timed from a voltage level of 1.6 V.

DRIVE

DON’T

LSBMSB

CARE

THREE-STATE

QUIET

05400-002

Rev. 0 | Page 7 of 36

AD7323

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted

Table 4.

Parameter Rating

VDD to AGND, DGND −0.3 V to +16.5 V VSS to AGND, DGND +0.3 V to −16.5 V VDD to VCC V

− 0.3 V to 16.5 V

VCC to AGND, DGND −0.3 V to +7 V V

to AGND, DGND −0.3 V to +7 V

DRIVE

AGND to DGND −0.3 V to +0.3 V Analog Input Voltage to AGND

VSS − 0.3 V to VDD + 0.3 V Digital Input Voltage to DGND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to V

DRIVE

+ 0.3 V REFIN to AGND −0.3 V to VCC + 0.3 V Input Current to Any Pin

Except Supplies

±10 mA

Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TSSOP Package

θJA Thermal Impedance 150°C/W θJC Thermal Impedance 27.6°C/W

Pb-Free Temperature, Soldering

Reflow 260(0)°C

ESD 2.5 kV

If the analog inputs are driven from alternative VDD and VSS supply circuitry,

Schottky diodes should be placed in series with the AD7323’s VDD and VSS supplies.

Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 8 of 36

AD7323

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DIN

DGND

AGND

REFIN/O UT

TOP VIEW

(Not to Scale)

AD7323

SCLK

DGND

DOUT

DRIVE

VIN2

05400-003

Figure 3. TSSOP Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on

the AD7323 and frames the serial data transfer.

2 DIN

3, 15 DGND

Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the register on the falling edge of SCLK (see the

Registers section).

Digital Ground. Ground reference point for all digital circuitry on the AD7323. The DGND and AGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

4 AGND

Analog Ground. Ground reference point for all analog circuitry on the AD7323. All analog input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

5 REFIN/OUT

Reference Input/Reference Output. The on-chip reference is available on this pin for use external to the AD7323. The nominal internal reference voltage is 2.5 V, which appears at this pin. A 680 nF capacitor should be placed on the reference pin (see the

Reference section). Alternatively, the internal reference can be disabled and an external reference applied to this input. On power-up, the external reference mode is the default condition.

6 VSS Negative Power Supply Voltage. This is the negative supply voltage for the analog input section. 7, 8, 10, 9 VIN0 to VIN3

Analog Input 0 to Analog Input 3. The analog inputs are multiplexed into the on-chip track-and-hold. The analog input channel for conversion is selected by programming the Channel Address Bit ADD1 and Bit ADD0 in the control register. The inputs can be configured as four single-ended inputs, two true differential input pairs, two pseudo differential inputs, or three pseudo differential inputs. The configuration of the analog inputs is selected by programming the mode bits, Bit Mode 1 and Bit Mode 0, in the control register. The input range on each input channel is controlled by programming the range register. Input ranges of ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V can be selected on each analog input channel when a +2.5 V reference voltage is used (see the

Registers section). 11 VDD Positive Power Supply Voltage. This is the positive supply voltage for the analog input section. 12 VCC

Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7323. This supply should be decoupled to AGND.

13 V

DRIVE

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. This pin should be decoupled to DGND. The voltage at this pin may be different to that at V but it should not exceed V

14 DOUT

Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits

by more than 0.3 V.

are clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The data stream consists of a leading ZERO, two channel identification bits, the sign bit, and 12 bits of conversion data. The data is provided MSB first (see the

16 SCLK

Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the

Serial Interface section).

AD7323. This clock is also used as the clock source for the conversion process.

Rev. 0 | Page 9 of 36

AD7323

TYPICAL PERFORMANCE CHARACTERISTICS

SNR (dB)

–100

–120

–140

–20

–40

–60

–80

50 100 150 200 250

FREQUENCY (kHz)

Figure 4. FFT True Differential Mode

4096 POINT FF T V

CC=VDRIVE

DD,VSS

= 25°C

INT/EXT 2.5V REFERENCE ±10V RANGE F

SNR = 77. 30dB SINAD = 76.85dB THD = –86.96dB SFDR = –88.22dB

= 50kHz

= ±15V

=5V

05400-004

1.0 VCC=V T

= 25°C

0.8

DD,VSS

0.6

0.4

0.2

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 8192

512 1536 2560 3584 4608 5632 6656 7680

=5V

DRIVE

1024 2048 307 2 4096 512 0 6144 7168

INT/EXT 2.5V REF ERENCE ±10V RANGE

= ±15V

+INL = + 0.55LSB –INL = –0.68LSB

CODE

Figure 7. Typical INL True Differential Mode

05400-007

SNR (dB)

–100

–120

–140

–20

–40

–60

–80

50 100 150 200 250

FREQUENCY (kHz)

4096 POINT FF T V

CC=VDRIVE

DD,VSS

= 25°C

INT/EXT 2.5V REFERENCE ±10V RANGE F

SNR = 74. 67dB SINAD = 74.03dB THD = –82.68dB SFDR = –85.40dB

= 50kHz

=5V

=±15V

Figure 5. FFT Single-Ended Mode

1.0

0.8

0.6

0.4

0.2

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 8192

1024 2048 307 2 4096 512 0 6144 7168

512 1536 2560 3584 4608 5632 6656 7680

VCC=V

DRIVE

=25°C

= ±15V

DD,VSS

INT/EXT 2.5V REFERENCE ±10V RANGE +DNL = +0.72LSB –DNL = –0.22LSB

CODE

=5V

Figure 6. Typical DNL True Differential Mode

1.0

0.8

0.6

0.4

0.2

–0.2

DNL ERROR (LSB)

–0.4

VCC=V

–0.6

= 25°C

–0.8

DD,VSS

INT/EXT 2.5V REF ERENCE

–1.0

0 8192

512 1536 2560 3584 4608 5632 6656 7680

5400-005

=5V

DRIVE

= ±15V

1024 2048 307 2 4096 512 0 6144 7168

±10V RANGE +DNL = +0.79LSB –DNL = –0.38LSB

CODE

05400-043

Figure 8. Typical DNL Single-Ended Mode

1.0

0.8

0.6

0.4

0.2

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 8192

1024 2048 307 2 4096 512 0 6144 7168

512 1536 2560 3584 4608 5632 6656 7680

05400-006

VCC=V

DRIVE

= 25°C

=±15V

DD,VSS

INT/EXT 2.5V REFERENCE ±10V RANGE +INL = + 0.87LSB –INL = –0.49LSB

CODE

=5V

05400-044

Figure 9. Typical INL Single-Ended Mode

Rev. 0 | Page 10 of 36

AD7323

–

VCC=V V

–55

DD/VSS

= 500kSPS

–60

INTERNAL RE FERENCE

–65

–70

–75

THD (dB)

–80

–85

–90

–95

–100

=3V

DRIVE

=±12V

= 25°C

ANALOG INPUT FREQUENCY (kHz)

0V TO +10V SE

±5V SE

100

±10V SE

±10V DIFF

0V TO +10V DIFF

±5V DIFF

±2.5V DIFF

±2.5V SE

1000

05400-060

Figure 10. THD vs. Analog Input Frequency for Single-Ended (SE) and True

Differential Mode (Diff) at 3 V V

SINAD (dB)

ANALOG INPUT F REQUENCY (kHz)

±5V DIFF

±2.5V DIFF

±10V SE

0V TO +10V SE

VCC=V V

DD/VSS

=25°C

= 500kSPS

INTERNAL REFERENCE

100

±5V SE

±2.5V SE

±10V DIFF

0V TO +10V DIFF

=5V

DRIVE

= ±12V

1000

05400-063

Figure 13. SINAD vs. Analog Input Frequency for Single-Ended (SE) and True

Differential Mode (Diff) at 5 V V

VCC=V

–55

DD/VSS

= 500kSPS

–60

INTERNAL RE FERENCE

–65

–70

–75

THD (dB)

–80

–85

–90

–95

–100

10 1000

=5V

DRIVE

= ±12V

=25°C

ANALOG INPUT F REQUENCY (kHz)

100

0V TO +10V SE

0V TO +10V DIFF

±2.5V DIFF

±10V SE

±10V DIFF

±5V SE

±5V DIFF

±2.5V SE

05400-061

Figure 11. THD vs. Analog Input Frequency for Single-Ended (SE) and True

±2.5V DIFF

±10V SE

DD/VSS

=25°C

= 500kSPS

±5V SE

±2.5V SE

0V TO +10V DIFF

±10V DIFF

=3V

DRIVE

= ±12V

1000

05400-062

Differential Mode (Diff) at 5 V V

SINAD (dB)

ANALOG INPUT F REQUENCY (kHz)

±5V DIFF

0V TO +10V SE

VCC=V V T f

INTERNAL REFERENCE

100

Figure 12.SINAD vs. Analog Input Frequency for Single-Ended (SE) and True

Differential Mode (Diff) at 3 V V

–55

–60

–65

–70

–75

–80

–85

–90

CHANNEL-TO-CHANNEL ISOLATION (dB)

–95

100 200 300 400 500

0 600

VCC=3V

VDD/VSS=±12V SINGLE- ENDED MODE

= 500kSPS

50kHz ON SELECTED CHANNE L

FREQUENCY OF INPUT NOISE (kHz)

VCC=5V

=25°C

Figure 14. Channel-to-Channel Isolation

10k

NUMBER OF OCCURRENCES

–2

228

–1 0 1 2

9469

CODE

VCC=5V V

DD/VSS

RANGE = ±10V 10k SAMPLES T

=25°C

303

Figure 15. Histogram of Codes, True Differential Mode

=±12V

05400-012

05400-013

Rev. 0 | Page 11 of 36

AD7323

–

NUMBER OF OCCURE NCES

023

–2–10123

–3

1201

7600

1165

CODE

Figure 16. Histogram of Codes, Single-Ended Mode

–55

–60

–65

VCC=5V

–70

–75

CMRR (dB)

–80

–85

–90

–95

–100

=3V

DIFFERENTIAL MODE

= 50kHz

DD/VSS

= 500kSPS

=25°C

200 400 600 800 1000 1200

RIPPLE F REQUENCY (kHz)

Figure 17. CMRR vs. Common-Mode Ripple Frequency

VCC=5V

= ±12V

DD/VSS

RANGE = ±10V 10k SAMPL ES

= 25°C

11 0

= ±12V

05400-014

5400-055

2.0

1.5

1.0

0.5

–0.5

INL ERROR (LSB)

INL = 500kSPS

–1.0

±5V RANGE V

–1.5

–2.0

5 7 9 11 13 15 17 19

±V

SUPPLY VOLTAGE (V)

DD/VSS

CC=VDRIVE

INTERNAL REF ERENCE SINGLE-ENDED MODE

=5V

Figure 19. INL Error vs. Supply Voltage at 500 kSPS

100mV p-p SI NE WAVE ON EACH SUPPLY

–55

NO DECOUPLING SINGLE-E NDED MODE f

= 500kSPS

–60

–65

–70

–75

PSRR (dB)

–80

–85

–90

–95

–100

200 400 600 800 1000

0 1200

SUPPLY RIPPLE FREQUENCY (kHz)

VCC=3V

VCC=5V

VDD=12V

VSS=–12V

Figure 20. PSRR vs. Supply Ripple Frequency Without Supply Decoupling

05400-050

05400-054

2.0

1.5

1.0

0.5

–0.5

DNL ERROR (LSB)

DNL = 500kSPS

–1.0

±5V RANGE V

CC=VDRIVE

–1.5

INTERNAL REF ERENCE SINGLE-ENDED MODE

–2.0

5 7 9 11 13 15 17 19

=5V

±V

DD/VSS

SUPPLY VOLTAGE (V)

Figure 18. DNL Error vs. Supply Voltage at 500 kSPS

05400-049

Figure 21. THD vs. Analog Input Frequency for Various Source Impedances,

Rev. 0 | Page 12 of 36

VCC=V V

–55

DD/VSS

= 25°C

INTERNAL RE F

–60

RANGE = ±10V AND ±2.5V

= 500kSPS

–65

DIFFERENTIAL MODE

–70

–75

THD (dB)

–80

–85

–90

–95

–100

=5V

DRIVE

=±12V

INPUT FREQUENCY (kHz)

True Differential Mode

100

±10V RANGE R

= 4000Ω

= 3000Ω

= 2000Ω

= 1000Ω

= 100Ω

=12Ω

±2.5V RANGE R

= 9000Ω

= 5500Ω

= 2000Ω

=100Ω

=12Ω

1000

05400-064

AD7323

–

VCC=V V

–55

DD/VSS

=25°C

INTERNAL RE F

–60

RANGE = ±10V AND ±2.5V

= 500kSPS

–65

SINGLE-ENDED MODE

–70

–75

THD (dB)

–80

–85

–90

–95

–100

=+5V

DRIVE

= ±12V

INPUT FRE QUENCY (kHz)

100

±10V RANGE R

= 4000Ω

= 2000Ω

= 1000Ω

=100Ω

=50Ω

±2.5V RANGE R

= 4700Ω

= 3000Ω

= 1000Ω

= 100Ω

=50Ω

1000

Figure 22. THD vs. Analog Input Frequency for Various Source Impedances,

Single-Ended Mode

05400-065

Rev. 0 | Page 13 of 36

AD7323

TERMINOLOGY

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.

Integral Nonlinearity

This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale (a point 1 LSB below the first code transition) and full scale (a point 1 LSB above the last code transition).

Negative Full-Scale Error

This applies when using twos complement output coding and any of the bipolar analog input ranges. This is the deviation of the first code transition (10 ... 000) to (10 ... 001) from the ideal (that is, −4 × V

+ 1 LSB, −2 × V

REF

+ 1 LSB, −V

REF

+ 1 LSB)

REF

after adjusting for the bipolar zero code error.

Negative Full-Scale Error Match

This is the difference in negative full-scale error between any two input channels.

Offset Code Error

This applies to straight binary output coding. It is the deviation of the first code transition (00 ... 000) to (00 ... 001) from the ideal, that is, AGND + 1 LSB.

Offset Error Match

This is the difference in offset error between any two input channels.

Gain Error

This applies to straight binary output coding. It is the deviation of the last code transition (111 ... 110) to (111 ... 111) from the ideal (that is, 4 × V

− 1 LSB, 2 × V

REF

− 1 LSB, V

REF

−1 LSB)

REF

after adjusting for the offset error.

Gain Error Match

This is the difference in gain error between any two input channels.

Bipolar Zero Code Error

This applies when using twos complement output coding and a bipolar analog input. It is the deviation of the midscale transition (all 1s to all 0s) from the ideal input voltage, that is, AGND − 1 LSB.

Bipolar Zero Code Error Match

This refers to the difference in bipolar zero code error between any two input channels.

Positive Full-Scale Error

This applies when using twos complement output coding and any of the bipolar analog input ranges. It is the deviation of the last code transition (011 ... 110) to (011 ... 111) from the ideal (4 × V

− 1 LSB, 2 × V

REF

− 1 LSB, V

REF

− 1 LSB) after adjusting

REF

for the bipolar zero code error.

Positive Full-Scale Error Match

This is the difference in positive full-scale error between any two input channels.

Track-and-Hold Acquisition Time

The track-and-hold amplifier returns into track mode after the

SCLK rising edge. Track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±½ LSB, after the end of a conversion. For the ±2.5 V range, the specified acquisition time is the time required for the track-and-hold amplifier to settle to within ±1 LSB.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all non-fundamental signals up to half the sampling frequency (f

/2), excluding dc. The ratio

is dependent on the number of quantization levels in the digitization process. The more levels, the smaller the quantization noise. Theoretically, the signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by

Signal to (Noise + Distortion) = (6.02 N + 1.76) dB

For a 13-bit converter, this is 80.02 dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7323 it is defined as

THD

where V V

, V5, and V6 are the rms amplitudes of the second through the

is the rms amplitude of the fundamental, and V2, V3,

log20)dB(

++++

VVVVV

sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to f

/2, excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, the largest harmonic could be a noise peak.

Rev. 0 | Page 14 of 36

AD7323

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of crosstalk between any two channels. It is measured by applying a full-scale, 100 kHz sine wave signal to all unselected input channels and determining the degree to which the signal attenuates in the selected channel with a 50 kHz signal.

Figure 14 shows the worstcase across all eight channels for the AD7323. The analog input range is programmed to be the same on all channels.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to 0. For example, the second-order terms include (fa + fb) and (fa − fb), whereas the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).

The AD7323 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, whereas the third-order

terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels.

PSR (Power Supply Rejection)

Variations in power supply affect the full-scale transition but not the linearity of the converter. Power supply rejection is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value (see the Typical Performance Characteristics section).

CMRR (Common-Mode Rejection Ratio)

CMRR is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV sine wave applied to the common-mode voltage of the VIN+ and VIN− frequency, f

, as

CMRR (dB) = 10 log (Pf/Pf

)

where Pf is the power at frequency f in the ADC output, and Pf is the power at frequency f

in the ADC output (see Figure 17).

Rev. 0 | Page 15 of 36

AD7323

THEORY OF OPERATION

CIRCUIT INFORMATION

The AD7323 is a fast, 4-channel, 12-bit plus sign, bipolar input, serial A/D converter. The AD7323 can accept bipolar input ranges that include ±10 V, ±5 V, and ±2.5 V; it can also accept a 0 V to +10 V unipolar input range. A different analog input range can be programmed on each analog input channel via the on-chip registers. The AD7323 has a high speed serial interface that can operate at throughput rates up to 500 kSPS.

The AD7323 requires V analog input structures. These supplies must be equal to or greater than the largest analog input range selected. See requirements of these supplies for each analog input range. The AD7323 requires a low voltage 2.7 V to 5.25 V V power the ADC core.

Table 6. Reference and Supply Requirements for Each Analog Input Range

Selected Analog Input Range (V)

Reference Voltage (V)

2.5 ±10 3/5 ±10 ±10

3.0 ±12 3/5 ±12

2.5 ±5 3/5 ±5 ± 5

3.0 ±6 3/5 ±6

2.5 ±2.5 3/5 ±5 ±2.5

3.0 ±3 3/5 ±5

2.5 0 to +10 3/5 +10/AGND 0 to +10

3.0 0 to +12 3/5 +12/AGND

It may be necessary to decrease the throughput rate when the AD7323 is configured with the minimum V in order to meet the performance specifications (see the Performance Characteristics change in THD as the V performance at the maximum throughput rate, the THD degrades slightly as V necessary to reduce the throughput rate when using minimum V

and VSS supplies so that there is less degradation of THD

and the specified performance can be maintained. The degradation is due to an increase in the on resistance of the input multiplexer when the V Figure 18 and Figure 19 show the change in INL and DNL as the V

and VSS voltages are varied. For dc performance when

operating at the maximum throughput rate, as the V supply voltages are reduced, the typical INL and DNL error remains constant.

and VSS dual supplies for the high voltage

Table 6 for the

supply to

FullScale Input Range (V)

AV (V)

Minimum

VDD/V

and VSS supplies

Ty pi ca l

section). Figure 31 shows the

and VSS supplies are reduced. For ac

and VSS are reduced. It might therefore be

and VSS supplies are reduced.

and VSS

(V)

The analog inputs can be configured as four single-ended inputs, two true differential inputs, two pseudo differential inputs, or three pseudo differential inputs. Selection can be made by programming the mode bits, Mode 0 and Mode 1, in the control register.

The serial clock input accesses data from the part and provides the clock source for the successive approximation ADC. The AD7323 has an on-chip 2.5 V reference. However, the AD7323 can also work with an external reference. On power-up, the external reference operation is the default option. If the internal reference is the preferred option, the user must write to the reference bit in the control register to select the internal reference operation.

The AD7323 also features power-down options to allow power savings between conversions. The power-down modes are selected by programming the on-chip control register, as described in the

Modes of Operation section.

CONVERTER OPERATION

The AD7323 is a successive approximation analog-to-digital converter built around two capacitive DACs. Figure 24 show simplified schematics of the ADC in singleended mode during the acquisition and conversion phases, respectively.

Figure 25 and Figure 26 show simplified schematics of the ADC in differential mode during acquisition and conversion phases, respectively. The ADC is composed of control logic, a SAR, and capacitive DACs. In acquisition phase), SW2 is closed and SW1 is in Position A, the comparator is held in a balanced condition, and the sampling capacitor array acquires the signal on the input.

SW1

AGND

Figure 23. ADC Acquisition Phase (Single-Ended)

COMPARATOR

SW2

When the ADC starts a conversion (Figure 24), SW2 opens and SW1 moves to Position B, causing the comparator to become unbalanced. The control logic and the charge redistribution DAC are used to add and subtract fixed amounts of charge from the capacitive DAC to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code.

Figure 23 and

Figure 23 (the

CAPACITIVE

DAC

CONTROL

LOGIC

05400-017

Rev. 0 | Page 16 of 36

AD7323

CAPACITIVE

AGND

COMPARATOR

SW2SW1

Figure 24. ADC Conversion Phase (Single-Ended)

DAC

CONTROL

LOGIC

5400-018

The ideal transfer characteristic for the AD7323 when twos complement coding is selected is shown in

Figure 27. The ideal transfer characteristic for the AD7323 when straight binary coding is selected is shown in

011...111

011...110

Figure 28.

Figure 25 shows the differential configuration during the acquisition phase. For the conversion phase, SW3 opens and SW1 and SW2 move to Position B (see impedances of the source driving the V

Figure 26). The output

+ and VIN− pins must

match; otherwise, the two inputs have different settling times, resulting in errors.

CAPACITIVE

DAC

SW1 SW2

–

REF

COMPARATOR

SW3

CONTROL

LOGIC

CAPACITIVE

DAC

05400-019

Figure 25. ADC Differential Configuration During Acquisition Phase

CAPACITIVE

DAC

SW1 SW2

–

REF

COMPARATOR

SW3

CONTROL

LOGIC

CAPACITIVE

DAC

05400-020

Figure 26. ADC Differential Configuration During Conversion Phase

Output Coding

The AD7323 default output coding is set to twos complement. The output coding is controlled by the coding bit in the control register. To change the output coding to straight binary coding, the coding bit in the control register must be set. When operating in sequence mode, the output coding for each channel in the sequence is the value written to the coding bit during the last write to the control register.

Transfer Functions

The designed code transitions occur at successive integer LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size is dependent on the analog input range selected.

Table 7. LSB Sizes for Each Analog Input Range

Input Range Full-Scale Range/8192 Codes LSB Size

±10 V 20 V 2.441 mV ±5 V 10 V 1.22 mV ±2.5 V 5 V 0.61 mV 0 V to +10 V 10 V 1.22 mV

000...001

000...000

111. ..111

ADC CODE

100...010

100...001

100...000

–FSR/2 + 1LSB

AGND + 1LS B

AGND – 1LSB

ANALOG INPUT

+FSR/2 – 1LSB BIPOLAR RANGES +FSR – 1LSB UNIPOLAR RANGE

05400-021

Figure 27. Twos Complement Transfer Characteristic

111. ..111

111.. .110

111...000

011...111

ADC CODE

000...010

000...001

000...000

–FSR/2 + 1LSB

AGND + 1LS B

+FSR/2 – 1LSB BIPOLAR RANGES +FSR – 1LSB UNIPOLAR RANGE

ANALOG INPUT

05400-022

Figure 28. Straight Binary Transfer Characteristic

ANALOG INPUT STRUCTURE

The analog inputs of the AD7323 can be configured as singleended, true differential, or pseudo differential via the control register mode bits (see bipolar input signals. On power-up, the analog inputs operate as four single-ended analog input channels. If true differential or pseudo differential is required, a write to the control register is necessary after power-up to change this configuration.

Figure 29 shows the equivalent analog input circuit of the AD7323 in single-ended mode. analog input structure in differential mode. The two diodes provide ESD protection for the analog inputs.

Figure 29. Equivalent Analog Input Circuit (Single-Ended)

Table 9 ). The AD7323 can accept true

Figure 30 shows the equivalent

05400-023

Rev. 0 | Page 17 of 36

AD7323

–

05400-024

Figure 30. Equivalent Analog Input Circuit (Differential)

Care should be taken to ensure that the analog input does not exceed the V

and VSS supply rails by more than 300 mV.

Exceeding this value causes the diodes to become forward biased and to start conducting into either the V V

supply rail. These diodes can conduct up to 10 mA without

supply rail or

causing irreversible damage to the part.

Figure 29and Figure 30, Capacitor C1 is typically 4 pF and

In can primarily be attributed to pin capacitance. Resistor R1 is a lumped component made up of the on resistance of the input multiplexer and the track-and-hold switch. Capacitor C2 is the sampling capacitor; its capacitance varies depending on the analog input range selected (see the

Specifications section).

Track-and-Hold Section

The track-and-hold on the analog input of the AD7323 allows the ADC to accurately convert an input sine wave of full-scale amplitude to 13-bit accuracy. The input bandwidth of the trackand-hold is greater than the Nyquist rate of the ADC. The AD7323 can handle frequencies up to 22 MHz.

The AD7323 enters track mode on the 14

SCLK rising edge. When running the AD7323 at a throughput rate of 1 MSPS with a 10 MHz SCLK signal, the ADC has approximately

1.5 SCLK + t

+ t

QUIET

to acquire the analog input signal. The ADC goes back into

hold mode on the

As the V

DD/VSS

falling edge.

supply voltage is reduced, the on resistance of the input multiplexer increases. Therefore, based on the equation for t

, it is necessary to increase the amount of

ACQ

acquisition time provided to the AD7323, and hence decrease the overall throughput rate. V

supplies are reduced, the specified THD performance

Figure 31 shows that as the VDD and

degrades slightly. If the throughput rate is reduced when operating with the minimum V

and VSS supplies, the specified

THD performance is maintained.

–80

–85

THD (dB)

–90

–95

Figure 31. THD vs. ±V

500kSPS

7 9 11 13 15 17

±V

DD/VSS

VCC=V INTERNAL REF ERENCE T

=25°C

±5V RANGE SE MODE

SUPPLIES (V)

DRIVE

= 10kHz

=5V

Supply Voltage at 500 kSPS

05400-051

The track-and-hold enters its tracking mode on the 14th SCLK

rising edge after the

falling edge. The time required to acquire an input signal depends on how quickly the sampling capacitor is charged. With 0 source impedance, 305 ns is sufficient to acquire the signal to the 13-bit level. The acquisition time required is calculated using the following formula:

= 10 × ((R

ACQ

SOURCE

+ R) C)

where C is the sampling capacitance and R is the resistance seen by the track-and-hold amplifier looking back on the input. For the AD7323, the value of R includes the on resistance of the input multiplexer and is typically 300 Ω. R

should include

SOURCE

any extra source impedance on the analog input.

Rev. 0 | Page 18 of 36

Unlike other bipolar ADCs, the AD7323 does not have a resistive analog input structure. On the AD7323, the bipolar analog signal is sampled directly onto the sampling capacitor. This gives the AD7323 high analog input impedance. An approximation for the analog input impedance can be calculated from the following formula:

Z = 1/(f

where f

× CS)

is the sampling frequency, and CS is the sampling

capacitor value.

depends on the analog input range chosen (see the

Specifications section). When operating at 500 kSPS, the analog input impedance is typically 145 k for the ±10 V range. As the sampling frequency is reduced, the analog input impedance further increases. As the analog input impedance increases, the current required to drive the analog input therefore decreases.

AD7323

TYPICAL CONNECTION DIAGRAM

Figure 32 shows a typical connection diagram for the AD7323. In this configuration, the AGND pin is connected to the analog ground plane of the system, and the DGND pin is connected to the digital ground plane of the system. The analog inputs on the AD7323 can be configured to operate in single-ended, true differential, or pseudo differential mode. The AD7323 can operate with either an internal or external reference. In

Figure 32, the AD7323 is configured to operate with the internal 2.5 V reference. A 680 nF decoupling capacitor is required when operating with the internal reference.

The V 5 V supply voltage. The V

pin can be connected to either a 3 V supply voltage or a

and VSS are the dual supplies for the

high voltage analog input structures. The voltage on these pins must be equal to or greater than the highest analog input range selected on the analog input channels (see

Tabl e 6 ). The V

DRIVE

pin is connected to the supply voltage of the microprocessor. The voltage applied to the V the serial interface. V

+15

ANALOG INPUTS ±10V, ±5V, ±2.5V 0V TO +10V

680nF

–15V

DRIVE

+ 10µF0.1µF

AD7323

VIN0 VIN1 VIN2 VIN3

REFIN/OUT

10µF0. 1µF

MINIMUM VDDAND VSSSUPPLY VOLTAGES DEPEND ON THE HIGHEST ANALOG INPUT RANGE SELECT ED.

Figure 32. Typical Connection Diagram

input controls the voltage of

DRIVE

can be set to 3 V or 5 V.

10µF 0.1µF

DGND

AGND

DRIVE

DOUT

SCLK

DIN

10µF 0.1µF

+3V SUPPLY

SERIAL

INTERFACE

+2.7VTO 5.25

µC/µP

ANALOG INPUT

Single-Ended Inputs

The AD7323 has a total of four analog inputs when operating the AD7323 in single-ended mode. Each analog input can be independently programmed to one of the four analog input ranges. In applications where the signal source is high impedance, it is recommended to buffer the signal before applying it to the ADC analog inputs. configuration of the AD7323 in single-ended mode.

Figure 33 shows the

AGND

AD7323

V–

ADDITIONAL PI NS OMITTED FOR CLARITY.

05400-026

Figure 33. Single-Ended Mode Typical Connection Diagram

True Differential Mode

The AD7323 can have a total of two true differential analog input pairs. Differential signals have some benefits over singleended signals, including better noise immunity based on the device’s common-mode rejection and improvements in distortion performance.

Figure 34 defines the configuration of

the true differential analog inputs of the AD7323.

AD7323

–

ADDITIONA L PINS OMI TTED FOR CLARITY.

05400-027

Figure 34. True Differential Inputs

The amplitude of the differential signal is the difference between the signals applied to the V each differential pair (V

+ − VIN−). VIN+ and VIN− should

+ and VIN− pins in

be simultaneously driven by two signals each of amplitude ±4 × VREF (depending on the input range selected) that are 180° out of phase. Assuming the ±4 × VREF mode, the amplitude of the differential signal is −20 V to +20 V p-p (2 × 4 × VREF), regardless of the common mode.

05400-025

The common mode is the average of the two signals

+ + VIN−)/2

and is therefore the voltage on which the two input signals are centered.

This voltage is set up externally, and its range varies with reference voltage. As the reference voltage increases, the common-mode range decreases. When driving the differential inputs with an amplifier, the actual common-mode range is determined by the amplifier’s output swing. If the differential inputs are not driven from an amplifier, the common-mode range is determined by the supply voltage on the V and the V

supply pin.

supply pin

When a conversion takes place, the common mode is rejected, resulting in a noise-free signal of amplitude −2 × (4 × VREF) to +2 × (4 × VREF) corresponding to Digital Codes −4096 to +4095.

Rev. 0 | Page 19 of 36

AD7323

RANGE (V)

–1

COM

–2

–3

–4

VCC=3V

–5

REF

–6

=3V

±10V

RANGE

±5V RANGE

±16.5V VDD/V

Figure 35. Common-Mode Range for V

RANGE

=3V

±5V RANGE

±10V

±16.5V VDD/V

RANGE (V)

COM

–2

VCC=5V V

REF

–4

Figure 36. Common-Mode Range for V

RANGE (V)

–2

COM

–4

–6

VCC=3V V

REF

–8

±10V

RANGE

=2.5V

±5V RANGE

±16.5V VDD/V

Figure 37. Common-Mode Range for V

±2.5V

RANGE

±2.5V

RANGE

±2.5V

RANGE

±5V RANGE

±10V

RANGE

±12V VDD/V

= 3 V and REFIN/OUT = 3 V

±10V

RANGE

±12V VDD/V

= 5 V and REFIN/OUT = 3 V

±10V

RANGE

±12V VDD/V

= 3 V and REFIN/OUT = 2.5 V

±5V RANGE

±2.5V

RANGE

±2.5V

RANGE

±2.5V

RANGE

±2.5V

RANGE

VCC=5V

=2.5V

REF

±10V

RANGE

±5V RANGE

±16.5V VDD/V

RANGE (V)

–2

COM

–4

–6

–8

05400-045

Figure 38. Common-Mode Range for V

±5V RANGE

±10V

RANGE

±2.5V

RANGE

±12V VDD/V

= 5 V and REFIN/OUT = 2.5 V

05400-048

Pseudo Differential Inputs

The AD7323 can have two pseudo differential pairs or three pseudo differential inputs referenced to a common V The V

+ inputs are coupled to the signal source and must have

− pin.

an amplitude within the selected range for that channel as programmed in the range register. A dc input is applied to the V

− pin. The voltage applied to this input provides an offset for

the V

+ input from ground or a pseudo ground. Pseudo

differential inputs separate the analog input signal ground from the ADC ground, allowing cancellation of dc common-mode voltages.

05400-046

When a conversion takes place, the pseudo ground corresponds to Code −4096 and the maximum amplitude corresponds to Code +4095.

AD7323

VIN–

V–

ADDITIONAL PINS OMIT TED FOR CLARITY.

Figure 39. Pseudo Differential Inputs

05400-047

Figure 40 and Figure 41 show the typical voltage range on the

− pin for the different analog input ranges when configured

05400-028

in the pseudo differential mode.

For example, when the AD7324 is configured to operate in pseudo differential mode and the ±5 V range is selected with ±16.5 V V

supplies and 5 V VCC, the voltage on the VIN−

DD/VSS

pin can vary from −6.5 V to +6.5 V.

Rev. 0 | Page 20 of 36

AD7323

–

–2–

–

–2–4–

VCC=5V V

REF

±10V

RANGE

=2.5V

±5V RANGE

±16.5V VDD/V

±2.5V

RANGE

0V TO + 10V

Figure 40. Pseudo Input Range with V

REF

±10V

RANGE

=2.5V

±5V RANGE

±2.5V

RANGE

±16.5V V

0V TO + 10V

DD/VSS

VCC=3V V

Figure 41. Pseudo Input Range with V

RANGE

±5V RANGE

±10V

RANGE

±12V VDD/V

±5V RANGE

±10V

RANGE

±12V VDD/V

±2.5V

RANGE

0V TO + 10V

RANGE

= 5 V

±2.5V

RANGE

0V TO + 10V

RANGE

= 3 V

05400-039

05400-040

DRIVER AMPLIFIER CHOICE

In applications where the harmonic distortion and signal-tonoise ratio are critical specifications, the analog input of the AD7323 should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC and can necessitate the use of an input buffer amplifier.

When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of THD that can be tolerated in the application. The THD increases as the source impedance increases and performance degrades. Figure 22 show graphs of the THD vs. the analog input frequency for various source impedances. Depending on the input range and analog input configuration selected, the AD7323 can handle source impedances of up to 5.5 kΩ before the THD starts to degrade.

Due to the programmable nature of the analog inputs on the AD7323, the choice of op amp used to drive the inputs is a function of the particular application and depends on the input configuration and the analog input voltage ranges selected.

Figure 21 and

Rev. 0 | Page 21 of 36

The driver amplifier must be able to settle for a full-scale step to a 13-bit level, 0.0122%, in less than the specified acquisition time of the AD7323. An op amp such as the AD8021 meets this requirement when operating in single-ended mode. The AD8021 needs an external compensating NPO type of capacitor. The AD8022 can also be used in high frequency applications where a dual version is required. For lower frequency applications, op amps such as the AD797, AD845, and AD8610 can be used with the AD7323 in single-ended mode configuration.

Differential operation requires that V

+ and VIN− be

simultaneously driven with two signals of equal amplitude that are 180° out of phase. The common mode must be set up externally to the AD7323. The common-mode range is determined by the REFIN/OUT voltage, the V

supply voltage,

and the particular amplifier used to drive the analog inputs. Differential mode with either an ac input or a dc input provides the best THD performance over a wide frequency range. Because not all applications have a signal preconditioned for differential operation, there is often a need to perform the single-ended-todifferential conversion.

This single-ended-to-differential conversion can be performed using an op amp pair. Typical connection diagrams for an op amp pair are shown in

Figure 42 and Figure 43. In Figure 42, the common-mode signal is applied to the noninverting input of the second amplifier.

1.5kΩ

3kΩ

1.5kΩ

10kΩ

COM

Figure 42. Single-Ended-to-Differential Configuration with the AD845

442Ω

100Ω

Figure 43. Single-Ended-to-Differential Configuration with the AD8021

20kΩ

AD845

1.5kΩ

AD845

442Ω

AD8021

442Ω

AD8021

V+

V–

05400-029

V+

V–

05400-030

AD7323

REGISTERS

The AD7323 has three programmable registers: the control register, sequence register, and range register. These registers are write-only registers.

ADDRESSING REGISTERS

A serial transfer on the AD7323 consists of 16 SCLK cycles. The three MSBs on the DIN line during the 16 SCLK transfer are decoded to determine which register is addressed. The three MSBs consist of the write bit, Register Select 1 bit, and Register Select 2 bit. The register select bits are used to determine which of the three on-board registers is selected. The write bit determines if the data on the DIN line following the register select bits loads into the addressed register. If the write bit is 1, the bits load into the register addressed by the register select bits. If the write bit is 0, the data on the DIN line does not load into any register.

Table 8. Decoding Register Select Bits and Write Bit

Write Register Select 1 Register Select 2 Description

0 0 0 Data on the DIN line during this serial transfer is ignored. 1 0 0

1 0 1

1 1 1

This combination selects the control register. The subsequent 12 bits are loaded into the control register.

This combination selects the range register. The subsequent 8 bits are loaded into the range register.

This combination selects the sequence register. The subsequent 4 bits are loaded into the sequence register.

Rev. 0 | Page 22 of 36

AD7323

CONTROL REGISTER

The control register is used to select the analog input channel, analog input configuration, reference, coding, and power mode. The control register is a write-only, 12-bit register. Data loaded on the DIN line corresponds to the AD7323 configuration for the next conversion. If the sequence register is being used, data should be loaded into the control register after the range register and the sequence register have been initialized. The bit functions of the control register are shown in

MSB LSB

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write Register Select 1 Register Select 2 ZERO ADD1 ADD0 Mode 1 Mode 0 PM1 PM0 Coding Ref Seq1 Seq2 ZERO 0

Table 9. Control Register Details

Bit Mnemonic Description

12, 1 ZERO A 0 should be written to these bits. 11, 10 ADD1, ADD0

9, 8 Mode 1, Mode 0

7, 6 PM1, PM0 The power management bits are used to select different power mode options on the AD7323 (see Tabl e 11). 5 Coding

4 Ref

3, 2 Seq1, Seq2 The Sequence 1 and Sequence 2 bits are used to control the operation of the sequencer (see Table 12).

These two channel address bits are used to select the analog input channel for the next conversion if the sequencer is not being used. If the sequencer is being used, the two channel address bits are used to select the final channel in a consecutive sequence.

These two mode bits are used to select the configuration of the four analog input pins, V pins are used in conjunction with the channel address bits. On the AD7323, the analog inputs can be configured as four single-ended inputs, two true differential input pairs, two pseudo differential inputs, or three pseudo differential inputs (see

This bit is used to select the type of output coding the AD7323 uses for the next conversion result. If coding = 0, the output coding is twos complement. If coding = 1, the output coding is straight binary. When operating in sequence mode, the output coding for each channel is the value written to the coding bit during the last write to the control register.

The reference bit is used to enable or disable the internal reference. If Ref = 0, the external reference is enabled and used for the next conversion, and the internal reference is disabled. If Ref = 1, the internal reference is used for the next conversion. When operating in sequence mode, the reference used for each channel is the value written to the Ref bit during the last write to the control register.

Table 10).

The four analog input channels can be configured as four single-ended analog inputs, two true differential input pairs, two pseudo differential inputs, or three pseudo differential inputs.

Table 10. Analog Input Configuration Selection

Mode 1 = 1, Mode 0 = 1 Mode 1 = 1, Mode 0 = 0 Mode 1 = 0, Mode 0 =1 Mode 1 = 0, Mode 0 = 0 Channel Address Bits 3 Pseudo Differential I/Ps 2 Fully Differential I/Ps 2 Pseudo Differential I/Ps 4 Single-Ended I/Ps ADD1 ADD0 VIN+ VIN− VIN+ VIN− VIN+ VIN− VIN+ VIN−

0 0 VIN0 VIN3 VIN0 VIN1 VIN0 VIN1 VIN0 AGND 0 1 VIN1 VIN3 VIN0 VIN1 VIN0 VIN1 VIN1 AGND 1 0 VIN2 VIN3 VIN2 VIN3 VIN2 VIN3 VIN2 AGND 1 1 Not allowed VIN2 VIN3 VIN2 VIN3 VIN3 AGND

Tabl e 9 (the power-up status of all bits is 0).

0 to VIN3. These

Rev. 0 | Page 23 of 36

AD7323

Table 11. Power Mode Selection

PM1 PM0 Description

1 1

1 0

0 1

0 0 Normal Mode. All internal circuitry is powered up at all times.

Table 12. Sequencer Selection

Seq1 Seq2 Description

0 0

0 1

1 0

1 1

Full Shutdown Mode. In this mode, all internal circuitry on the AD7323 is powered down. Information in the control register is retained when the AD7323 is in full shutdown mode.

Autoshutdown Mode. The AD7323 enters autoshutdown on the 15 All internal circuitry is powered down in autoshutdown.

Autostandby Mode. In this mode, all internal circuitry is powered down, excluding the internal reference. The AD7323 enters autostandby mode on the 15

The channel sequencer is not used. The analog channel, selected by programming the ADD1 bit and ADD0 bit in the control register, selects the next channel for conversion.

Uses the sequence of channels previously programmed into the sequence register for conversion. The AD7323 starts converting on the lowest channel in the sequence. The channels are converted in ascending order. If uninterrupted, the AD7323 keeps converting the sequence. The range for each channel defaults to the range previously written into the range register.

Used in conjunction with the channel address bits in the control register. This allows continuous conversions on a consecutive sequence of channels, from Channel 0 through a final channel selected by the channel address bits in the control register. The range for each channel defaults to the range previously written into the range register.

The channel sequencer is not used. The analog channel, selected by programming the ADD1 bit and ADD0 bit in the control register, selects the next channel for conversion.

SCLK rising edge after the control register is updated.

SCLK rising edge when the control register is updated.

Rev. 0 | Page 24 of 36

AD7323

SEQUENCE REGISTER

The sequence register on the AD7323 is a 4-bit, write-only register. Each of the four analog input channels has one corresponding bit in the sequence register. To select a channel for inclusion in the sequence, set the corresponding channel bit to 1 in the sequence register.

MSB LSB

16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Write Register Select 1 Register Select 2 VIN0 VIN1 VIN2 VIN3 0 0 0 0 0 0 0 0 0

RANGE REGISTER

The range register is used to select one analog input range per analog input channel. It is an 8-bit, write-only register with two dedicated range bits for each of the analog input channels from Channel 0 to Channel 3. There are four analog input ranges, ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V. A write to the range register is selected by setting the write bit to 1 and the register select bits to 0 and 1. After the initial write to the range register occurs, each time an analog input is selected, the AD7323 automatically configures the analog input to the appropriate range, as indicated by the range register. The ±10 V input range is selected by default on each analog input channel (see

MSB LSB

16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Write Register Select 1 Register Select 2 VIN0A VIN0B VIN1A VIN1B VIN2A VIN2B VIN3A VIN3B 0 0 0 0 0

Table 13. Range Selection

VINxA VINxB Description

0 0 This combination selects the ± 10 V input range on VINx. 0 1 This combination selects the ±5 V input range on VINx. 1 0 This combination selects the ± 2.5 V input range on VINx. 1 1 This combination selects the 0 V to +10 V input range on VINx.

Tabl e 1 3 ).

Rev. 0 | Page 25 of 36

AD7323

SEQUENCER OPERATION

POWER ON.

DIN: WRIT E TO CONTROL

SEQUENCE, Seq1 = 0, Seq2 = 0.

DOUT: CONVERSION RESULT

FROM CHANNEL I N SEQUENCE.

DIN: WRIT E TO RANGE REGI STER TO SELECT THE RANG E

DIN: TIE DIN LO W/WRI TE BIT = 0 TO CONTINUE TO CO NVERT

A SEQUENCE.

FOR EACH ANALOG INPUT CHANNEL.

DOUT: CONV ERSION RESULT F ROM CHANNEL 0, ±10V

DIN: WRIT E TO SEQUENCE REGISTER TO SEL ECT THE

DOUT: CONVERS ION RESULT FROM F IRST CHANNEL I N

STOPPING

RANGE, SI NGLE-ENDED MODE.

ANALOG INPUT CHANNELS TO BE INCLUDED I N

DOUT: CONVERSION RESULT F ROM CHANNEL 0,

SINGLE-E NDED MODE, RANGE SELECTED IN

DIN: WRIT E TO CONTROL REGISTER TO S TART THE

DOUT: CONVERSION RESULT F ROM CHANNEL 0,

SINGLE-E NDED MODE, RANGE SELECTED IN

THROUGH THE SEQUENCE OF CHANNELS.

SELECTING A NEW SEQUENCE.

THE SEQUE NCE.

RANGE REGI STER.

SEQUENCE, Seq1 = 0, Seq2 = 1.

RANGE REGI STER.

THE SEQUE NCE.

CONTINUOUSL Y CONVERT

ON THE SELECT ED SEQUENCE

OF CHANNELS .

DIN TIED LOW/ WRITE BIT = 0.

DIN: WRIT E TO SEQUENCE REGISTER TO SEL ECT THE

DOUT: CONVERSION RESULT FROM CHANNEL X IN

Figure 44. Programmable Sequence Flowchart

The AD7323 can be configured to automatically cycle through a number of selected channels using the on-chip sequence register with the Seq1 bit and the Seq2 bit in the control register. Figure 44 shows how to program the AD7323 register to operate in sequence mode.

After power-up, all of the three on-chip registers contain default values. Each analog input has a default input range of ±10 V. If different analog input ranges are required, a write to the range register is required. This is shown in the first serial transfer of Figure 44.

Rev. 0 | Page 26 of 36

NEW SEQUE NCE.

THE FIRST SEQUENCE.

This initial serial transfer is only necessary if input ranges other than the default ranges are required. After the analog input ranges are configured, a write to the sequence register is necessary to select the channels to be included in the sequence. Once the channels for the sequence have been selected, the sequence can be initiated by writing to the control register and setting the Seq1 = 0 and Seq2 = 1. The AD7323 continues to convert the selected sequence without interruption provided that the sequence register remains unchanged, and Seq1 = 0 and Seq2 = 1 in the control register.

5400-031

AD7323

If a change to the range register is required during a sequence, it is necessary to first stop the sequence by writing to the control register and setting Seq1 to 0 and Seq2 to 0. Next, the write to the range register should be completed to change the required range. The previously selected sequence can be initiated again by writing to the control register and setting Seq1 to 0 and Seq2 to 1. The ADC converts on the first channel in the sequence.

The AD7323 can be configured to convert a sequence of consecutive channels (see

Figure 45). This sequence begins by converting on Channel 0 and ends with a final channel as selected by Bit ADD1 to Bit ADD0 in the control register. In this configuration, there is no need for a write to the sequence register. To operate the AD7323 in this mode, set Seq1 to 1 and Seq2 to 0, and then select the final channel in the sequence by programming Bit ADD1 to Bit ADD0 in the control register.

POWER ON.

Once the control register is configured to operate the AD7323 in this mode, the DIN line can be held low, or the write bit can be set to 0. To return to traditional multichannel operation, a write to the control register to set Seq1 to 0 and Seq2 to 0 is necessary.

When Seq1 and Seq2 are both set to 0, or when both are set to 1, the AD7323 is configured to operate in traditional multichannel mode, where a write to Channel Address Bit ADD1 to Bit ADD0 in the control register selects the next channel for conversion.

DIN: WRIT E TO RANGE REGIS TER TO SELECT THE RANGE

DOUT: CONVERSION RESULT F ROM CHANNEL 0, ±10V

DIN: WRIT E TO CONTROL REGISTER TO SEL ECT THE FINAL

CHANNEL IN THE CONS ECUTIVE SEQ UENCE, SET S eq1 = 1

AND Seq2 = 0. SEL ECT OUTPUT CODING F OR SEQUENCE.

DIN: WRITE BIT = 0 OR DIN LINE HEL D LOW TO CO NTINUE

THROUGH SEQUENCE OF CONSECUT IVE CHANNELS.

FOR ANALOG I NPUT CHANNELS.

RANGE, SINGLE-ENDED M ODE.

DOUT: CONVE RSION RESULT FROM CHANNEL 0,

RANGE SELECTED IN RANGE REGI STER,

SINGLE-ENDED MODE.

TO CONVERT T HROUGH THE SEQUENCE OF

CONSECUTIVE CHANNELS.

DOUT: CONVE RSION RESULT FROM CHANNEL 0,

RANGE SELECTED IN RANGE REGI STER.

DOUT: CONVE RSION RESULT FROM CHANNEL 1,

RANGE SELECTED IN RANGE REGI STER.

STOPPING

A SEQUENCE.

ON CONSECUTI VE SEQUENCE

CONTINUOUSL Y CONVERT

DINTIEDLOW/WRITEBIT =0.

OF CHANNELS.

DIN: WRIT E TO CONTROL

SEQUENCE, Seq1 = 0, Seq2 = 0.

DOUT: CONVERSION RESULT

FROM CHANNEL IN S EQUENCE.

05400-032

Figure 45. Flowchart for Consecutive Sequence of Channels

Rev. 0 | Page 27 of 36

AD7323

REFERENCE

The AD7323 can operate with either the internal 2.5 V on-chip reference or an externally applied reference. The internal reference is selected by setting the Ref bit in the control register to 1. On power-up, the Ref bit is 0, which selects the external reference for the AD7323 conversion. Suitable reference sources for the AD7323 include AD780, AD1582, ADR431, REF193, and ADR391.

conversion result from the first initial conversion is invalid. The reference buffer requires 500 µs to power up and charge the 680 nF decoupling capacitor during the power-up time.

The AD7323 is specified for a 2.5 V to 3 V reference range. When a 3 V reference is selected, the ranges are ±12 V, ±6 V, ±3 V, and 0 V to +12 V. For these ranges, the V

and VSS supply

must be equal to or greater than the maximum analog input range selected (see

Tabl e 6).

The internal reference circuitry consists of a 2.5 V band gap reference and a reference buffer. When operating the AD7323 in internal reference mode, the 2.5 V internal reference is available at the REFIN/OUT pin, which should be decoupled to AGND using a 680 nF capacitor. It is recommended that the internal reference be buffered before applying it elsewhere in the system. The internal reference is capable of sourcing up to 90 A.

On power-up, if the internal reference operation is required for the ADC conversion, a write to the control register is necessary to set the Ref bit to 1. During the control register write, the

DRIVE

The AD7323 has a V the serial interface operates. V

feature to control the voltage at which

DRIVE

allows the ADC to easily

DRIVE

interface to both 3 V and 5 V processors. For example, if the AD7323 is operated with a V

of 5 V, the V

pin can be

DRIVE

powered from a 3 V supply. This allows the AD7323 to accept large bipolar input signals with low voltage digital processing.

Rev. 0 | Page 28 of 36

AD7323

MODES OF OPERATION

The AD7323 has several modes of operation that are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for different application requirements. The mode of operation of the AD7323 is controlled by the power management bits, Bit PM1 and Bit PM0, in the control register as shown in Tabl e 1 1 . The default mode is normal mode, where all internal circuitry is fully powered up.

NORMAL MODE

(PM1 = PM0 = 0)

This mode is intended for the fastest throughput rate performance

, and the

Figure 46

with the AD7323 being fully powered up at all times. shows the general operation of the AD7323 in normal mode.

The conversion is initiated on the falling edge of track-and-hold section enters hold mode, as described in the Serial Interface section. Data on the DIN line during the 16 SCLK transfer is loaded into one of the on-chip registers if the write bit is set. The register is selected by programming the register select bits (see

SCLK

DOUT

DIN

Table 8 ).

116

LEADING ZERO, 2 CHANNEL I.D. BITS, SIGN BIT +

DATA INTO CONTROL/ SEQUENCE /RANGE RE GIST ER

CONVERSION RESULT

Figure 46. Normal Mode

5400-035

The AD7323 remains fully powered up at the end of the conversion if both PM1 and PM0 contain 0 in the control register.

To complete the conversion and access the conversion result, 16 serial clock cycles are required. At the end of the conversion, CS

can idle either high or low until the next conversion.

Once the data transfer is complete, another conversion can be initiated after the quiet time, t

, has elapsed.

QUIET

FULL SHUTDOWN MODE

(PM1 = PM0 = 1)

In this mode, all internal circuitry on the AD7323 is powered down. The part retains information in the registers during full shutdown. The AD7323 remains in full shutdown mode until the power management bits, Bit PM1 and Bit PM0, in the control register are changed.

A write to the control register with PM1 = 1 and PM0 = 1 places the part into full shutdown mode. The AD7323 enters full shutdown mode on the 15 is updated.

If a write to the control register occurs while the part is in full shutdown mode with the power management bits, Bit PM1 and Bit PM0, set to 0 (normal mode), the part begins to power up on the 15 updated.

SCLK rising edge once the control register is

Figure 47 shows how the AD7323 is configured to exit full shutdown mode. To ensure the AD7323 is fully powered up, t

should elapse before the next CS falling edge.

POWER-UP

SCLK rising edge once the control register

THE PARTISFULLYPOWEREDUP ONCE

PART IS IN FULL SHUTDOWN

SCLK

SDATA

DIN

PART BEGINS TO POWER UP ON THE 15TH SCLK RISING EDGE AS PM1 = PM0 = 0

1161

INVALID DATA CHANNE L IDENTI FIER BITS + CONVERSION RESULT

DATA INTO CONTROL REGISTER DATA INTO CONTROL REGIS TER

CONTROL REGI STER IS L OADED ON THE FIRST 15 CL OCKS,

PM1 = 0, PM0 = 0

Figure 47. Exiting Full Shutdown Mode

POWER-UP

TO KEEP THE PART IN NORMAL MODE, LOAD PM1 = PM0 = 0

Rev. 0 | Page 29 of 36

POWER- UP

HAS ELAPSED

IN CONTROL REGISTER

05400-041

AD7323

AUTOSHUTDOWN MODE

(PM1 = 1, PM0 = 0)

Once the autoshutdown mode is selected, the AD7323 automatically enters shutdown on the 15 autoshutdown mode, all internal circuitry is powered down. The AD7323 retains information in the registers during autoshutdown. The track-and-hold is in hold mode during autoshutdown. On the rising which was in hold during shutdown, returns to track as the AD7323 begins to power up. The power-up from autoshutdown is 500 µs.

When the control register is programmed to transition to autoshutdown mode, it does so on the 15 Figure 48 shows the part entering autoshutdown mode. The AD7323 automatically begins to power up on the edge. The t by bringing the

is required before a valid conversion, initiated

POWER-UP

signal low, can take place. Once this valid

conversion is complete, the AD7323 powers down again on the

SCLK rising edge. The CS signal must remain low again to

15 keep the part in autoshutdown mode.

SCLK rising edge. In

edge, the track-and-hold,

SCLK rising edge.

rising

As is the case with autoshutdown mode, the AD7323 enters

standby on the 15 updated (see

SCLK rising edge once the control register is

Figure 48). The part retains information in the registers during standby. The AD7323 remains in standby until it receives a CS

rising edge. On the CS rising edge, the track-and-hold, which

rising edge. The ADC begins to power up on the

was in hold mode while the part was in standby, returns to track.

The power-up time from standby is 700 ns. The user should

ensure that 700 ns have elapsed before bringing

low to attempt a valid conversion. Once this valid conversion is complete, the AD7323 again returns to standby on the 15

The

signal must remain low to keep the part in standby mode.

SCLK rising edge.

Figure 48 shows the part entering autoshutdown mode. The sequence of events is the same when entering autostandby mode. In

Figure 48, the power management bits are configured for autoshutdown. For autostandby mode, the power management bits, PM1 and PM0, should be set to 0 and 1, respectively.

AUTOSTANDBY MODE

(PM1 = 0, PM0 =1)

In autostandby mode, portions of the AD7323 are powered down, but the on-chip reference remains powered up. The reference bit in the control register should be 1 to ensure that the on-chip reference is enabled. This mode is similar to autoshutdown but allows the AD7323 to power up much faster, which allows faster throughput rates.

TBEGINSTOPOWER

UP ON CS RISING EDGE

PART ENTERS SHUTDO WN MODE ON THE 15TH RISING SCLK EDGE

11615 1 1615

SCLK

SDATA

DIN

CONTROL REGI STER IS LOADED ON T HE FIRST 15 CLOCKS,

AS PM1 = 1, PM0 = 0

VAL ID DATA VAL ID DATA

DATA INTO CONTROL REG ISTE R DATA INTO CONTROL REG ISTE R

PM1 = 1, PM0 = 0

Figure 48. Entering Autoshutdown/Autostandby Mode

POWER-UP

THE PART IS F ULLY POWERED UP ONCE

POWER-UP

HAS ELAPSED

5400-042

Rev. 0 | Page 30 of 36

AD7323

POWER VS. THROUGHPUT RATE

The power consumption of the AD7323 varies with throughput rate. The static power consumed by the AD7323 is very low, and significant power savings can be achieved as the throughput rate is reduced. throughput rate for the AD7323 at a V

Figure 49 and Figure 50 shows the power vs.

of 3 V and 5 V,

respectively. Both plots clearly show that the average power consumed by the AD7323 is greatly reduced as the sample frequency is reduced. This is true whether a fixed SCLK value is used or if it is scaled with the sampling frequency.

Figure 49 and Figure 50 show the power consumption when operating in normal mode for a variable SCLK that scales with the sampling frequency.

VCC=3V V

= ±12V

DD/VSS

=25°C

INTERNAL RE FERENCE

VCC=5V V

AVERAGE POWER (mW)

=±12V

DD/VSS

=25°C

INTERNAL REF ERENCE

VARIABLE SCLK

100 200 300 400 500

THROUGHPUT RATE (kSPS)

Figure 50. Power vs. Throughput Rate with 5 V V

05400-053

AVERAGE POWER (mW)

100 200 300 400 500

THROUGHPUT RATE (kSPS)

Figure 49. Power vs. Throughput Rate with 3 V V

VARIABLE SCLK

5400-052

Rev. 0 | Page 31 of 36

AD7323

SERIAL INTERFACE

Figure 51 shows the timing diagram for the serial interface of the AD7323. The serial clock applied to the SCLK pin provides the conversion clock and controls the transfer of information to and from the AD7323 during a conversion.

The

signal initiates the data transfer and the conversion

process. The falling edge of hold mode and takes the bus out of three-state. Then the analog input signal is sampled. Once the conversion is initiated, it requires 16 SCLK cycles to complete.

The track-and-hold goes back into track mode on the 14 rising edge. On the 16

SCLK falling edge, the DOUT line returns to three-state. If the rising edge of cycles have elapsed, the conversion is terminated, and the DOUT line returns to three-state. Depending on where the signal is brought high, the addressed register may be updated.

SCLK

DOUT

THREE-

STATE

DIN

puts the track-and-hold into

SCLK

occurs before 16 SCLK

1 2 3 4 5 13 14 15 16

2 IDENTIFICATION BITS

ADD1

ZERO

WRITE

ADD0 SIGN DB 11 DB10 DB2 DB1 DB0

REG

SEL1

SEL2

Figure 51. Serial Interface Timing Diagram (Control Register Write)

CONVERT

Data is clocked into the AD7323 on the SCLK falling edge. The three MSBs on the DIN line are decoded to select which register is being addressed. The control register is a 12-bit register. If the control register is addressed by the three MSBs, the data on the DIN line is loaded into the control on the 15

SCLK falling edge. If the sequence register or the range register is addressed, the data on the DIN line is loaded into the addressed register on

the 11

SCLK falling edge.

Conversion data is clocked out of the AD7323 on each SCLK falling edge. Data on the DOUT line consists of a ZERO bit, two channel identifier bits, a sign bit, and a 12-bit conversion result. The channel identifier bits are used to indicate which channel corresponds to the conversion result. The ZERO bit is clocked out on the

falling edge, and the ADD1 bit is clocked out on

the first SCLK falling edge.

DON’T

LSBMSB

CARE

THREE-STATE

QUIET

05400-036

Rev. 0 | Page 32 of 36

AD7323

MICROPROCESSOR INTERFACING

The serial interface on the AD7323 allows the part to be directly connected to a range of different microprocessors. This section explains how to interface the AD7323 with some common microcontroller and DSP serial interface protocols.

AD7323 TO ADSP-21xx

The ADSP-21xx family of DSPs interface directly to the AD7323 without requiring glue logic. The V the same supply voltage as that of the ADSP-21xx. This allows the ADC to operate at a higher supply voltage than its serial interface. The SPORT0 on the ADSP-21xx should be configured as shown in

Tabl e 14 .

Table 14. SPORT0 Control Register Setup

Setting Description

TFSW = RFSW = 1 Alternative framing INVRFS = INVTFS = 1 Active low frame signal DTYPE = 00 Right justify data SLEN = 1111 16-bit data-word ISCLK = 1 Internal serial clock TFSR = RFSR = 1 Frame every word IRFS = 0 ITFS = 1

The connection diagram is shown in Figure 52. The ADSP-21xx has TFS0 and RFS0 tied together. TFS0 is set as an output, and RFS0 is set as an input. The DSP operates in alternative framing mode, and the SPORT0 control register is set up as described in Tabl e 14. The frame synchronization signal generated on the TFS

is tied to

, and, as with all signal processing applications, requires equidistant sampling. However, as in this example, the timer interrupt is used to control the sampling rate of the ADC, and under certain conditions equidistant sampling cannot be achieved.

pin of the AD7323 takes

DRIVE

The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given (AX0 = TX0), the state of the serial clock is checked. The DSP waits until the SCLK has gone high, low, and high again before starting the transmission. If the timer and SCLK are chosen so that the instruction to transmit occurs on or near the rising edge of SCLK, data can be transmitted immediately or at the next clock edge.

For example, the ADSP-2111 has a master clock frequency of 16 MHz. If the SCLKDIV register is loaded with the value 3, an SCLK of 2 MHz is obtained, and eight master clock periods elapse for every one SCLK period. If the timer registers are loaded with the value 803, 100.5 SCLKs occur between interrupts and, subsequently, between transmit instructions. This situation leads to nonequidistant sampling because the transmit instruction occurs on an SCLK edge. If the number of SCLKs between interrupts is an integer of N, equidistant sampling is implemented by the DSP.

AD7323 TO ADSP-BF53x

The ADSP-BF53x family of DSPs interfaces directly to the AD7323 without requiring glue logic, as shown in The SPORT0 Receive Configuration 1 register should be set up as outlined in

AD7323

DRIVE

Table 1 5 .

SCLK RSCLK0

DIN

DOUT

ADSP-BF53x

RFS0

DT0

DR0

Figure 53.

AD7323

SCLK

DIN

DRIVE

ADDITIONAL PI NS OMITTED FOR CLARITY.

DOUT

Figure 52. Interfacing the AD7323 to the ADSP-21xx

SCLK0

TFS0

RFS0

DT0

DR0

ADSP-21xx

5400-037

The timer registers are loaded with a value that provides an interrupt at the required sampling interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS, and hence the reading of data.

Rev. 0 | Page 33 of 36

ADDITIONAL PI NS OMITTED FOR CLARITY.

Figure 53. Interfacing the AD7323 to the ADSP-BF53x

Table 15. SPORT0 Receive Configuration 1 Register

Setting Description

RCKFE = 1 Sample data with falling edge of RSCLK LRFS = 1 Active low frame signal RFSR = 1 Frame every word IRFS = 1 Internal RFS used RLSBIT = 0 Receive MSB first RDTYPE = 00 Zero fill IRCLK = 1 Internal receive clock RSPEN = 1 Receive enable SLEN = 1111 16-bit data-word TFSR = RFSR = 1

05400-038

AD7323

APPLICATION HINTS

LAYOUT AND GROUNDING

The printed circuit board that houses the AD7323 should be designed so that the analog and digital sections are confined to certain areas of the board. This design facilitates the use of ground planes that can easily be separated.

To provide optimum shielding for ground planes, a minimum etch technique is generally best. All AGND pins on the AD7323 should be connected to the AGND plane. Digital and analog ground pins should be joined in only one place. If the AD7323 is in a system where multiple devices require an AGND and DGND connection, the connection should still be made at only one point. A star point should be established as close as possible to the ground pins on the AD7323.

Good connections should be made to the power and ground planes. This can be done with a single via or multiple vias for each supply and ground pin.

Avoid running digital lines under the AD7323 device because this couples noise onto the die. However, the analog ground plane should be allowed to run under the AD7323 to avoid noise coupling. The power supply lines to the AD7323 device should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line.

To avoid radiating noise to other sections of the board, components, such as clocks, with fast switching signals should be shielded with digital ground and never run near the analog inputs. Avoid crossover of digital and analog signals. To reduce the effects of feedthrough within the board, traces should be run at right angles to each other. A microstrip technique is the best method, but its use may not be possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, and signals are placed on the other side.

Good decoupling is also important. All analog supplies should be decoupled with 10 µF tantalum capacitors in parallel with

0.1 µF capacitors to AGND. To achieve the best results from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. The

0.1 µF capacitors should have a low effective series resistance (ESR) and low effective series inductance (ESI), such as is typical of common ceramic and surface mount types of capacitors. These low ESR, low ESI capacitors provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.

Rev. 0 | Page 34 of 36

AD7323

OUTLINE DIMENSIONS

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

0.65 BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AB

0.10

0.30

0.19

1.20 MAX

SEATING PLANE

6.40 BSC

0.20

0.09 8°

0°

0.75

0.60

0.45

Figure 54. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions show in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7323BRUZ AD7323BRUZ-REEL AD7323BRUZ-REEL7 EVAL-AD7323CB EVAL-CONTROL BRD2

Z = Pb-free part.

This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL board for evaluation/demonstration purposes.

This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete

evaluation kit, the particular ADC evaluation board (for example, EVAL-AD7323CB), the EVAL-CONTROL BRD2, and a 12 V transformer must be ordered. See the relevant evaluation board technical note for more information.

–40°C to +85°C 16-Lead TSSOP RU-16 –40°C to +85°C 16-Lead TSSOP RU-16 –40°C to +85°C 16-Lead TSSOP RU-16 Evaluation Board Controller Board

Rev. 0 | Page 35 of 36

AD7323

NOTES

Rev. 0 | Page 36 of 36

Datasheet AD7323 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

REVISION HISTORY

SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY

THEORY OF OPERATION

CIRCUIT INFORMATION

CONVERTER OPERATION

Output Coding

Transfer Functions

ANALOG INPUT STRUCTURE

Track-and-Hold Section

TYPICAL CONNECTION DIAGRAM

ANALOG INPUT

Single-Ended Inputs

True Differential Mode

Pseudo Differential Inputs

DRIVER AMPLIFIER CHOICE

REGISTERS

ADDRESSING REGISTERS

CONTROL REGISTER

SEQUENCE REGISTER

RANGE REGISTER

SEQUENCER OPERATION

REFERENCE

MODES OF OPERATION

NORMAL MODE

FULL SHUTDOWN MODE

AUTOSHUTDOWN MODE

AUTOSTANDBY MODE

POWER VS. THROUGHPUT RATE

SERIAL INTERFACE

MICROPROCESSOR INTERFACING

AD7323 TO ADSP-21xx

AD7323 TO ADSP-BF53x

APPLICATION HINTS

LAYOUT AND GROUNDING

OUTLINE DIMENSIONS

ORDERING GUIDE