Analog Devices AD7304 5 c Datasheet

3 V/5 V, Rail-to-Rail

A

FEATURES

Four 8-bit DACs in one package
+3 V, +5 V, and ±5 V operation
Rail-to-rail REF input to voltage output swing

2.6 MHz reference multiplying bandwidth
Internal power-on reset
SPI serial interface-compatible—AD7304
Fast parallel interface—AD7305
40 µA power shutdown

APPLICATIONS

Automotive output span voltage
Instrumentation, digitally controlled calibration
Pin-compatible AD7226 replacement when V

GENERAL DESCRIPTION

The AD7304/AD7305
a single +3 V to +5 V supply, or ±5 V supplies. The AD7304 has
a serial interface, while the AD7305 has a parallel interface.
Internal precision buffers swing rail-to-rail. The reference input
range includes both supply rails, allowing for positive or negative
full-scale output voltages. Operation is guaranteed over the
supply voltage range of 2.7 V to 5.5 V, consuming less than
9 mW from a 3 V supply.

The full-scale voltage output is determined by the external
reference input voltage applied. The rail-to-rail V
DAC V
supply, V

allows for a full-scale voltage set equal to the positive

OUT

, the negative supply, VSS, or any value in between.

DD

1

are quad, 8-bit DACs that operate from

< 5.5 V

DD

REF

input to

Quad, 8-Bit DAC

AD7304/AD7305

FUNCTIONAL BLOCK DIAGRAMS

B

8 8

DAC A

REG

8 8

DAC B

REG

8 8

DAC C

REG

DAC D

REG

LDAC

V

REF

V

REFCVREF

CS

SDI/SHDN

CLK

V

DD

PWR-ON

RESET

SERIAL

REG

V

SS

8

GND

INPUT
REG A

INPUT

REG B

INPUT
REG C

INPUT
REG D

8 8

CLR

Figure 1.

DAC A

REG

DAC B

REG

DAC C

REG

DAC D

REG

LDAC

V

REF

DB0
DB1
DB2
DB3
DB4
DB5
DB6

WR

0/SHDN

V

DD

PWR-ON

RESET

8

8

DECODE

A1

INPUT
REG A

INPUT

REG B

INPUT
REG C

INPUT
REG D

8 8

8 8

8 8

8 8

Figure 2.

When operating from less than 5.5 V, the AD7305 is
pin-compatible with the popular industry-standard AD7226.

V

DAC A

DAC B

DAC C

DAC D

SS

V

REF

DAC A

DAC B

DAC C

DAC D

A

AD7304

D

AD7305

GND

V

OUT

V

OUT

V

OUT

V

OUT

01114-001

V

OUT

V

OUT

V

OUT

V

OUT

01114-002

A

B

C

D

A

B

C

D

The AD7304’s doubled-buffered serial data interface offers high
speed, 3-wire, SPI®-, and microcontroller-compatible inputs
using data in (SDI), clock (CLK), and chip select (

CS

) pins.
Additionally, an internal power-on reset sets the output to zero
scale.

The parallel input AD7305 uses a standard address decode

WR

along with the

control line to load data into the input

registers.

The double-buffered architecture allows all four input registers

LDAC

to be preloaded with new values, followed by an

control
strobe that copies all the new data into the DAC registers,
thereby updating the analog output values.

_______________________ ______________________________

1

Protected under Patent No. 5684481.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

An internal power-on reset places both parts in the zero-scale
state at turn-on. A 40 µA power shutdown (SHDN) feature is
activated on both parts by three-stating the SDI/SHDN pin on
the AD7304 and three-stating the A0/SHDN address pin on the
AD7305.

The AD7304/AD7305 are specified over the extended industrial

−40°C to +85°C and the automotive −40°C to +125°C
temperature ranges. AD7304s are available in a wide-body
16-lead SOIC (R-16) package. The parallel input AD7305 is
available in the wide-body 20-lead SOIC (R-20) surface-mount
package. For ultracompact applications, the thin 1.1 mm,
16-lead TSSOP (RU-16) package is available for the AD7304,
while the 20-lead TSSOP (RU-20) houses the AD7305.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

AD7304/AD7305

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Specifications .................................................................. 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 8

Typical Performance Characteristics ........................................... 10

Circuit Operation ...........................................................................14

DAC Section................................................................................ 14

AD7304 Serial Data Interface ....................................................... 15

AD7304 Hardware Shutdown SHDN...................................... 15

Revision History

11/04—Data Sheet Changed from Rev. B to Rev. C

Update Format ....................................................................Universal

Update Features ................................................................................ 1

Changes to Figure 35...................................................................... 15

Add Power-Up Sequence............................................................... 15

Changes to Figure 36...................................................................... 16

Change to Figure 37 ....................................................................... 16

Updated Outline Dimensions....................................................... 18

AD7304/AD7305 Power-On Reset .......................................... 15

Power up sequence ..................................................................... 15

AD7305 Parallel Data Interface.................................................... 16

AD7226 Pin Compatibility ....................................................... 16

AD7305 Hardware Shutdown SHDN...................................... 16

ESD Protection Circuits ............................................................ 16

Applications..................................................................................... 17

Outline Dimensions ....................................................................... 18

Ordering Guide .......................................................................... 19

2/04—Data Sheet Changed from Rev. A to Rev. B

Renumber TPCs and Figures............................................Universal

Deleted N-16 and N-20 packages.....................................Universal

Changes to Absolute Maximum Ratings....................................... 3

Changes to Ordering Guide............................................................ 4

Updated Outline Dimensions....................................................... 14

3/98—Changed from Rev. 0 to Rev. A

2/98—Revision 0: Initial Version

Rev. C | Page 2 of 20

AD7304/AD7305

SPECIFICATIONS

@ VDD = 3 V or 5 V, VSS = 0 V; or VDD = +5 V and VSS = –5 V, VSS ≤ V

Table 1.

Parameter Symbol Condition 3 V ± 10% 5 V ± 10% ±5 V ± 10% Unit

STATIC PERFORMANCE

Resolution

1

Integral Nonlinearity2 INL

N

Differential Nonlinearity DNL Monotonic, all codes 0 to 0xFF ±1 ±1 ±1 LSB max
Zero-Scale Error V
Full-Scale Voltage Error V
Full-Scale Temperature

Coefficient

3

REFERENCE INPUT

V

Range V

REFIN

Input Resistance (AD7304) R
Input Resistance (AD7305) R
Input Capacitance

3

ANALOG OUTPUTS

Output Voltage Range V
Output Current Drive I
Shutdown Resistance R

Data = 0x00 15 15 ±15 mV max

ZSE

Data = 0xFF ±4 ±4 ±4 LSB max

FSE

TCV

FS

REFIN

REFIN

REFIN

C

REFIN

Code = 0x55 28 28 28 kΩ typ
All DACs at code = 0x55 7.5 7.5 7.5 kΩ typ

OUT

Code = 0x80, ∆V

OUT

DAC outputs placed in shutdown

OUT

< 1 LSB ±3 ±3 ±3 mA typ

OUT

state

Capacitive Load

3

LOGIC INPUTS

Logic Input Low Voltage VIL
Logic Input High Voltage VIH
Input Leakage Current5 IIL
Input Capacitance

AC CHARACTERISTICS

3

3

CL No oscillation 200 200 200 pF typ

CIL

Output Slew Rate SR Code = 0x00 to 0xFF to 0x00 1/2.7 1/3.6 1.0/3.6 V/µs min/typ
Reference Multiplying BW Small signal, VSS = –5 V
Total Harmonic Distortion THD V

= 4 V p-p, VSS = –5 V, f = 1 kHz

REF

Settling Time6 tS To ±0.1% of full scale 1.1/2 1.0/2 1.0/2 µs typ/max
Shutdown Recovery Time t
Time to Shutdown t

SDR

SDN

DAC Glitch Q
Digital Feedthrough Q
Feedthrough V

SUPPLY CHARACTERISTICS

OUT/VREF

Positive Supply Current IDD V

To ±0.1% of full scale 2 2 2 µs max

Code = 0x00, V

= 0 V or VDD, no load 6 6 6 mA max

LOGIC

= 1 V p-p, f = 100 kHz

REF

Negative Supply Current ISS VSS = –5 V
Power Dissipation P
Power Down I

V

DISS

SDI/SHDN = floating 40 40 40 µA typ

DD_SD

= 0 V or VDD, no load 15 30 60 mW max

LOGIC

Power Supply Sensitivity PSS ∆VDD = ±10% 0.004 0.004 0.004 %/%

1

One LSB = V

2

The first three codes (0x00, 0x01, 0x10) are excluded from the integral nonlinearity error measurement in single-supply operation 3 V or 5 V.

3

These parameters are guaranteed by design and not subject to production testing.

4

Typical specifications represent average readings measured at 25°C.

5

The SDI/SHDN and A0/SHDN pins have a 30 µA maximum IIL input leakage current.

6

The settling time specification does not apply for negative going transitions within the last three LSBs of ground in single-supply operation.

REF

/256.

≤ VDD, −40°C < TA < +85°C/+125°C, unless otherwise noted.

REF

8 8 8 Bits
±1 ±1 ±1 LSB max

5 5 5 ppm/°C typ4

VSS/VDD VSS/VDD VSS/VDD V min/max

5 5 5 pF typ

VSS/VDD VSS/VDD VSS/VDD V min/max

120 120 120 kΩ typ

0.6 0.8 0.8 V min

2.1 2.4 2.4 V max
±10 ±10 ±10 µA max
8 8 8 pF max

2.6 MHz typ

0.025 %

15 15 15 µs typ
15 15 15 nVs typ
2 2 2 nVs typ

−65 dB

6 mA max

Rev. C | Page 3 of 20

AD7304/AD7305

+5V

= 10V p-p

V

REF

f = 20kHz

+5V

0V

0V

V

= 10V p-p

OUT

–5V

(OUT)

Figure 3. Rail-to-Rail Reference Input to Output at 20 kHz

–5V

(IN)

01114-003

TIMING SPECIFICATIONS

@ VDD = 3 V or 5 V, VSS = 0 V; or VDD = +5 V and VSS = –5 V, VSS ≤ V

Table 2.

Parameter Symbol 3 V ± 10% 5 V ± 10% ±5 V ± 10% Unit
INTERFACE TIMING SPECIFICATIONS
AD7304 Only

1, 2

Clock Width High tCH 70 55 55 ns min
Clock Width Low tCL 70 55 55 ns min
Data Setup tDS 50 40 40 ns min
Data Hold tDH 30 20 20 ns min
Load Pulse Width t
Load Setup t
Load Hold t
Clear Pulse Width t
Select t
Deselect t

AD7305 Only

70 60 60 ns min

LDW

40 30 30 ns min

LD1

40 30 30 ns min

LD2

60 60 60 ns min

CLWR

30 20 20 ns min

CSS

60 40 40 ns min

CSH

Data Setup tDS 60 40 40 ns min
Data Hold tDH 30 20 20 ns min
Address Setup tAS 60 40 40 ns min
Address Hold tAH 30 20 20 ns min
Write Width tWR 60 50 50 ns min
Load Pulse Width t

60 50 50 ns min

LDW

Load Setup tLS 60 40 40 ns min
Load Hold t

LH

1

These parameters are guaranteed by design and not subject to production testing.

2

All input control signals are specified with tR = tF = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

≤ VDD, –40°C < TA < +85°C/+125°C, unless otherwise noted.

REF

30 20 20 ns min

Rev. C | Page 4 of 20

AD7304/AD7305

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VDD to GND

VSS to GND

V

to GND VSS, V

REFX

Logic Inputs to GND

V

to GND

OUTX

I

Short-Circuit to GND 50 mA

OUT

Package Power Dissipation

Thermal Resistance θ

JA

−0.3 V, +8 V

+0.3 V, −8 V

DD

−0.3 V, V

−0.3 V, V

(T

J MAX

DD

DD

– TA)/θ

+ 0.3 V

+ 0.3 V

JA

16-Lead SOIC Package (R-16) 73°C/W
16-Lead TSSOP Package (RU-16) 180°C/W
20-Lead SOIC Package (R-20) 74°C/W

20-Lead TSSOP Package (RU-20) 155°C/W
Maximum Junction Temperature (T
Operating Temperature Range

Storage Temperature Range

Lead Temperature

) 150°C

J MAX

−40°C to +85°C

−65°C to +150°C

R-16, R-20, RU-16, RU-20 (Vapor Phase, 60 sec) 235°C

R-16, R-20, RU-16, RU-20 (Infrared, 15 sec) 220°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. C | Page 5 of 20

AD7304/AD7305

V

LDAC

LDAC

OUT

SDI

CLK

CS

SDI

CLK

CLR

SA SI A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

t

CSS

t

LD1

tDSt

t

CL

FS

ZS

DH

t

CH

t

LDW

t

S

Figure 4. AD7304 General Timing Diagram

t

CSH

±1 LSB

ERROR BAND

t

LD2

t

CLRW

t

S

01114-004

t

SDN

SDI/SHDN

I

DD

Figure 5. AD7304 Timing Diagram Zoom In

t

SDR

01114-005

Table 4. AD7304 Control Logic Truth Table

CS

1

CLK1

LDAC CLR

H X H H No effect No effect No effect
L
↑+

H H Data advanced 1 bit No effect No effect

↑

+

L H H No effect Updated with SR contents2 No effect
H X L H No effect
H X H
H X H

1

Serial Shift Register Function Input REG Function DAC Register Function

Latched with SR contents2

No effect Loaded with 0x00 Loaded with 0x00

↓

–

No effect Latched with 0x00 Latched with 0x00

↑

+

All input register contents transferred3

1

↑+ positive logic transition; ↓– negative logic transition; X Don’t Care.

2

One input register receives the data bits D7–D0 decoded from the SR address bits (A1, A0), where REG A = (0, 0), B = (0, 1), C = (1, 0), and D = (1, 1).

3

LDAC

is a level-sensitive input.

Table 5. AD7304 Serial Input Register Data Format, Data is Loaded in MSB-First Format

MSB

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1

LSB
B0

AD7304 SAC SDC A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

If B11 (SAC), Shutdown All Channels, is set to logic low, all DACs are placed in a power shutdown mode, and all output voltages become
high resistance. If B10 (SDC), Shutdown Decoded Channel, is set to logic low, only the DAC decoded by Address Bits A1 and A0 is placed
in shutdown mode.

Rev. C | Page 6 of 20