Datasheet AD7304 Datasheet (Analog Devices)

3 V/5 V, Rail-to-Rail

A

FEATURES

Four 8-bit DACs in one package
+3 V, +5 V, and ±5 V operation
Rail-to-rail REF input to voltage output swing

2.6 MHz reference multiplying bandwidth
Internal power-on reset
SPI serial interface-compatible—AD7304
Fast parallel interface—AD7305
40 µA power shutdown

APPLICATIONS

Automotive output span voltage
Instrumentation, digitally controlled calibration
Pin-compatible AD7226 replacement when V

GENERAL DESCRIPTION

The AD7304/AD7305
a single +3 V to +5 V supply, or ±5 V supplies. The AD7304 has
a serial interface, while the AD7305 has a parallel interface.
Internal precision buffers swing rail-to-rail. The reference input
range includes both supply rails, allowing for positive or negative
full-scale output voltages. Operation is guaranteed over the
supply voltage range of 2.7 V to 5.5 V, consuming less than
9 mW from a 3 V supply.

The full-scale voltage output is determined by the external
reference input voltage applied. The rail-to-rail V
DAC V
supply, V

allows for a full-scale voltage set equal to the positive

OUT

, the negative supply, VSS, or any value in between.

DD

1

are quad, 8-bit DACs that operate from

< 5.5 V

DD

REF

input to

Quad, 8-Bit DAC

AD7304/AD7305

FUNCTIONAL BLOCK DIAGRAMS

B

8 8

DAC A

REG

8 8

DAC B

REG

8 8

DAC C

REG

DAC D

REG

LDAC

V

REF

V

REFCVREF

CS

SDI/SHDN

CLK

V

DD

PWR-ON

RESET

SERIAL

REG

V

SS

8

GND

INPUT
REG A

INPUT

REG B

INPUT
REG C

INPUT
REG D

8 8

CLR

Figure 1.

DAC A

REG

DAC B

REG

DAC C

REG

DAC D

REG

LDAC

V

REF

DB0
DB1
DB2
DB3
DB4
DB5
DB6

WR

0/SHDN

V

DD

PWR-ON

RESET

8

8

DECODE

A1

INPUT
REG A

INPUT

REG B

INPUT
REG C

INPUT
REG D

8 8

8 8

8 8

8 8

Figure 2.

When operating from less than 5.5 V, the AD7305 is
pin-compatible with the popular industry-standard AD7226.

V

DAC A

DAC B

DAC C

DAC D

SS

V

REF

DAC A

DAC B

DAC C

DAC D

A

AD7304

D

AD7305

GND

V

OUT

V

OUT

V

OUT

V

OUT

01114-001

V

OUT

V

OUT

V

OUT

V

OUT

01114-002

A

B

C

D

A

B

C

D

The AD7304’s doubled-buffered serial data interface offers high
speed, 3-wire, SPI®-, and microcontroller-compatible inputs
using data in (SDI), clock (CLK), and chip select (

CS

) pins.
Additionally, an internal power-on reset sets the output to zero
scale.

The parallel input AD7305 uses a standard address decode

WR

along with the

control line to load data into the input

registers.

The double-buffered architecture allows all four input registers

LDAC

to be preloaded with new values, followed by an

control
strobe that copies all the new data into the DAC registers,
thereby updating the analog output values.

_______________________ ______________________________

1

Protected under Patent No. 5684481.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

An internal power-on reset places both parts in the zero-scale
state at turn-on. A 40 µA power shutdown (SHDN) feature is
activated on both parts by three-stating the SDI/SHDN pin on
the AD7304 and three-stating the A0/SHDN address pin on the
AD7305.

The AD7304/AD7305 are specified over the extended industrial

−40°C to +85°C and the automotive −40°C to +125°C
temperature ranges. AD7304s are available in a wide-body
16-lead SOIC (R-16) package. The parallel input AD7305 is
available in the wide-body 20-lead SOIC (R-20) surface-mount
package. For ultracompact applications, the thin 1.1 mm,
16-lead TSSOP (RU-16) package is available for the AD7304,
while the 20-lead TSSOP (RU-20) houses the AD7305.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

AD7304/AD7305

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Specifications .................................................................. 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 8

Typical Performance Characteristics ........................................... 10

Circuit Operation ...........................................................................14

DAC Section................................................................................ 14

AD7304 Serial Data Interface ....................................................... 15

AD7304 Hardware Shutdown SHDN...................................... 15

Revision History

11/04—Data Sheet Changed from Rev. B to Rev. C

Update Format ....................................................................Universal

Update Features ................................................................................ 1

Changes to Figure 35...................................................................... 15

Add Power-Up Sequence............................................................... 15

Changes to Figure 36...................................................................... 16

Change to Figure 37 ....................................................................... 16

Updated Outline Dimensions....................................................... 18

AD7304/AD7305 Power-On Reset .......................................... 15

Power up sequence ..................................................................... 15

AD7305 Parallel Data Interface.................................................... 16

AD7226 Pin Compatibility ....................................................... 16

AD7305 Hardware Shutdown SHDN...................................... 16

ESD Protection Circuits ............................................................ 16

Applications..................................................................................... 17

Outline Dimensions ....................................................................... 18

Ordering Guide .......................................................................... 19

2/04—Data Sheet Changed from Rev. A to Rev. B

Renumber TPCs and Figures............................................Universal

Deleted N-16 and N-20 packages.....................................Universal

Changes to Absolute Maximum Ratings....................................... 3

Changes to Ordering Guide............................................................ 4

Updated Outline Dimensions....................................................... 14

3/98—Changed from Rev. 0 to Rev. A

2/98—Revision 0: Initial Version

Rev. C | Page 2 of 20

AD7304/AD7305

SPECIFICATIONS

@ VDD = 3 V or 5 V, VSS = 0 V; or VDD = +5 V and VSS = –5 V, VSS ≤ V

Table 1.

Parameter Symbol Condition 3 V ± 10% 5 V ± 10% ±5 V ± 10% Unit

STATIC PERFORMANCE

Resolution

1

Integral Nonlinearity2 INL

N

Differential Nonlinearity DNL Monotonic, all codes 0 to 0xFF ±1 ±1 ±1 LSB max
Zero-Scale Error V
Full-Scale Voltage Error V
Full-Scale Temperature

Coefficient

3

REFERENCE INPUT

V

Range V

REFIN

Input Resistance (AD7304) R
Input Resistance (AD7305) R
Input Capacitance

3

ANALOG OUTPUTS

Output Voltage Range V
Output Current Drive I
Shutdown Resistance R

Data = 0x00 15 15 ±15 mV max

ZSE

Data = 0xFF ±4 ±4 ±4 LSB max

FSE

TCV

FS

REFIN

REFIN

REFIN

C

REFIN

Code = 0x55 28 28 28 kΩ typ
All DACs at code = 0x55 7.5 7.5 7.5 kΩ typ

OUT

Code = 0x80, ∆V

OUT

DAC outputs placed in shutdown

OUT

< 1 LSB ±3 ±3 ±3 mA typ

OUT

state

Capacitive Load

3

LOGIC INPUTS

Logic Input Low Voltage VIL
Logic Input High Voltage VIH
Input Leakage Current5 IIL
Input Capacitance

AC CHARACTERISTICS

3

3

CL No oscillation 200 200 200 pF typ

CIL

Output Slew Rate SR Code = 0x00 to 0xFF to 0x00 1/2.7 1/3.6 1.0/3.6 V/µs min/typ
Reference Multiplying BW Small signal, VSS = –5 V
Total Harmonic Distortion THD V

= 4 V p-p, VSS = –5 V, f = 1 kHz

REF

Settling Time6 tS To ±0.1% of full scale 1.1/2 1.0/2 1.0/2 µs typ/max
Shutdown Recovery Time t
Time to Shutdown t

SDR

SDN

DAC Glitch Q
Digital Feedthrough Q
Feedthrough V

SUPPLY CHARACTERISTICS

OUT/VREF

Positive Supply Current IDD V

To ±0.1% of full scale 2 2 2 µs max

Code = 0x00, V

= 0 V or VDD, no load 6 6 6 mA max

LOGIC

= 1 V p-p, f = 100 kHz

REF

Negative Supply Current ISS VSS = –5 V
Power Dissipation P
Power Down I

V

DISS

SDI/SHDN = floating 40 40 40 µA typ

DD_SD

= 0 V or VDD, no load 15 30 60 mW max

LOGIC

Power Supply Sensitivity PSS ∆VDD = ±10% 0.004 0.004 0.004 %/%

1

One LSB = V

2

The first three codes (0x00, 0x01, 0x10) are excluded from the integral nonlinearity error measurement in single-supply operation 3 V or 5 V.

3

These parameters are guaranteed by design and not subject to production testing.

4

Typical specifications represent average readings measured at 25°C.

5

The SDI/SHDN and A0/SHDN pins have a 30 µA maximum IIL input leakage current.

6

The settling time specification does not apply for negative going transitions within the last three LSBs of ground in single-supply operation.

REF

/256.

≤ VDD, −40°C < TA < +85°C/+125°C, unless otherwise noted.

REF

8 8 8 Bits
±1 ±1 ±1 LSB max

5 5 5 ppm/°C typ4

VSS/VDD VSS/VDD VSS/VDD V min/max

5 5 5 pF typ

VSS/VDD VSS/VDD VSS/VDD V min/max

120 120 120 kΩ typ

0.6 0.8 0.8 V min

2.1 2.4 2.4 V max
±10 ±10 ±10 µA max
8 8 8 pF max

2.6 MHz typ

0.025 %

15 15 15 µs typ
15 15 15 nVs typ
2 2 2 nVs typ

−65 dB

6 mA max

Rev. C | Page 3 of 20

AD7304/AD7305

+5V

= 10V p-p

V

REF

f = 20kHz

+5V

0V

0V

V

= 10V p-p

OUT

–5V

(OUT)

Figure 3. Rail-to-Rail Reference Input to Output at 20 kHz

–5V

(IN)

01114-003

TIMING SPECIFICATIONS

@ VDD = 3 V or 5 V, VSS = 0 V; or VDD = +5 V and VSS = –5 V, VSS ≤ V

Table 2.

Parameter Symbol 3 V ± 10% 5 V ± 10% ±5 V ± 10% Unit
INTERFACE TIMING SPECIFICATIONS
AD7304 Only

1, 2

Clock Width High tCH 70 55 55 ns min
Clock Width Low tCL 70 55 55 ns min
Data Setup tDS 50 40 40 ns min
Data Hold tDH 30 20 20 ns min
Load Pulse Width t
Load Setup t
Load Hold t
Clear Pulse Width t
Select t
Deselect t

AD7305 Only

70 60 60 ns min

LDW

40 30 30 ns min

LD1

40 30 30 ns min

LD2

60 60 60 ns min

CLWR

30 20 20 ns min

CSS

60 40 40 ns min

CSH

Data Setup tDS 60 40 40 ns min
Data Hold tDH 30 20 20 ns min
Address Setup tAS 60 40 40 ns min
Address Hold tAH 30 20 20 ns min
Write Width tWR 60 50 50 ns min
Load Pulse Width t

60 50 50 ns min

LDW

Load Setup tLS 60 40 40 ns min
Load Hold t

LH

1

These parameters are guaranteed by design and not subject to production testing.

2

All input control signals are specified with tR = tF = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

≤ VDD, –40°C < TA < +85°C/+125°C, unless otherwise noted.

REF

30 20 20 ns min

Rev. C | Page 4 of 20

AD7304/AD7305

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VDD to GND

VSS to GND

V

to GND VSS, V

REFX

Logic Inputs to GND

V

to GND

OUTX

I

Short-Circuit to GND 50 mA

OUT

Package Power Dissipation

Thermal Resistance θ

JA

−0.3 V, +8 V

+0.3 V, −8 V

DD

−0.3 V, V

−0.3 V, V

(T

J MAX

DD

DD

– TA)/θ

+ 0.3 V

+ 0.3 V

JA

16-Lead SOIC Package (R-16) 73°C/W
16-Lead TSSOP Package (RU-16) 180°C/W
20-Lead SOIC Package (R-20) 74°C/W

20-Lead TSSOP Package (RU-20) 155°C/W
Maximum Junction Temperature (T
Operating Temperature Range

Storage Temperature Range

Lead Temperature

) 150°C

J MAX

−40°C to +85°C

−65°C to +150°C

R-16, R-20, RU-16, RU-20 (Vapor Phase, 60 sec) 235°C

R-16, R-20, RU-16, RU-20 (Infrared, 15 sec) 220°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. C | Page 5 of 20

AD7304/AD7305

V

LDAC

LDAC

OUT

SDI

CLK

CS

SDI

CLK

CLR

SA SI A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

t

CSS

t

LD1

tDSt

t

CL

FS

ZS

DH

t

CH

t

LDW

t

S

Figure 4. AD7304 General Timing Diagram

t

CSH

±1 LSB

ERROR BAND

t

LD2

t

CLRW

t

S

01114-004

t

SDN

SDI/SHDN

I

DD

Figure 5. AD7304 Timing Diagram Zoom In

t

SDR

01114-005

Table 4. AD7304 Control Logic Truth Table

CS

1

CLK1

LDAC CLR

H X H H No effect No effect No effect
L
↑+

H H Data advanced 1 bit No effect No effect

↑

+

L H H No effect Updated with SR contents2 No effect
H X L H No effect
H X H
H X H

1

Serial Shift Register Function Input REG Function DAC Register Function

Latched with SR contents2

No effect Loaded with 0x00 Loaded with 0x00

↓

–

No effect Latched with 0x00 Latched with 0x00

↑

+

All input register contents transferred3

1

↑+ positive logic transition; ↓– negative logic transition; X Don’t Care.

2

One input register receives the data bits D7–D0 decoded from the SR address bits (A1, A0), where REG A = (0, 0), B = (0, 1), C = (1, 0), and D = (1, 1).

3

LDAC

is a level-sensitive input.

Table 5. AD7304 Serial Input Register Data Format, Data is Loaded in MSB-First Format

MSB

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1

LSB
B0

AD7304 SAC SDC A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

If B11 (SAC), Shutdown All Channels, is set to logic low, all DACs are placed in a power shutdown mode, and all output voltages become
high resistance. If B10 (SDC), Shutdown Decoded Channel, is set to logic low, only the DAC decoded by Address Bits A1 and A0 is placed
in shutdown mode.

Rev. C | Page 6 of 20

AD7304/AD7305

Table 6. AD7305 Control Logic Truth Table

1

A1 A0

WR

L L L H Register A loaded with DB0 to DB7 Latched with previous contents, no change
↑+

L L H Register A latched with DB0 to DB7 Latched with previous contents, no change
L L H H Register B loaded with DB0 to DB7 Latched with previous contents, no change
↑+

L H H Register B latched with DB0 to DB7 Latched with previous contents, no change
L H L H Register C loaded with DB0 to DB7 Latched with previous contents, no change
↑+

H L H Register C latched with DB0 to DB7 Latched with previous contents, no change
L H H H Register D loaded with DB0 to DB7 Latched with previous contents, no change
↑+

H H H Register D latched with DB0 to DB7 Latched with previous contents, no change
H X X L No effect All input register contents loaded, register transparent
L X X L Input register x transparent to DB0 to DB7 Register transparent
H X X
H X X H No effect, device not selected No effect, device not selected

1

↑+ positive logic transition; ↓– negative logic transition; X don’t care.

2

LDAC

is a level-sensitive input.

LDAC

↑+

2

Input Register Function DAC Register Function

No effect All input register contents latched

A0/SHDN

I

A0, A1

D0–D7

LDAC

DD

t

WR

WR

t

t

AS

AH

t

t

DS

DH

t

LS

V

OUT

t

LH

t

S

Figure 6. AD7305 General Timing Diagram

t

SDN

Figure 7. AD7305 Timing Diagram Zoom In

t

LDW

±1 LSB

ERROR BAND

t

SDR

01114-006

01114-007

Rev. C | Page 7 of 20

AD7304/AD7305

V

V

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

OUT
OUT

V

REF

V

REF

GND

LDAC

CLR

B
A

V

SS

A
B

1
2
3

AD7304

4

TOP VIEW

(Not to Scale)

5
6
7
8

16

V
V

15

V

14

V

13

V

12
11

SDI/SHDN

10

CLK

9

CS

OUT
OUT
DD
REF
REF

C
D

C
D

01114-008

Figure 8. AD7304 Pin Configuration

Table 7. AD7304 Pin Function Descriptions

Pin No. Mnemonic Description

1 V

OUT

B

Channel B Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V
Output is open circuit when SHDN is enabled.

2 V

OUT

A

Channel A Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V
Output is open circuit when SHDN is enabled.

3 VSS

4 V
5 V

REF

REF

A Channel A Reference Input. Establishes V
B Channel B Reference Input. Establishes V

Negative Power Supply Input. Specified range of operation is 0 V to −5.5 V.

full-scale voltage. Specified range of operation is VSS < V

OUTA

B full-scale voltage. Specified range of operation is VSS < V

OUT

6 GND Common Analog and Digital Ground.
7

LDAC Load DAC Register Strobe, Active Low. Simultaneously transfers data from all four input registers into the

corresponding DAC registers. Asynchronous active low input. DAC register is transparent when
Table 4 for operation.

8

CLR Clears All Input and DAC Registers to the Zero Condition. Asynchronous active low input. The serial register is

not effected.

9

10 CLK
11 SDI/SHDN

CS Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial input register data to

the decoded input register when

CS returns high. Does not effect LDAC operation.
Clock Input, Positive Edge Clocks Data into Shift Register. Disabled by chip select
Serial Data Input Loads Directly into the Shift Register, MSB First. Hardware shutdown (SHDN) control input,

active when pin is left floating by a three-state logic driver. Does not effect DAC register contents as long as

.

DD

full-scale voltage. Specified range of operation is VSS < V

OUTD

C full-scale voltage. Specified range of operation is VSS V

OUT

12 V
13 V

power is present on V

D Channel D Reference Input. Establishes V

REF

C Channel C Reference Input. Establishes V

REF

14 VDD Positive Power Supply Input. Specified range of operation is 2.7 V to 5.5 V.
15 V

OUT

D

Channel D Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V
Output is open circuit when SHDN is enabled.

16 V

OUT

C

Channel C Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V
Output is open circuit when SHDN is enabled.

CS.

B pin.

REF

A pin.

REF

A < VDD.

REF

B < VDD.

REF

LDAC = 0. See

D < VDD.

REF

C < VDD.

REF

D pin.

REF

C pin.

REF

Rev. C | Page 8 of 20

AD7304/AD7305

V

V

1

B

OUT

2

A

OUT

3

V

SS

AD7305

4

V

REF

GND

LDAC

DB7
DB6
DB5
DB4

(Not to Scale)

5

6

7

8

9

10

TOP VIEW

Figure 9. AD7305 Pin Configuration

Table 8. AD7305 Pin Function Description

Pin No. Mnemonic Description

1 V

OUT

B

Channel B Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V
open circuit when SHDN is enabled.

2 V

OUT

A

Channel A Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V

open circuit when SHDN is enabled.
3 VSS Negative Power Supply Input. Specified range of operation is 0 V to –5.5 V.
4 V

Channel B Reference Input. Establishes V

REF

OUT

5 GND Common Analog and Digital Ground.
6

LDAC

Load DAC Register Strobe, Active Low. Simultaneously transfers data from all four input registers into the

corresponding DAC registers. Asynchronous active low input. DAC register is transparent when

for operation.
7 DB7 MSB Digital Input Data Bit.
8 DB6 Data Bit 6.
9 DB5 Data Bit 5.
10 DB4 Data Bit 4.
11 DB3 Data Bit 3.
12 DB2 Data Bit 2.
13 DB1 Data Bit 1.
14 DB0 LSB Digital Input Data Bit.
15

WR

Write Data into Input Register Control Line, Active Low. See Table 6 for operation.
16 A1 Address Bit 1.

17 A0/SHDN

Address Bit 0/Hardware Shutdown (SHDN) Control Input, Active When Pin Is Left Floating by a Three-State Logic

Driver. Does not effect DAC register contents as long as power is present on V
18 VDD Positive Power Supply Input. Specified range of operation is 2.7 V to 5.5 V.
19 V

OUT

D

Channel D Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V

open circuit when SHDN is enabled.
20 V

OUT

C

Channel C Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V

open circuit when SHDN is enabled.

20

C

V

OUT

19

D

V

OUT

18

V

DD

17

A0/SHDN

16

A1

15

WR

14

DB0

13

DB1

12

DB2

11

DB3

01114-009

full-scale voltage. Specified range of operation is VSS < V

LDAC = 0. See Table 6

.

DD

B pin. Output is

REF

A pin. Output is

REF

< VDD.

REF

D pin. Output is

REF

C pin. Output is

REF

Rev. C | Page 9 of 20

AD7304/AD7305

TYPICAL PERFORMANCE CHARACTERISTICS

144

VDD = +5V
VSS = –5V

120

V

= V

REF

DD

DATA = 0x00

96

72

SINK CURRENT (mA)

48

OUT

I

24

INL (LSB)

1.0

0.6

0.2

–0.2

–0.6

VDD = +5V
V

= –5V

SS

DATA = 0x80
T

= +25°C

A

DAC D

DAC B

DAC C

DAC A

0

015

3

Figure 10. I

–35

–28

–21

–14

SOURCE CURRENT (mA)

OUT

I

–7

0

4.0 5.04.2

INL (LSB)

Figure 11. I

+1

0
–1
+1

0
–1

+1

0
–1
+1

0
–1

0 25632

OUT

DAC A

DAC B

DAC C

DAC D

6912

V

(mV)

OUT

Sink vs. V

OUT

V

OUT

SOURCE vs. V

64 96 128 160 192 224

Rail-to-Rail Performance

OUT

VDD = +5V
V

SS

V

REF

DATA = 0xFF

4.4 4.6 4.8

OUTPUT VOLTAGE (V)

Rail-to-Rail Performance

OUT

VDD = +5V
V

SS

V

REF

T

A

CODE (Decimal)

= –5V

= V

= –5V

= +2.5V

= +25°C

DD

01114-010

01114-011

01114-012

–1.0

–5.0 5.0–3.0

0.500

0.375

0.250

0.125

0

DNL (LSB)

–0.125

–0.250

–0.375

–0.500

4.0

3.6

3.2

2.8

ZERO-SCALE VOLTAGE (mV)

2.4

2.0

0 25632

VDD = 5.5V
V

SS

V

REF

–55 125–35

= 0V

–1.0 1.0 3.0

REFERENCE INPUT VOLTAGE (V)

Figure 13. INL vs. Reference Input Voltage

VDD = +5V
V

SS

V

REF

64 96 128 160 192 224

CODE (Decimal)

Figure 14. DNL vs. Code

= 5.45V

–15 5 25 45 65 85 105

TEMPERATURE (°C)

= –5V

= +2.5V

01114-013

01114-014

01114-015

Figure 12. INL vs. Code, All DAC Channels

Figure 15. Zero-Scale Voltage vs. Temperature

Rev. C | Page 10 of 20

AD7304/AD7305

V

OUT

V

REFIN

(±5V @

50kHz)

V

OUT

CS

VDD = 5V

= 4V

V

REF

DATA = 0x00 0xFF

0V

5V

0V

2µs/DIV

01114-016

Figure 16. Large-Signal Settling Time

DATA = 0xFF

A

+5V

0V

–5V

+5V

0V

–5V

NO LOAD

RL = 70kΩ

RL = 10kΩ

5µs/DIV

Figure 19. Time to Shutdown

V
C

V

DD

= 5V

DD

= 150pF

L

= 5V

CS

V

OUT

CS

I

DD

1mA/V

V

OUT

01114-019

2µs/DIV

Figure 17. Multiplying Mode Step Response and Output Slew Rate

6

4

0

GAIN (dB)

–4

–6

–8

10k 10M

FREQUENCY (Hz)

f

–3dB

VDD = +5V
V

SS

DATA = 0xFF
V

REF

= 2.6MHz

1M100k

= –5V

= 100mV rms

Figure 18. Multiplying Mode Gain vs. Frequency

01114-017

01114-018

0.1

THD (%)

0.01

0.001

Figure 20. Shutdown Recovery Time (Wakeup)

10

1

10m 101

23456789

V

AMPLITUDE (V p-p)

REF

Figure 21. THD vs. Reference Input Amplitude

VDD = +5V

= –5V

V

SS

01114-020

01114-021

Rev. C | Page 11 of 20

AD7304/AD7305

1

VDD = +5V

= –5V

V

SS

0.1

THD (%)

0.01

VDD = +5V

= –5V

V

SS

= +2.5V

V

REF

V

OUT

CS

F = 1MHz
DATA = 0x80 0x7F

0.001
20 100k100

1k 10k

FREQUENCY (Hz)

Figure 22. THD vs. Frequency

3.0

2.4

V/ Hz)

µ

1.8

1.2

NOISE DENSITY (

0.6

0

1 100k10

100 1k 10k

FREQUENCY (Hz)

Figure 23. Output Noise Voltage Density vs. Frequency

VDD = +5V

= –5V

V

SS

V

= +4V

REF

DATA = 0xFF

01114-022

01114-023

40
20

0
–20

–40

–60

–80

CROSS TALK (dB)

–100

–120

–140
–160

100 10M1k

60

50

Figure 25. Midscale Transition Glitch

VDD = +5V
V

= –5V

SS

V

= 50mV rms

REF

DAC A DATA = 0xFF
DAC B, DAC C, DAC D DATA = 0x00

10k 1M

FREQUENCY (Hz)

100k

Figure 26. Cross talk vs. Frequency

–PSRR, VSS = –5V ±∆10%

+PSRR, VDD = +5V ±∆10%

CT = 20 LOG

01114-025

V

B

OUT

V

REF

01114-026

B

V

OUT

= +5V

V

DD

= –5V

V

SS

= +2.5V

V

REF

DAC A = 0xFF
DAC B = 0x00
F = 2MHz

CLK

50ns/DIV

50ns/DIV

01114-024

Figure 24. Digital Feedthrough

40

30

PSRR (dB)

20

10

0

10 100

–PSRR, VSS = –3V ±∆10%

+PSRR, VDD = +3V ±∆10%

DATA = 0x80
T

A

1k 100k

FREQUENCY (Hz)

10k

Figure 27. Power-Supply Rejection vs. Frequency

= +25°C

01114-027

Rev. C | Page 12 of 20

AD7304/AD7305

12

VDD = +5V
V

= –5V

10

8

SS

= +2.5V

V

REF

A0 = +5V
ALL OTHER DIGITAL
PINS VARYING

80

70

60

VDD = +5.5V

= –5.5V

V

SS

V

= +2.5V

REF

PIN A0 FLOATING

SUPPLY CURRENT (mA)

6

4

2

0

051

DIGITAL INPUT VOLTAGE (V)

I

DD

I

SS

234

Figure 28. Supply Current vs. Digital Input Voltage

10

1

VDD = +5V
V

0.1

0.01

SUPPLY CURRENT (mA)

0.001

0.0001
051

I

DD

I

SS

234

DIGITAL INPUT VOLTAGE (V)

= –5V

SS

= +2.5V

V

REF

ALL DIGITAL PINS VARY,
EXCEPT A0 = +5V

Figure 29. Shutdown Supply Current vs. Digital Input Voltage (A0 Only)

5.0
VDD = +5V

= –5V

V

SS

= +2.5V

V

4.4

REF

01114-028

01114-029

50

40

SHUTDOWN SUPPLY (µA)

30

20

–55 125–35

–15 5 25 45 65 85 105

TEMPERATURE (°C)

Figure 31. Shutdown Supply Current vs. Temperature

0.08
READING MADE AT TA = +25°C

SAMPLE SIZE = 924 UNITS

0.04

VDD = +2.7V

0

ERROR DRIFT (LSB)

–0.04

NORMALIZED TOTAL UNADJUSTED

–0.08

084

VDD = +5.5V

168 252 336 420 504

TEMPERATURE (°C)

Figure 32. Normalized TUE Drift Accelerated by Burn-In Hours

of Operation @ 150°C

01114-031

01114-032

3.8

3.2

SUPPLY CURRENT (mA)

2.6

2.0

IDD AND I

–55 125–35

–15 5 25 45 65 85 105

TEMPERATURE (°C)

Figure 30. Supply Current vs. Temperature

SS

01114-030

Rev. C | Page 13 of 20

AD7304/AD7305

CIRCUIT OPERATION

The AD7304/AD7305 are 4-channel, 8-bit, voltage output
DACs, differing primarily in digital logic interface and number
of reference inputs. Both parts share the same internal DAC
design and true rail-to-rail output buffers. The AD7304 contains
four independent multiplying reference inputs, while the
AD7305 has one common reference input. The AD7304 uses a
3-wire SPI-compatible serial data interface, while the AD7305
offers an 8-bit parallel data interface.

DAC SECTION

Each part contains four voltage-switched R-2R ladder DACs.
Figure 33 shows a typical equivalent DAC. These DACs are
designed to operate both single-supply or dual-supply,
depending on whether the user supplies a negative voltage on

pin. In a single-supply application, the VSS is tied to

the V

SS

ground. In either mode, the DAC output voltage is determined
by the V
the corresponding DAC register according to Equation 1.

Note that the output full-scale polarity is the same as the V
polarity for dc reference voltages.

input voltage and the digital data (D) loaded into

REF

= V

V

OUT

D/256 (1)

REF

V

DD

V

REF

Figure 33. Typical Equivalent DAC Channel

DB7

DB6

DB0

2R

R

V

2R

2R

SS

2R

V

OUT

01114-033

REF

These DACs are also designed to accommodate ac reference
input signals. As long as the ac signals are maintained between

< V

V

SS

< VDD, the user can expect 50 kHz of full power,

REF

multiplying bandwidth performance. In order to use negative
input reference voltages, the V

pin must be biased with a

SS

negative voltage of equal or greater magnitude than the
reference voltage.

The reference inputs are code dependent, exhibiting worst-case
minimum resistance values specified in the parametric specifi­cation table. The DAC outputs V

OUT

OUT

C, and V

OUT

OUT

D

A, V

B, V
are each capable of driving 2 kΩ loads in parallel with up to 500 pF
loads. Output sink current and source current are shown in
Figure 10 and Figure 11, respectively. The output slew rate is
nominally 3.6 V/µs while operating from ±5 V supplies. The
low output impedance of the buffers minimizes crosstalk
between analog input channels. At 100 kHz, 65 dB of channel­to-channel isolation exists (Figure 26). Output voltage noise is
plotted in Figure 23. In order to maintain good analog perform­ance, power supply bypassing of 0.01 µF in parallel with 1 µF is
recommended. The true rail-to-rail capability of the AD7304/AD7305
allows the user to connect the reference inputs directly to the
same supply as the V

or VSS pin (Figure 34). Under these

DD

conditions, clean power supply voltages (low ripple, avoid
switching supplies) appropriate for the application should be
used.

V

DD

Q1

V

X

120kΩ

Q2

V

SS

Figure 34. Equivalent DAC Amplifier Output Circuit

OUT

01114-034

Rev. C | Page 14 of 20

AD7304/AD7305

AD7304 SERIAL DATA INTERFACE

The AD7304 uses a 3-wire (CS, SDI, CLK) SPI-compatible
serial data interface. New serial data is clocked into the serial
input register in a 12-bit data-word format. MSB bits are loaded
first.

Table 5 defines the 12 data-word bits. Data is placed on the
SDI/SHDN pin and clocked into the register on the positive
clock edge of CLK subject to the data setup and data hold time
requirements specified in the Timing Specifications section.
Data can only be clocked in while the
active low. Only the last 12-bits clocked into the serial register
are interrogated when the

CS

pin returns to the logic high state,
extra data bits are ignored. Since most microcontrollers output
serial data in 8-bit bytes, two right-justified data bytes can be
written to the AD7304. Keeping the
first and second byte transfer results in a successful serial
register update.

Once the data is properly aligned in the shift register, the
positive edge of the

CS

initiates either the transfer of new data
to the target DAC register, determined by the decoding of
Address Bits A1 and A0, or the shutdown features is activated
based on the SAC or SDC bits. When either SAC or SDC pins
are set (Logic 0), the loading of new data determined by Bits B9
to B0 are still loaded, but the results do not appear on the buffer
outputs until the device is brought out of the shutdown state.
The selected DAC output voltages become high impedance with
a nominal resistance of 120 kΩ to ground, see Figure 34. If
both the SAC and SDC pins are set, all channels are still placed
in shutdown mode. When the AD7304 has been programmed
into the power shutdown state, the present DAC register data is
maintained as long as V

remains greater than 2.7 V. The

DD

remaining characteristics of the software serial interface are
defined by Table 4, Table 5, and Figure 5.

CLR

Two additional pins,

and
hardware control over the clear function and the DAC register
loading. If these functions are not needed, the
tied to logic high, and the
The asynchronous input

LDAC

CLR

pin forces all input and DAC
registers to the zero-code state. The asynchronous
can be strobed to active low when all DAC registers need to be
updated simultaneously from their respective input registers.

LDAC

The

pin places the DAC register in a transparent mode

while in the logic low state.

CS

chip select pin is

CS

line low between the

LDAC

, on the AD7304 provide

CLR

pin can be

pin can be tied to logic low.

LDAC

pin

V

CLK

SDI

A

V

B

C

REF

INPUT

INPUT

INPUT

INPUT

ON

V

REF

AD7304

R

REGISTER

R

R

REGISTER

R

LDAC

DAC A

REGISTER

DAC B

DAC C

REGISTER

DAC D

REF

CS

EN

D0
D1
D2
D3

8
D4
D5
D6
D7

2:4

A0

DECODE

A1

SDC
SAC

640kΩ 680kΩ

80kΩ

320kΩ

280kΩ

GND

DAC A

V

DD

B
C
D

REGISTER

DQ

REGISTER

DQ

REGISTER

DQ

REGISTER

DQ

POWER-

RESET

V

V

D

DD

REF

DAC A

R

DAC B

R

DAC C

R

DAC D

R

CLR

V

OUT

OE

V

OE

OUT

V

OE

OUT

V

OE

OUT

V

SS

Figure 35. AD7304 Equivalent Logic Interface

AD7304 HARDWARE SHUTDOWN SHDN

If a three-state driver is used on the SDI/SHDN pin, the
AD7304 can be placed into a power shutdown mode when the
SDI/ SHDN pin is placed in a high impedance state. For proper
operation, no other termination voltages should be present on
this pin. An internal window comparator detects when the logic
voltage on the SHDN pin is between 28% and 36% of V

DD

. A
high impedance internal bias generator provides this voltage on
the SHDN pin. The four DAC output voltages become high
impedance with a nominal resistance of 120 kΩ to ground (see
Figure 34 for an equivalent circuit).

AD7304/AD7305 POWER-ON RESET

When the VDD power supply is turned on, an internal reset
strobe forces all the input and DAC registers to the zero-code
state. The V

power supply should have a monotonically

DD

increasing ramp in order to have consistent results, especially in
the region of V

= 1.5 V to 2.3 V. The VSS supply has no effect

DD

on the power-on reset performance. The DAC register data
stays at zero until a valid serial register software load takes
place. In the case of the double-buffered AD7305, the output
DAC register can only be changed once the

LDAC

strobe is

initiated.

POWER-UP SEQUENCE

It is recommended to power VDD/VSS first before applying any
voltage to the reference terminals to avoid potential latch up.
The ideal power-up sequence is in the following order: GND,

, VSS, Digital Inputs, and V

V

DD

digital inputs and reference inputs is not important as long as
they are powered after V

DD/VSS

. The order of powering

REFx

.

A

B

C

D

01114-035

Rev. C | Page 15 of 20

AD7304/AD7305

L

AD7305 PARALLEL DATA INTERFACE

The AD7305 has an 8-bit parallel interface DB7 = MSB, DB0 =
LSB. Two address bits, A1 and A0, are decoded when an active

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

POWER-

ON

RESET

WR

pin, see Table 6. The WR

V

V

REF

DD

AD7305

DAC A

REGISTER

R

DAC B

REGISTER

R

DAC C

REGISTER

R

DAC D

REGISTER

R

DAC A

OE

R

DAC B

OE

R

DAC C

OE

R

DAC D

OE

R

V

OUT

V

OUT

V

OUT

V

OUT

low write strobe is placed on the
is a level-sensitive input pin, therefore, the data setup and data
hold times defined in the Timing Specifications section need to
be adhered to.

DATA

DB0–DB7

WR

A0/SHDN

A1

8

2:4
DECODE

640k

Ω

80kΩ

280k

Ω

DAC A

V

DD

680k

320k

B
C
D

Ω

Ω

LDAC

is tied to Logic Low, the DAC registers become
transparent and the input register data determines the DAC
output voltage (see Figure 36 for an equivalent interface logic
diagram).

AD7226 PIN COMPATIBILITY

By tying the
configuration and functionality as the AD7226, with the
exception of a lower power supply operating voltage.

LDAC

pin to ground, the AD7305 has the same pin

AD7305 HARDWARE SHUTDOWN SHDN

A

B

C

D

If a three-state driver is used on the A0/SHDN pin, the AD7305
can be placed into a power shutdown mode when the A0/SHDN
pin is placed in a high impedance state. For proper operation,
no other termination voltages should be present on this pin. An
internal window comparator detects when the logic voltage on
the SHDN pin is between 28% and 36% of V

. A high imped-

DD

ance, internal-bias generator provides this voltage on the SHDN
pin. The four DAC output voltages become high impedance
with a nominal resistance of 120 kΩ to ground.

ESD PROTECTION CIRCUITS

All logic input pins contain back-biased ESD protection Zeners
connected to ground (GND). The V
biased ESD protection Zener connected to V

pins also contain a back-

REF

(see Figure 37).

DD

GND

LDAC

V

SS

Figure 36. AD7305 Equivalent Logic Interface

LDAC

The

pin provides the capability of simultaneously
updating all DAC registers with new data from the input
registers at the same time. This results in the analog outputs all
changing to their new values at the same time. The

LDAC

pin is
a level-sensitive input. If the simultaneous update feature is not
required, the

LDAC

pin can be tied to logic low. When the

01114-036

DIGITA
INPUTS

V

DD

V

X

REF

GND

Figure 37. Equivalent ESD Protection Circuits

01114-037

Rev. C | Page 16 of 20

AD7304/AD7305

APPLICATIONS

The AD7304/AD7305 are inherently 2-quadrant multiplying
DACs. That is, they can easily be set up for unipolar output
operation. The full-scale output polarity is the same as the
reference input voltage polarity.

In some applications, it may be necessary to generate the full
4-quadrant multiplying capability or a bipolar output swing.
This is easily accomplished using an external true rail-to-rail op
amp, such as the OP295. Connecting the external amplifier with
two equal value resistors, as shown in Figure 38, results in a full
4-quadrant multiplying circuit. In this circuit, the amplifier
provides a gain of two, which increases the output span
magnitude to 10 V. The transfer equation of this circuit shows
that both negative and positive output voltages are created as

the input data (D) is incremented from code zero (V
to midscale (V

V ×

=

+5V

REF

Figure 38. 4-Quadrant Multiplying Application Circuit

= 0 V) to full scale (V

OUT

D

−

1128

10kΩ 10kΩ

AD7304

(2)

V

REFOUT

2.2pF

OUT

–5V < V

= +5 V).

< +5V

OUT

= –5 V)

OUT

01114-038

Rev. C | Page 17 of 20

AD7304/AD7305

OUTLINE DIMENSIONS

10.50 (0.4134)

10.10 (0.3976)

16

1

1.27 (0.0500)
BSC

0.30 (0.0118)

0.10 (0.0039)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

0.51 (0.0201)

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-013AA

Figure 39. 16-Lead Standard Small Outline Package [SOIC]

Dimensions shown in millimeters and (inches)

9

7.60 (0.2992)

7.40 (0.2913)

10.65 (0.4193)

8

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

0.33 (0.0130)

0.20 (0.0079)

Wide Body (R-16)

8°
0°

0.75 (0.0295)

0.25 (0.0098)

1.27 (0.0500)

0.40 (0.0157)

× 45°

5.10

5.00

4.90

16

4.50

4.40

4.30

PIN 1

0.15

0.05

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153AB

0.10

0.30

0.19

9

6.40

BSC

81

1.20
MAX

SEATING
PLANE

0.20

0.09
8°

0°

0.75

0.60

0.45

Figure 41. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

13.00 (0.5118)

12.60 (0.4961)

20 11

1

0.30 (0.0118)

0.10 (0.0039)

1.27

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MS-013AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

(0.0500)

BSC

0.51 (0.0201)

0.31 (0.0122)

7.60 (0.2992)

7.40 (0.2913)

10

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

10.65 (0.4193)

10.00 (0.3937)

0.33 (0.0130)

0.20 (0.0079)

Figure 40. 20-Lead Standard Small Outline Package [SOIC]

Wide Body (R-20)

Dimensions shown in millimeters and (inches)

0.75 (0.0295)

0.25 (0.0098)

8°
0°

× 45°

1.27 (0.0500)

0.40 (0.0157)

6.60

6.50

6.40

PIN 1

0.15

0.05

COPLANARITY

0.10

20

1

0.65

BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153AC

1.20 MAX

11

10

SEATING
PLANE

4.50

4.40

4.30

6.40 BSC

0.20

0.09
8°

0°

0.75

0.60

0.45

Figure 42. 20-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-20)

Dimensions shown in millimeters

Rev. C | Page 18 of 20

AD7304/AD7305

ORDERING GUIDE

Model Temperature Range Package Description Package Options

AD7304BR –40°C to +85°C 16-Lead SOIC R-16
AD7304BR-REEL –40°C to +85°C 16-Lead SOIC R-16
AD7304BRZ
AD7304BRZ-REEL1 –40°C to +85°C 16-Lead SOIC R-16
AD7304YR –40°C to +125°C 16-Lead SOIC R-16
AD7304YRZ1 –40°C to +125°C 16-Lead SOIC R-16
AD7304BRU –40°C to +85°C 16-Lead TSSOP RU-16
AD7304BRU-REEL7 –40°C to +85°C 16-Lead TSSOP RU-16
AD7305BR –40°C to +85°C 20-Lead SOIC R-20
AD7305BR-REEL –40°C to +85°C 20-Lead SOIC R-20
AD7305YR –40°C to +125°C 20-Lead SOIC R-20
AD7305YR-REEL –40°C to +125°C 20-Lead SOIC R-20
AD7305BRU –40°C to +85°C 20-Lead TSSOP RU-20
AD7305BRU-REEL7 –40°C to +85°C 20-Lead TSSOP RU-20
AD7305BRUZ1 –40°C to +85°C 20-Lead TSSOP RU-20
AD7305BRUZ-REEL71 –40°C to +85°C 20-Lead TSSOP RU-20

1

Z = Pb-free part.

1

–40°C to +85°C 16-Lead SOIC R-16

Rev. C | Page 19 of 20

AD7304/AD7305

NOTES

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
Printed in the U.S.A.

C01114-0-11/04(C)

Rev. C | Page 20 of 20