ANALOG DEVICES AD7294 Service Manual

12-Bit Monitor and Control System with Multichannel

ADC, DACs, Temperature Sensor, and Current Sense

FEATURES

12-bit SAR ADC with 3 μs conversion time

4 uncommitted analog inputs

Differential/single-ended
V

, 2 × V

REF

2 high-side current sense inputs

5 V to 59.4 V operating range

0.5% max gain error
±200 mV input range

2 external diode temperature sensor inputs

−55°C to +150°C measurement range
±2°C accuracy
Series resistance cancellation

1 internal temperature sensor

±2°C accuracy

Built-in monitoring features

Minimum/maximum recorder for each channel
Programmable alert thresholds
Programmable hysteresis

Four 12-bit monotonic 15 V DACs

5 V span, 0 V to 10 V offset
8 μs settling time
10 mA sink and source capability

Power-on resets (POR) to 0 V
Internal 2.5 V reference
2-wire fast mode I
Temperature range: −40°C to +105°C
Package type: 64-lead TQFP

input ranges

REF

2

C interface

AD7294

APPLICATIONS

Cellular base stations

GSM, EDGE, UMTS, CDMA, TD-SCDMA, W-CDMA, WiMAX
Point-to-multipoint and other RF transmission systems
12 V, 24 V, 48 V automotive applications
Industrial controls

GENERAL DESCRIPTION

The AD7294 contains all the functions required for general­purpose monitoring and control of current, voltage, and
temperature integrated into a single-chip solution. The part
includes low voltage (±200 mV) analog input sense amplifiers
for current monitoring across shunt resistors, temperature sense
inputs, and four uncommitted analog input channels multiplexed
into a SAR analog-to-digital converter (ADC) with a 3 s conver­sion time. A high accuracy internal reference is provided to drive
both the digital-to-analog converter (DAC) and ADC. Four 12-bit
DACs provide the outputs for voltage control. The AD7294 also
includes limit registers for alarm functions. The part is designed
on Analog Devices, Inc., high voltage DMOS process for high
voltage compliance, 59.4 V on the current sense inputs, and up
to a 15 V DAC output voltage.

The AD7294 is a highly integrated solution that offers all the
functionality necessary for precise control of the power amplifier
in cellular base station applications. In these types of applications,
the DACs provide 12-bit resolution to control the bias currents
of the power transistors. Thermal diode-based temperature sensors
are incorporated to compensate for temperature effects. The ADC
monitors the high-side current and temperature. All this func­tionality is provided in a 64-lead TQFP operating over a
temperature range of −40°C to +105°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

AD7294

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications ..................................................................................... 4

DAC Specifications....................................................................... 4

ADC Specifications ...................................................................... 5

General Specifications ................................................................. 7

Timing Characteristics ................................................................ 8

Absolute Maximum Ratings ............................................................ 9

Thermal Resistance ...................................................................... 9

ESD Caution .................................................................................. 9

Pin Configuration and Function Descriptions ........................... 10

Typical Performance Characteristics ........................................... 12

Terminology .................................................................................... 17

DAC Terminology ...................................................................... 17

ADC Terminology ...................................................................... 17

Theory of Operation ...................................................................... 18

ADC Overview ........................................................................... 18

ADC Transfer Functions ........................................................... 18

Analog Inputs .............................................................................. 18

Current Sensor ............................................................................ 20

Analog Comparator Loop ......................................................... 21

Temperature Sensor ................................................................... 22

DAC Operation ........................................................................... 23

ADC and DAC Reference .......................................................... 24

V

Feature .............................................................................. 24

DRIVE

Register Setting ............................................................................... 25

Address Pointer Register ........................................................... 25

Command Register (0x00) ........................................................ 26

Result Register (0x01) ................................................................ 26

T

1, T

2 Result Registers (0x02 and 0x03) ....................... 27

SENSE

INT Result Register (0x04).............................................. 27

T

SENSE

SENSE

DACA, DACB, DACC, DACD, Register (0x01 to 0x04) .............. 28

Alert Status Register A (0x05), Register B (0x06), and

Register C (0x07) ........................................................................ 28

Channel Sequence Register (0x08) .......................................... 28

Configuration Register (0x09) .................................................. 29

Power-Down Register (0x0A) ................................................... 30

DATA
(V

/DATA

HIGH

1); 0x11, 0x12 (VIN2); 0x14, 0x15 (VIN3) .............................. 30

IN

Registers: 0x0B, 0x0C (VIN0); 0x0E, 0x0F

LOW

Hysteresis Registers: 0x0D (VIN0), 0x10 (VIN1), 0x13 (VIN2),
0x16 (V

T

SENSE

3) .................................................................................. 30 

IN

Offset Registers (0x26 and 0x27) ................................... 31

I2C Interface .................................................................................... 32

General I2C Timing .................................................................... 32

Serial Bus Address Byte ............................................................. 33

Interface Protocol ....................................................................... 33

Modes of Operation ....................................................................... 37

Command Mode ........................................................................ 37

Autocycle Mode .......................................................................... 38

Alerts and Limits Theory .............................................................. 39

Alert_Flag Bit .............................................................................. 39

Alert Status Registers ................................................................. 39

Data

and Data

HIGH

Monitoring Features ............................ 39

LOW

Hysteresis ..................................................................................... 40

Applications Information .............................................................. 41

Base Station Power Amplifier Monitor and Control ............. 41

Gain Control of Power Amplifier............................................. 42

Layout and Configuration ............................................................. 43

Power Supply Bypassing and Grounding ................................ 43

Outline Dimensions ....................................................................... 44

Ordering Guide .......................................................................... 44



REVISION HISTORY

1/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 44

AD7294

FUNCTIONAL BLOCK DIAGRAM

R

SENSE

OVERRANGE

OVERRANGE

T1 T2

I

SENSE

I

SENSE

VIN0
V

IN

V

IN

V

IN

D1+
D2+

D2–

D1–

1
2
3

VPP(1 TO 2)

2

1

AD7294

DV

V

10.41

DD

RS1(+) RS2(+) RS2(–)RS1(–)

HIGH SIDE
CURRENT

SENSE

REF

DGND

(1 TO 2)

HIGH SIDE

CURRENT

SENSE

CONTROL L OGIC

I2C INTERFACE

PROTOCOL

SDA

MUX

AS1AS2SCL

Figure 1.

REF

REF

IN

12-BIT

ADC

REGIS TERS

TEMP

SENSOR

DCAP

AS0

TO LOAD

OUT

ADC

LIMIT

/

2.5V
REF

ALERT/

BUSY

REF

REF

IN

OUT

DAC

AV

/

DD

(1 TO 6)

12-BIT

DAC

100kΩ 200kΩ

12-BIT

DAC

100kΩ 200kΩ

12-BIT

DAC

100kΩ 200kΩ

12-BIT

DAC

100kΩ 200kΩ

AGND

(1 TO 7)

100kΩ 200kΩ

100kΩ 200kΩ

100kΩ 200kΩ

100kΩ 200kΩ

DAC OUT
V+ AB/CD

V

A

OUT

OFFSET IN A

V

B

OUT

OFFSET IN B

V

C

OUT

OFFSET IN C

V

D

OUT

OFFSET IN D

5747-001

Rev. 0 | Page 3 of 44

AD7294

SPECIFICATIONS

DAC SPECIFICATIONS

AVDD = DVDD = 4.5 V to 5.5 V, AGND = DGND = 0 V, internal 2.5 V reference; V
otherwise noted. DAC OUTV+ AB and DAC OUTV+ CD = 4.5 V to 16.5 V, OFFSET IN x is floating, therefore, the DAC output
span = 0 V to 5 V.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

ACCURACY

Resolution 12 Bits
Relative Accuracy (INL) ±1 ±3 LSB
Differential Nonlinearity (DNL) ±0.3 ±1 LSB Guaranteed monotonic
Zero-Scale Error 2.5 8 mV

1

Full-Scale Error of DAC and

15.5

mV DAC OUTV+ = 5.0 V

Output Amplifier
Full-Scale Error of DAC 2 mV DAC OUTV+ = 15.0 V
Offset Error ±8.575 mV Measured in the linear region, TA = −40°C to +105°C
±2 mV Measured in the linear region, TA = 25°C
Offset Error Temperature

±5 ppm/°C

Coefficient
Gain Error ±0.025 ±0.155 % FSR
Gain Temperature Coefficient ±5 ppm/°C

DAC OUTPUT CHARACTERISTICS

Output Voltage Span 0 2 × V

V 0 V to 5 V for a 2.5 V reference

REF

Output Voltage Offset 0 10 V

Offset Input pin range 0 5 V

1.667 5 V
DC Input Impedance
Output Voltage Settling Time

Slew Rate

2

1.1 V/µs

Short-Circuit Current
Load Current
Capacitive Load Stability
DC Output Impedance

2

75 kΩ 100 kΩ to V

2

8 µs

2

2

40 mA Full-scale current shorted to ground

±10 mA Source and/or sink within 200 mV of supply

2

10 nF R

2

1 Ω

REFERENCE

Reference Output Voltage 2.49 2.5 2.51 V ±0.4% maximum @ 25°C, AVDD = DVDD = 4.5 V to 5.5 V
Reference Input Voltage Range 0 AVDD − 2 V
Input Current 100 125 µA V
Input Capacitance
V

Output Impedance

REF

Reference Temperature

2

20 pF

2

25 Ω

10 25 ppm/°C

Coefficient

1

This value indicates that the DAC output amplifiers can output voltages 15.5 mV below the DAC OUTV+ supply. If higher DAC OUTV+ supply voltages are used, the

full-scale error of the DAC is typically 2 mV with no load.

2

Samples are tested during initial release to ensure compliance; they are not subject to production testing.

= 2.7 V to 5.5 V; TA =−40°C to +105°C, unless

DRIVE

The output voltage span can be positioned in the 0 V to
15 V range; if the OFFSET IN x is left floating, the offset
pin = 2/3 × V

= 3 V

OUT

= OFFSET IN x, DAC HIGH-Z = V

OUT

, giving an output of 0 V to 2 × V

REF

− 2 × V

OFFSET

, and 200 kΩ to AGND, see Figure 47

REF

REF

+ V

, DAC HIGH-Z = 0 V

DAC

DRIVE

REF

1/4 to 3/4 change within 1/2 LSB, measured from last
SCL edge

= ∞

L

= 2.5 V

REF

Rev. 0 | Page 4 of 44

AD7294

ADC SPECIFICATIONS

AVDD = DVDD = 4.5 V to 5.5 V, AGND = DGND = 0 V, V

T

= −40°C to +105°C, unless otherwise noted.

A

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

DC ACCURACY

Resolution 12 Bits
Integral Nonlinearity (INL)

1

±0.5 ±1 LSB Differential mode

±0.5 ±1.5 LSB Single-ended or pseudo differential mode
Differential Nonlinearity (DNL)1 ±0.5 ±0.99 LSB

Single-Ended Mode

Offset Error ±1 ±7 LSB
Offset Error Match ±0.4 LSB
Gain Error ±0.5 ±2.5 LSB
Gain Error Match ±0.4 LSB

Differential Mode

Positive Gain Error ±3 LSB
Positive Gain Error Match ±0.5 LSB
Zero Code Error ±3 ±10 LSB
Zero Code Error Match ±0.5 LSB
Negative Gain Error ±3 LSB
Negative Gain Error Match ±0.5 LSB

CONVERSION RATE

Conversion Time
Autocycle Update Rate

2

3 s

2

50 s

Throughput Rate 22.22 kSPS f

ANALOG INPUT

Single-Ended Input Range 0

3

0 2 × V
Pseudo Differential Input Range: V

4

− V

IN−

0

IN+

0 2 × V
Fully Differential Input Range: V

IN+

− V

−V

IN−

REF

−2 × V
Input Capacitance

2

30 pF

DC Input Leakage Current ±1 µA

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio (SNR)

1

72.5 73 dB f

71 72 dB

Signal-to-Noise + Distortion (SINAD) Ratio

1

69 71.5 dB f

71 72.5 dB

Total Harmonic Distortion (THD)

1

−81 –74 dB f

−79 –72 dB

Spurious-Free Dynamic Range (SFDR)

1

−91 −84.5 dB f

−93 −85.5

Channel-to-Channel Isolation

2

−90 dB f

= 2.5 V internal or external; V

REF

V

V

+V

+2 × V

REF

REF

V 0 V to 2 × V

REF

REF

0 V to 2 × V

REF

0 V to V

REF

0 V to 2 × V

REF

DRIVE

Differential, single-ended, and pseudo differential
modes

= 400 kHz

SCL

V 0 V to V

0 V to V

= 10 kHz sine wave; differential mode

IN

= 10 kHz sine wave; single-ended and pseudo

f

IN

differential modes

= 10 kHz sine wave; differential mode

IN

= 10 kHz sine wave; single-ended and pseudo

f

IN

differential modes

= 10 kHz sine wave; differential mode

IN

= 10 kHz sine wave; single-ended and pseudo

f

IN

differential modes

= 10 kHz sine wave; differential mode

IN

= 10 kHz sine wave; single-ended and pseudo

f

IN

differential modes

= 10 kHz to 40 kHz

IN

= 2.7 V to 5.5 V; VPP = AVDD to 59.4 V;

mode

REF

mode

REF

mode

REF

mode

REF

mode

REF

mode

REF

Rev. 0 | Page 5 of 44

AD7294

Parameter Min Typ Max Unit Test Conditions/Comments

TEMPERATURE SENSOR—INTERNAL

Operating Range −40 +105 °C
Accuracy ±2 °C Internal temperature sensor, TA = −30°C to +90°C
±2.5 °C Internal temperature sensor, TA = −40°C to +105°C
Resolution 0.25 °C LSB size
Update Rate 5 ms

TEMPERATURE SENSOR—EXTERNAL External transistor is 2N3906

Operating Range −55 +150 °C Limited by external diode
Accuracy ±2 °C TA = T
Resolution 0.25 °C LSB size
Low Level Output Current Source
Medium Level Output Current Source
High Level Output Current Source
Maximum Series Resistance (RS) for

External Diode
Maximum Parallel Capacitance (CP) for

External Diode

2

2

2

8 µA

2

32 µA

2

128 µA

100 Ω For < ±0.5°C additional error, C

1 nF RS = 0, see Figure 29

CURRENT SENSE VPP = AVDD to 59.4 V

VPP Supply Range AVDD 59.4 V
Gain 12.4375 12.5 12.5625

Gain of 12.5 gives a gain error = 0.5% maximum;

delivers ±200 mV range with +2.5 V reference
RS(+)/RS(−) Input Bias Current 25 32 µA
CMRR/PSRR

2

80 dB Inputs shorted to V

Offset Error ±50 ±340 µV
Offset Drift 1 µV/°C
Amplifier Peak-To-Peak Noise

2

400 µV Referred to input

VPP Supply Current 0.18 0.22 mA VPP = 59.4 V

REFERENCE

Reference Output Voltage 2.49 2.51 V ±0.2% maximum at 25°C only
Reference Input Voltage Range 0.1 4.1 V For four uncommitted ADCs
1 AVDD − 2 For current sense
DC Leakage Current ±2 A
V

Output Impedance

REF

Input Capacitance

2

25 Ω

2

20 pF

Reference Temperature Coefficient 10 25 ppm/°C

1

See the section for more details. Terminolo gy

2

Sampled during initial release to ensure compliance, not subject to production testing.

3

V

or V

must remain within GND/VDD.

IN+

IN−

4

V

= 0 V for specified performance. For full input range on V

IN−

, see . Figure 39

IN−

= −40°C to +105°C

DIODE

= 0, see Figure 30

P

PP

Rev. 0 | Page 6 of 44

AD7294

GENERAL SPECIFICATIONS

AVDD = DVDD = 4.5 V to 5.5 V, AGND = DGND = 0 V, V
DAC OUTV+ AB and DAC OUTV+ CD = 4.5 V to 16.5 V; OFFSET IN x is floating, therefore, DAC output span = 0 V to 5 V; T

−40°C to +105°C, unless otherwise noted.

Table 3.

Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS

Input High Voltage, VIH 0.7 V

DRIVE

Input Low Voltage, VIL 0.3 V
Input Leakage Current, IIN ±1 µA
Input Hysteresis, V

0.05 V

HYST

Input Capacitance, CIN 8 pF
Glitch Rejection 50 ns

I2C® Address Pins Maximum External

30 pF Tristate input

Capacitance if Floating
DAC HIGH-Z Pin Leakage 10 µA Input with pull-down resistor, VIN = 5.5 V
1 µA Input with pull-down resistor, VIN = 0 V

LOGIC OUTPUTS

SDA, ALERT SDA and ALERT/BUSY are open-drain outputs

Output Low Voltage, VOL 0.4 V I

0.6 V I

Floating-State Leakage Current ±1 µA

Floating-State Output Capacitance 8 pF

I

OVERRANGE I

SENSE

Output High Voltage, VOH V
Output Low Voltage, VOL 0.2 V I
Overrange Setpoint VFS V

POWER REQUIREMENTS

VPP AVDD 59.4 V
AVDD 4.5 5.5 V
V(+) 4.5 16.5 V
DVDD 4.5 5.5 V Tie DVDD to AVDD
V

2.7 5.5 V

DRIVE

IDD Dynamic 5.3 6.5 mA AVDD + DVDD + V
DAC OUTV+ x, IDD 0.6 0.9 mA

Power Dissipation 70 92 mW
Power-Down

IDD 0.5 1 µA For each AVDD and V

DIDD 1 16.5 µA

DAC OUTV+ x, IDD 35 60 µA

Power Dissipation 2.5 mW

= 2.5 V internal or external; V

REF

= 2.7 V to 5.5 V; VPP = AVDD to 59.4 V;

DRIVE

V SDA, SCL only

V SDA, SCL only

DRIVE

V

DRIVE

Input filtering suppresses noise spikes of less
than 50 ns

= 3 mA

SINK

= 6 mA

SINK

OVERRANGE is a push-pull output

SENSE

− 0.2 V I

DRIVE

× 1.2 mV VFS = ±V

FS

= 200 µA for push-pull outputs

SOURCE

= 200 µA for push-pull outputs

SINK

@ midscale output voltage, DAC outputs
unloaded

ADC/12.5

REF

, DAC outputs unloaded

DRIVE

DRIVE

=

A

Rev. 0 | Page 7 of 44

AD7294

T

TIMING CHARACTERISTICS

I2C Serial Interface

AVDD = DVDD = 4.5 V to 5.5 V, AGND = DGND = 0 V, V
DAC OUTV+ AB and DAC OUTV+ CD = 4.5 V to 16.5 V; OFFSET IN x is floating, therefore, DAC output span = 0 V to 5 V; T

−40°C to +105°C, unless otherwise noted.

= 2.5 V internal or external; V

REF

= 2.7 V to 5.5 V; VPP = AVDD to 59.4 V;

DRIVE

=

A

Table 4.

1

Parameter

f

400 kHz max SCL clock frequency

SCL

Limit at T

, T

Unit Description

MIN

MAX

t1 2.5 µs min SCL cycle time
t2 0.6 µs min t
t3 1.3 µs min t
t4 0.6 µs min t
t5 100 ns min t

2

t

0.9 µs max t

6

0 µs min t
t7 0.6 µs min t
t8 0.6 µs min t
t9 1.3 µs min t

, SCL high time

HIGH

, SCL low time

LOW

, start/repeated start condition hold time

HD,STA

, data setup time

SU,DAT

, data hold time

HD,DAT

, data hold time

HD,DAT

, setup time for repeated start

SU,STA

, stop condition setup time

SU,STO

, bus free time between a stop and a start condition

BUF

t10 300 ns max tR, rise time of SCL and SDA when receiving
0 ns min tR, rise time of SCL and SDA when receiving (CMOS compatible)
t11 300 ns max tF, fall time of SDA when transmitting
0 ns min tF, fall time of SDA when receiving (CMOS compatible)
300 ns max tF, fall time of SCL and SDA when receiving
20 + 0.1C

3

ns min t

b

, fall time of SCL and SDA when transmitting

F

Cb 400 pF max Capacitive load for each bus line

1

See Figure 2.

2

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V

edge of SCL.

3

Cb is the total capacitance in pF of one bus line. tR and tF are measured between 0.3 DVDD and 0.7 DVDD.

minimum of the SCL signal) to bridge the undefined region of the falling

IH

Timing and Circuit Diagrams

SDA

SCL

t

9

t

4

START

CONDITION

t

3

t

10

t

6

O OUTPUT PIN

Figure 2. I

t

2

C-Compatible Serial Interface Timing Diagram

t

11

2

t

C

L

50pF

5

200µA

200µA

I

OL

I

OH

REPEATED

CONDITION

V

OH

V

OL

t

7

START

(MIN) OR

(MAX)

t

4

t

1

05747-003

t

8

STOP

CONDITIO N

05747-002

Figure 3. Load Circuit for Digital Output

Rev. 0 | Page 8 of 44

AD7294

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.1

Table 5.

Parameter Rating

VPPx to AGND −0.3 V to +70 V
AVDDx to AGND −0.3 V to +7 V
DAC OUTV+ AB to AGND −0.3 V to +17 V
DAC OUTV+ CD to AGND −0.3 V to +17 V
DVDD to DGND −0.3 V to +7 V
V

to OPGND −0.3 V to +7 V

DRIVE

Digital Inputs to OPGND −0.3 V to V

DRIVE

+ 0.3 V
SDA/SCL to OPGND −0.3 V to +7 V
Digital Outputs to OPGND −0.3 V to V

DRIVE

+ 0.3 V
RS(+)/RS(−) to VPPx VPP − 0.3 V to VPP + 0.3 V
REF

/REFIN ADC to AGND −0.3 V to AVDD + 0.3 V

OUT

REF

/REFIN DAC to AGND −0.3 V to AVDD + 0.3 V

OUT

OPGND to AGND −0.3 V to +0.3 V
OPGND to DGND −0.3 V to +0.3 V
AGND to DGND −0.3 V to +0.3 V
V

x to AGND −0.3 V to DAC OUTV(+) + 0.3 V

OUT

Analog Inputs to AGND −0.3 V to AVDD + 0.3 V
Operating Temperature Range

B Version −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ Max) 150°C
ESD Human Body Model 1 kV
Reflow Soldering Peak

230°C

Temperature

1

Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

To conform with IPC 2221 industrial standards, it is advisable
to use conformal coating on the high voltage pins.

THERMAL RESISTANCE

Table 6. Thermal Resistance

Package Type θJA θ

Unit

JC

64-Lead TQFP 54 16 °C/W

ESD CAUTION

Rev. 0 | Page 9 of 44

AD7294

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

C
D
A

N
I

F
E
R

/

T

6

7

)

RS2(–)

RS2(+)

AV

AGND1

AGND2

AV

AGND3

/REFIN DAC

OUT

AV

REF

NC = NO CONNECT

)
–

(

2

1

1

P

P

C

S

P

P

N

V

R

V

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1

NC

NC

DD

DD

D2–

D2+

D1+

D1–

DD

NC

1

2

3

PIN 1

2

INDICATO R

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

A

A

C

B

N

T

A

N

I

U

D

O

T

N

V

E

G

S
F

T

F

U

O

O
C

A
D

+

D

(

N

1

G

S

C

A

R

N

AD7294

TQFP

TOP VIEW

(Not to Scale)

B

B

B
A

T

N

I

U

+

O

T

V

V

E

T

S

U

F

O

F

C

O

A
D

6

D
D

V
A

4
D

N
G
A

Figure 4. Pin Configuration

U

5

D

P

O

D
D

V
A

4

D

D

V
A

0

N

A

F

N

G

C

E

I

A

V

D

R

C

D

D

C

C

T

C

N

U

I

+

D

O

T

V

N

V

E

T

G

S

U

F

T

O

F

U

C

O

O

A

C

D

A
D

1

2

3

N

N

N

I

I

I

V

V

V

48

DAC HIGH-Z

47

DGND

1 OVERRANGE

I

46

SENSE

2 OVERRANGE

I

45

SENSE

44

DV

DD

43

DGND

42

V

DRIVE

41

OPGND

40

SCL

39

SDA

38

AS0

37

AS1

36

AS2

35

ALERT/BUSY

34

AGND5

33

NC

D

C

D

N

T

N

I

U
O

T

V

E
S
F
F
O

05747-005

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

2, 61 RS2(−), RS1(−) Connection for External Shunt Resistor.
3, 60 RS2(+), RS1(+) Connection for External Shunt Resistor.
1, 4, 16, 17,

NC No Connection. Do not connect these pins.

32, 33, 59, 64

1 to AVDD6

5, 8, 14, 25,
56, 57

AV

DD

Analog Supply Pins. The operating range is 4.5 V to 5.5 V. These pins provide the supply voltage for
all the analog circuitry on the AD7294. Connect the AV
supply pins are at the same potential. This supply should be decoupled to AGND with one 10 µF
tantalum capacitor and a 0.1 µF ceramic capacitor for each AVDD pin.

6, 7, 13, 24,
34, 55, 58

AGND1 to AGND7

Analog Ground. Ground reference point for all analog circuitry on the AD7294. Refer all analog
input signals and any external reference signal to this AGND voltage. Connect all seven of these
AGND pins to the AGND plane of the system. Note that AGND5 is a DAC ground reference point and
should be used as a star ground for circuitry being driven by the DAC outputs. Ideally, the AGND
and DGND voltages should be at the same potential and must not be more than 0.3 V apart, even
on a transient basis.

9, 12 D2(−), D1(−)

Temperature Sensor Analog Input. These pins are connected to the external temperature sensing
transistor. See Figure 45 and Figure 46.

10, 11 D2(+), D1(+)

Temperature Sensor Analog Input. These pins are connected to the external temperature sensing
transistor. See Figure 45 and Figure 46.

15 REF

/REFIN DAC

OUT

DAC Reference Output/Input Pin. The REF
power-up, the default configuration of this pin is external reference (REF
reference by writing to the power-down register; see Tab le 27. Decoupling capacitors (220 nF
recommended) are connected to this pin to decouple the reference buffer. Provided the output is
buffered, the on-chip reference can be taken from this pin and applied externally to the rest of a
system. A maximum external reference voltage of AV
of the REF

/REFIN DAC pin.

OUT

and DVDD pins together to ensure that all

DD

/REFIN DAC pin is common to all four DAC channels. On

OUT

− 2 V can be supplied to the REF

DD

). Enable the internal

IN

portion

OUT

Rev. 0 | Page 10 of 44

AD7294

Pin No. Mnemonic Description

18, 23, 26, 31

19, 22, 27, 30 V

20, 29

21, 28

35 ALERT/BUSY

When configured as a busy output, this pin becomes active when a conversion is in progress.
38, 37, 36 AS0, AS1, AS2

39 SDA

40 SCL

41 OPGND Dedicated Ground Pin for I2C Interface.
42 V

43, 47 DGND Digital Ground. This pin is the ground for all digital circuitry.
44 DV

46, 45

48 DAC HIGH-Z

49, 50, 51, 52 VIN3 to VIN0

53 REF

54 DCAP

62, 63 VPP1, VPP2

OFFSET IN A to
OFFSET IN D

OUT

A to V

OUT

D

DAC OUT GND AB,
DAC OUT GND CD

DAC OUTV+ AB,
DAC OUTV+ CD

DRIVE

DD

1 OVERRANGE,

I

SENSE

2 OVERRANGE

I

SENSE

/REFIN ADC

OUT

DAC Analog Offset Input Pins. These pins set the desired output range for each DAC channel. The
DACs have an output voltage span of 5 V, which can be shifted from 0 V to 5 V to a maximum output
voltage of 10 V to 15 V by supplying an offset voltage to these pins. These pins can be left floating,
in which case decouple them to AGND with a 100 nF capacitor.

Buffered Analog DAC Outputs for Channel A to Channel D. Each DAC analog output is driven from
an output amplifier that can be offset using the OFFSET IN x pin. The DAC has a maximum output
voltage span of 5 V that can be level shifted to a maximum output voltage level of 15 V. Each output
is capable of sourcing and sinking 10 mA and driving a 10 nF load.

Analog Ground. Analog ground pins for the DAC output amplifiers on V
and V

D, respectively.

OUT

Analog Supply. Analog supply pins for the DAC output amplifiers on V
V

D, respectively. The operating range is 4.5 V to 16.5 V.

OUT

OUT

OUT

A and V

A and V

OUT

B, and V

OUT

B, and V

OUT

C

OUT

C and

Digital Output. Selectable as an alert or busy output function in the configuration register. This is an
open-drain output. An external pull-up resistor is required.

When configured as an alert, this pin acts as an out-of-range indicator and becomes active when
the conversion result violates the DATA

HIGH

or DATA

register values. See the Alert Status Registers

LOW

section.

2

Digital Logic Input. Together, the logic state of these inputs selects a unique I

C address for the

AD7294. See Tab le 34 for details.
Digital Input/Output. Serial bus bidirectional data. This open-drain output requires a pull-up

resistor.

2

C Bus Clock. The data transfer rate in I2C mode is compatible with both 100 kHz and 400 kHz

Serial I
operating modes. This open-drain output requires pull-up resistors.

Logic Power Supply. The voltage supplied at this pin determines at what voltage the interface
operates. Decouple this pin to DGND. The voltage range on this pin is 2.7 V to 5.5 V and may be
different to the voltage level at AV

and DVDD, but should never exceed either by more than 0.3 V.

DD

To set the input and output thresholds, connect this pin to the supply to which the I2C bus is pulled.

Logic Power Supply. The operating range is 4.5 V to 5.5 V. These pins provide the supply voltage for
all the digital circuitry on the AD7294. Connect the AV

and DVDD pins together to ensure that all

DD

supply pins are at the same potential. Decouple this supply to DGND with a10 µF tantalum
capacitor and a 0.1 µF ceramic capacitor.

Fault Comparator Outputs. These pins connect to the high-side current sense amplifiers.

High Impedance Control on DAC Outputs. When this pin is set to a high logic level, it sets the DAC
outputs to the voltage level on the OFFSET IN x pins. This pin has an internal 1 MΩ pull-down
resistor.

Uncommitted ADC Analog Inputs. These pins are programmable as four single-ended channels or
two true differential analog input channel pairs. See Table 1 and Table 13 for more details.

ADC Reference Input/Output Pin. The REF
ADC. Upon power-up, the default configuration of this pin is external reference (REF

/REFIN ADC pin provides the reference source for the

OUT

). Enable the

IN

internal reference by writing to the power-down register; see Table 27. Connect decoupling
capacitors (220 nF recommended) to this pin to decouple the reference buffer. Provided the output
is buffered, the on-chip reference can be taken from this pin and applied externally to the rest of a
system. A maximum external reference voltage of 2.5 V can be supplied to the REF
REF

/REFIN ADC pin.

OUT

portion of the

OUT

External Decoupling Capacitor Input for Internal Temperature Sensor. Decouple this pin to AGND
using a 0.1 F capacitor. In normal operation, the voltage is typically 3.7 V.

Current Sensor Supply Pins. Power supply pins for the high-side current sense amplifiers. Operating
range is from AV

to 59.4 V. Decouple this supply to AGND. See the Current Sense Filtering section.

DD

Rev. 0 | Page 11 of 44

AD7294

TYPICAL PERFORMANCE CHARACTERISTICS

20

8192 POINT FFT
AV

= DVDD = 5V

DD

V

0

= 5V, V

DRIVE

F

SAMPLE

F

= 10kHz, F

IN

–20

SINGLE ENDED
SNR = 71dB, THD = –82dB

–40

RANGE

REF

= 22.22kSPS

SCLK

= 400kHz

20

8192 POINT FFT
AV

= DVDD = 5V

DD

V

0

= 5V, 2V

DRIVE

F

= 22.22kSPS

SAMPLE

F

= 10kHz, F

IN

–20

DIFFERENTIAL
SNR = 73dB, T HD = –82dB

–40

REF

SCLK

RANGE

= 400kHz

–60

AMPLITUDE ( dB)

–80

–100

–120

0 100008000600040002000

FREQUENCY (kHz)

Figure 5. Signal-to-Noise Ratio Single-Ended, V

20

8192 POINT FFT
AV

= DVDD = 5V

DD

V

0

DRIVE

F

SAMPLE

F

= 10kHz, F

IN

–20

SINGLE ENDED
SNR = 72dB, THD = –80dB

–40

–60

AMPLITUDE ( dB)

–80

–100

–120

0 100008000600040002000

= 5V, 2V

REF

= 22.22kSPS

SCLK

RANGE

= 400kHz

FREQUENCY (kHz)

Figure 6. Signal-to-Noise Ratio Single-Ended, 2 × V

20

8192 POINT FFT
AV

= DVDD = 5V

DD

V

0

DRIVE

F

SAMPLE

F

= 10kHz, F

IN

–20

DIFFERENTIAL
SNR = 72dB, THD = –86dB

–40

–60

AMPLITUDE ( dB)

–80

–100

–120

0 100008000600040002000

= 5V, V

RANGE

REF

= 22.22kSPS

SCLK

= 400kHz

FREQUENCY (kHz)

Figure 7. Signal-to-Noise Ratio Differential, V

REF

Range

REF

Range

Range

REF

–60

AMPLITUDE ( dB)

–80

–100

–120

5747-088

5747-089

5747-087

0 100008000600040002000

FREQUENCY (kHz)

Figure 8. Signal-to-Noise Ratio Differential, 2 × V

1.0

0.8

0.6

0.4

0.2

0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

256

768

1280

5120

1024

1536

1792

2048

CODE

2304

TA = 25°C
V

DRIVE

V

REF

V

DD

SINGLE-E NDED

2560

Figure 9. ADC INL Single-Ended, V

1.0
TA = 25°C

V

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

DRIVE

0.8
V

REF

V

DD

0.6
SINGLE-ENDED

0.4

0.2

0

256

= 5V, V

= 2.5V

= 5V

5120

768

1024

REF

RANGE

1280

1536

1792

2048

CODE

2304

2560

Figure 10. ADC DNL Single-Ended, V

= 5V, V

= 2.5V

= 5V

2816

2816

3072

Range

REF

3072

REF

REF

REF

3328

3328

Range

Range

RANGE

3840

3584

3840

3584

5747-086

4096

05747-077

4096

05747-072

Rev. 0 | Page 12 of 44

AD7294

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

DNL (LSB)

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

1.0

0.8

0.6

0.4

0.2

0

256

768

1280

5120

1024

1536

1792

Figure 11. ADC INL Single-Ended, 2 × V

1.0
TA = 25°C

V

0.8
V

V

0.6
SINGLE-ENDED

DRIVE
REF
DD

= 5V

= 5V

= 5V, 2V

REF

RANGE

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

256

768

1280

5120

1024

1536

1792

Figure 12. ADC DNL Single-Ended, 2 × V

1.0

TA = 25°C
V

0.8

V
V

0.6

DIFFERENTIAL

DRIVE
REF
DD

= 5V, V

= 2.5V

= 5V

REF

RANGE

0.4

0.2

0

256

768

1280

5120

1024

1536

1792

Figure 13. ADC INL Differential, V

2048

CODE

2048

CODE

2048

CODE

2304

2304

2304

TA = 25°C
V

= 5V, 2V

DRIVE

V

= 2.5V

REF

V

= 5V

DD

SINGLE-E NDED

2816

2560

3072

REF

2816

2560

3072

REF

2816

2560

3072

Range

REF

REF

3328

3584

Range

3328

3584

Range

3328

3584

RANGE

3840

3840

3840

4096

4096

4096

05747-078

05747-073

05747-075

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

1.0
TA = 25°C

V

0.8
V

V

0.6
DIFFERENTIAL

DRIVE
REF
DD

= 5V

= 5V

= 5V, V

REF

RANGE

0.4

0.2

0

256

768

1280

5120

1024

1536

1792

Figure 14. ADC INL Differential, V

1.0

TA = 25°C

TA = 25°C
V

V

0.8

V

V
V

DIFFERENTIAL

0.6

DIFFERENTIAL

DRIVE
REF

REF

= 5V

DD
DD

= 5V, 2V

= 2.5V
= 2.5V

= 5V

REF

RANGE

0.4

0.2

0

256

768

1280

5120

1024

1536

1792

Figure 15. ADC DNL Differential, 2 × V

1.0

TA = 25°C
V

0.8

V
V

0.6

DIFFERENTIAL

DRIVE
REF
DD

= 5V, 2V

= 5V

= 5V

REF

RANGE

0.4

0.2

0

256

768

1280

5120

1024

1536

1792

Figure 16. ADC DNL Differential, 2 × V

2048

CODE

2048

CODE

2048

CODE

2304

2304

2304

2560

2560

2560

2816

REF

2816

2816

3328

3072

Range

3328

3072

Range

REF

3328

3072

Range

REF

3584

3584

3584

3840

3840

3840

4096

4096

4096

05747-076

05747-070

05747-071

Rev. 0 | Page 13 of 44

AD7294

1.5

1.0

0.5

0

–0.5

INL (LSB)

–1.0

–1.5

–2.0

MAX INL

MIN INL

T

= 25°C

A

= 5V, V

V

DRIVE

= 5V

V

DD

SINGLE-ENDED

2

C MODE 400kHz

I

REF

RANGE

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

AVDD = DVDD = 5V

= 5V, INTE RNAL REF,

V

DRIVE

OFFSET IN A/B/C/D = FLOATI NG

INL (LSB)

DNL (LS B)

–0.5

–1.0

–1.5

–2.0

–2.5

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

2.0

1.5

1.0

0.5

0

0654321

REFERENCE VOL TAGE (V)

Figure 17. ADC INL vs. Reference Voltage

MAX DNL

T
V
V
SINGLE-E NDED

2

I

MIN DNL

0654321

REFERENCE VOL TAGE (V)

Figure 18. ADC DNL vs. Reference Voltage

AVDD = DVDD = 5V

= 5V, INTE RNAL REF,

V

DRIVE

OFFSET IN A/B/C/D = FLOATI NG

256

768

1280

1792

5120

1024

1536

2048

CODE

2304

2560

Figure 19. DAC INL

= 25°C

A

= 5V, V

DRIVE
DD

C MODE 400kHz

= 5V

2816

3072

REF

3328

RANGE

3584

3840

4096

–0.6

256

768

1280

1792

2304

2816

3328

5120

1024

1536

2048

2560

5747-093

CODE

3072

3584

3840

4096

05747-080

Figure 20. DAC DNL

20

15

10

5

0

OUTPUT (µV)

–5

–10

–15

–20

5747-094

012345678910

TIME (s)

5747-097

Figure 21. 0.1 Hz to 10 Hz DAC Output Noise (Code 800)

5.0

4.5

4.0

3.5

3.0

2.5

2.0

DAC OUTPUT (V)

1.5

1.0

0.5

0

–5–4–3–2–1012345678910

05747-079

TIME (µs)

64pF
1nF
10nF

5747-084

Figure 22. Settling Time for a ¼ to ¾ Output Voltage Step

Rev. 0 | Page 14 of 44