Analog Devices AD7276 7 8 prg Datasheet

3 MSPS,12-/10-/8-Bit

Preliminary Technical Data

FEATURES

Fast throughput rate: 3 MSPS
Specified for VDD of 2.35 V to 3.6 V

Low power:

13.5 mW max at 3 MSPS with 3 V supplies

TBD mW typ at 1.5 MSPS with 3 V supplies

Wide input bandwidth:

70 dB SNR at 1 MHz input frequency

Flexible power/serial clock speed management

No pipeline delays

High speed serial interface

SPI®/QSPI™/MICROWIRE™/DSP compatible

Power-down mode: 1 µA max

6-lead TSOT package

8-lead MSOP package

AD7476 and AD7476A pin compatible

APPLICATIONS

Battery-powered systems

Personal digital assistants

Medical instruments

Mobile communications

Instrumentation and control systems

Data acquisition systems

High speed modems

Optical sensors

GENERAL DESCRIPTION

The AD7276/AD7277/AD7278 are 12-bit, 10-bit and 8-bit, high
speed, low power, successive-approximation ADCs respectively.
The parts operate from a single 2.35V to 3.6 V power supply
and feature throughput rates up to 3 MSPS. The parts contain a
low-noise, wide bandwidth track/hold amplifier which can
handle input frequencies in excess of TBD MHz.

The conversion process and data acquisition are controlled

CS

using
with microprocessors or DSPs. The input signal is sampled on
the falling edge of
point. There are no pipeline delays associated with the part.

The AD7276/AD7277/AD7278 use advanced design techniques
to achieve very low power dissipation at high throughput rates.

and the serial clock, allowing the devices to interface

CS

and the conversion is also initiated at this

ADCs in 6-Lead TSOT

AD7276/AD7277/AD7278

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

The reference for the part is taken internally from VDD. This
allows the widest dynamic input range to the ADC. Thus the
analog input range for the part is 0 to V
is determined by the SCLK.

PRODUCT HIGHLIGHTS

1. 3 MSPS ADCs in a 6-lead TSOT package.

2. AD7476/77/78 and AD7476A/77A/78A pin compatible.

3. High Throughput with Low Power Consumption.

4. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock
allowing the conversion time to be reduced through the serial
clock speed increase. This allows the average power
consumption to be reduced when a power-down mode is
used while not converting. The part also features a power­down mode to maximize power efficiency at lower
throughput rates. Current consumption is 1 µA max when in
Power-Down mode.

5. Reference derived from the power supply.

6. No Pipeline Delay.
The parts feature a standard successive-approximation ADC
with accurate control of the sampling instant via a
and once-off conversion control.

. The conversion rate

DD

CS

input

Rev. PrG

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infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

Preliminary Technical Data AD7276/AD7277/AD7278

TABLE OF CONTENTS

AD7278—Specifications.................................................................. 3

AD7277—Specifications.................................................................. 5

AD7276—Specifications.................................................................. 7

Timing Specifications....................................................................... 9

Timing Examples........................................................................ 10

Absolute Maximum Ratings.......................................................... 11

ESD Caution................................................................................ 11

Pin Configurations and Function Descriptions......................... 12

Terminology................................................................................ 13

Performance Curves....................................................................... 14

Dynamic Performance curves .................................................. 14

DC Accuracy Curves ................................................................. 14

Power Requirements Curves..................................................... 14

REVISION HISTORY

Typical Performance Characteristics........................................... 15

Theory of Operation ......................................................................17

Circuit Information.................................................................... 17

Converter Operation.................................................................. 17

ADC Transfer Function............................................................. 17

Typical Connection Diagram ................................................... 17

Modes of Operation................................................................... 19

Power Versus Throughput Rate................................................ 22

Serial Interface ................................................................................ 23

AD7278 in a 10 SCLK’s cycle Serial Interface ........................ 24

Outline Dimensions....................................................................... 25

Ordering Guide .......................................................................... 25

Revision PrF: Preliminary Version

Rev. PrG | Page 2 of 25

Preliminary Technical Data AD7276/AD7277/AD7278

AD7278—SPECIFICATIONS

VDD = +2.35 V to +3.6 V, f

= 52 MHz, f

SCLK

= 3 MSPS, TA = T

SAMPLE

MIN

to T

, unless otherwise noted.

MAX

Table 1.

Parameter B Grade1 Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 1MHz Sine Wave

Signal-to-Noise + Distortion (SINAD)2 49 dB min
Total Harmonic Distortion (THD)2 −65 dB max
Peak Harmonic or Spurious Noise (SFDR)2 −65 dB max
Intermodulation Distortion (IMD)2

Second Order Terms −76 dB typ fa = TBD kHz, fb = TBD kHz

Third Order Terms −76 dB typ fa = TBD kHz, fb = TBD kHz
Aperture Delay TBD ns typ
Aperture Jitter TBD ps typ
Full Power Bandwidth TBD MHz typ @ 3 dB
Full Power Bandwidth TBD MHz typ @ 0.1dB

DC ACCURACY

Resolution 8 Bits
Integral Nonlinearity2 ±0.3 LSB max
Differential Nonlinearity2 ±0.3 LSB max Guaranteed No Missed Codes to 8 Bits
Offset Error2 ±0.5 LSB max
±TBD LSB typ
Gain Error2 ±0.5 LSB max
±TBD LSB typ
Total Unadjusted Error (TUE)2 ±TBD LSB max

ANALOG INPUT

Input Voltage Ranges 0 to VDD Volts
DC Leakage Current ±0.5 µA max
Input Capacitance TBD pF typ

LOGIC INPUTS

Input High Voltage, V

1.7 V min 2.35V ≤ Vdd ≤ 2.7V

INH

2 V min 2.7V < Vdd ≤ 3.6V
Input Low Voltage, V

0.7 V max 2.35V ≤ Vdd< 2.7V

INL

0.8 V max 2.7V ≤ Vdd ≤ 3.6V
Input Current, IIN, SCLK Pin ±0.5 µA max Typically TBD nA, VIN = 0 V or VDD
Input Current, IIN, CS Pin
Input Capacitance, C

3

10 pF max

IN

± 1 µA max

LOGIC OUTPUTS

Output High Voltage, VOH V
Output Low Voltage, VOL 0.2 V max I

– 0.2 V min I

DD

= 200 µA,VDD = 2.35 V to 3.6V

SOURCE

= 200µA

SINK

Floating-State Leakage Current ±1 µA ma
Floating-State Output Capacitance3 10 pF max
Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 192 ns max 10 SCLK Cycles with SCLK at 52 MHz
Track/Hold Acquisition Time2 50 ns max
Throughput Rate 3 MSPS max

POWER REQUIREMENTS

Rev. PrG | Page 3 of 25

AD7276/AD7277/AD7278 Preliminary Technical Data

Parameter B Grade1 Unit Test Conditions/Comments

VDD 2.35/3.6 Vmin/max
IDD Digital I/Ps= 0V or VDD

Normal Mode(Static) 2.5 mA typ VDD = 2.35V to 3.6V, SCLK On or Off
Normal Mode (Operational) 4.5 mA max VDD = 2.35V to 3.6V, f
Full Power-Down Mode (Static) 1 µA max SCLK On or Off, typically TBD nA

Power Dissipation4

Normal Mode (Operational)

13.5 mW max VDD = 3V, f

SAMPLE

= 3 MSPS
Partial Power Down Mode
Full Power-Down 3 µW max VDD = 3V

1

Temperature range from −40°C to +85°C.

2

See Terminology.

3

Guaranteed by characterization.

4

See Power Versus Throughput Rate section.

Specifications subject to change without notice.

SAMPLE

= 3MSPS

Rev. PrG | Page 4 of 25

Preliminary Technical Data AD7276/AD7277/AD7278

AD7277—SPECIFICATIONS

VDD =+2.35 V to +3.6 V, f

= 52 MHz, f

SCLK

= 3 MSPS, TA = T

SAMPLE

MIN

to T

, unless otherwise noted.

MAX

Table 2.

Parameter B Grade

DYNAMIC PERFORMANCE

Signal-to-Noise + Distortion (SINAD)

Total Harmonic Distortion (THD)

2

Peak Harmonic or Spurious Noise (SFDR)

Intermodulation Distortion (IMD)

2

2

61 dB min

−73 dB max

2

−74 dB max

1

Unit Test Conditions/Comments

fIN = 1 MHz Sine Wave

Second Order Terms −82 dB typ fa = TBD kHz, fb = TBD kHz
Third Order Terms −82 dB typ fa = TBD kHz, fb = TBD kHz

Aperture Delay TBD ns typ

Aperture Jitter TBD ps typ

Full Power Bandwidth TBD MHz typ @ 3 dB
Full Power Bandwidth TBD MHz typ @ 0.1dB

DC ACCURACY

Resolution 10 Bits

Integral Nonlinearity

Differential Nonlinearity
Offset Error

2

±1 LSB max

2

±0.5 LSB max

2

±0.5 LSB max Guaranteed No Missed Codes to 10 Bits

Gain Error

2

±1 LSB max

Total Unadjusted Error (TUE)

ANALOG INPUT

Input Voltage Ranges 0 to V

DC Leakage Current ±0.5 µA max

Input Capacitance TBD pF typ

LOGIC INPUTS

Input High Voltage, V

2

±TBD LSB max

1.7 V min 2.35V ≤ Vdd ≤ 2.7V

INH

Input Low Voltage, V

0.7 V max 2.35V ≤ Vdd< 2.7V

INL

±TBD LSB typ

±TBD LSB typ

Volts

DD

2 V min 2.7V <Vdd ≤ 3.6V

0.8 V max 2.7V ≤ Vdd ≤ 3.6V

Input Current, IIN, SCLK Pin ±0.5 µA max Typically TBD nA, VIN = 0 V or V
Input Current, IIN, CS Pin

Input Capacitance, C

3

10 pF max

IN

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V

V

OH

0.2 V max I

OL

Floating-State Leakage Current ±1 µA max

± 1 µA max

– 0.2 V min I

DD

= 200 µA,VDD= 2.35 V to 3.6 V

SOURCE

= 200µA

SINK

DD

Rev. PrG | Page 5 of 25

AD7276/AD7277/AD7278 Preliminary Technical Data

Parameter B Grade

Floating-State Output Capacitance

3

10 pF max

Output Coding Straight (Natural) Binary

CONVERSION RATE

1

Unit Test Conditions/Comments

Conversion Time 230 ns max 12 SCLK cycles with SCLK at 52 MHz
Track/Hold Acquisition Time

Throughput Rate 3 MSPS max

POWER REQUIREMENTS

V

2.35/3.6 V min/max

DD

I

DD

2

50 ns max

Digital I/Ps 0V or V

DD

Normal Mode(Static) 2.5 mA typ VDD = 2.35V to 3.6V, SCLK On or Off
Normal Mode (Operational) 4.5 mA max VDD = 2.35V to 3.6V, f

SAMPLE

= 3MSPS
Full Power-Down Mode(Static) 1 µA max SCLK On or Off, typically TBD nA
Full Power-Down Mode(Dynamic) TBD mA typ VDD = 3V, f

Power Dissipation

Normal Mode (Operational)

4

13.5 mW max VDD = 3V, f

SAMPLE

SAMPLE

= 1 MSPS

= 3 MSPS
Partial Power-Down
Full Power-Down 3 µW max VDD =3V

1

Temperature range from −40°C to +85°C.

2

See Terminology.

3

Guaranteed by Characterization.

4

See Power Versus Throughput Rate section.

Specifications subject to change without notice.

Rev. PrG | Page 6 of 25

Preliminary Technical Data AD7276/AD7277/AD7278

AD7276—SPECIFICATIONS

VDD = +2.35 V to +3.6 V, f

= 52 MHz, f

SCLK

= 3 MSPS, TA = T

SAMPLE

MIN

to T

, unless otherwise noted.

MAX

Table 3.

Parameter B Grade1 Units Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 1 MHz Sine Wave

Signal-to-Noise + Distortion (SINAD)2 70 dB min
Signal-to-Noise Ratio (SNR) 71 dB min
Total Harmonic Distortion (THD)2 −80 dB max
Peak Harmonic or Spurious Noise (SFDR)2 −82 dB max
Intermodulation Distortion (IMD)2

Second Order Terms −84 dB typ Fa = TBD kHz, fb = TBD kHz

Third Order Term −84 dB typ Fa = TBD kHz, fb = TBD kHz
Aperture Delay TBD ns typ
Aperture Jitter TBD ps typ
Full Power Bandwidth TBD MHz typ @ 3 dB
Full Power Bandwidth TBD MHz typ @ 0.1dB

DC ACCURACY

Resolution 12 Bits
Integral Nonlinearity2 ±1 LSB max
Differential Nonlinearity2 ±1 LSB max Guaranteed No Missed Codes to 12 Bits
Offset Error2 ±TBD LSB max
Gain Error2 ±TBD LSB max
Total Unadjusted Error (TUE)2 ±TBD LSB max

ANALOG INPUT

Input Voltage Ranges 0 to VDD Volts
DC Leakage Current ±0.5 µA max
Input Capacitance TBD pF typ

LOGIC INPUTS

Input High Voltage, V

1.7 V min 2.35V ≤ Vdd ≤ 2.7V

INH

2 V min 2.7V < Vdd ≤ 3.6V
Input Low Voltage, V

0.7 V max 2.35V ≤ Vdd< 2.7V

INL

0.8 V max 2.7V ≤ Vdd ≤ 3.6V
Input Current, IIN,SCLK Pin ±0.5 µA max Typically TBDnA, VIN = 0 V or VDD
Input Current, IIN, CS Pin
Input Capacitance, C

3

10 pF max

IN

± 1 µA max

LOGIC OUTPUTS

Output High Voltage, VOH V
Output Low Voltage, VOL 0.2 V max I

–0.2 V min I

DD

= 200 µA;VDD = 2.35 V to 3.6V

SOURCE

=200 µA

SINK

Floating-State Leakage Current ±1 µA max
Floating-State Output Capacitance3 10 pF max
Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 270 ns max 14 SCLK Cycles with SCLK at 52 MHz
Track/Hold Acquisition Time2 50 ns max
Throughput Rate 3 MSPS max See Serial Interface Section

POWER REQUIREMENTS

VDD 2.35/3.6 V min/max

Rev. PrG | Page 7 of 25

AD7276/AD7277/AD7278 Preliminary Technical Data

Parameter B Grade1 Units Test Conditions/Comments

IDD Digital I/Ps 0V or VDD

Normal Mode(Static) 2.5 mA typ VDD = 2.35V to 3.6V, SCLK On or Off
Normal Mode (Operational) 4.5 mA max VDD = 2.35V to 3.6V, f
Full Power-Down Mode(Static) 1 µA max SCLK On or Off, typically TBD nA
Full Power-Down Mode(Dynamic) TBD mA typ VDD = 3V, f

SAMPLE

= 1MSPS

Power Dissipation4

Normal Mode (Operational)

13.5 mW max VDD = 3V, f

SAMPLE

= 3MSPS
Partial Power-Down
Full Power-Down 3 µW max VDD =3V

1

Temperature range from −40°C to +85°C.

2

See Terminology.

3

Guaranteed by Characterization.

4

See Power Versus Throughput Rate section.

Specifications subject to change without notice.

SAMPLE

= 3MSPS

Rev. PrG | Page 8 of 25