Datasheet AD7266 Datasheet (Analog Devices)

Differential Input, Dual 2 MSPS,

V

VA2VA3V

V

V

VB1VB2VB3VB4VB5V

Preliminary Technical Data

FEATURES

Dual 12-bit, 3-channel ADC
Fast throughput rate: 2 MSPS
Specified for V
Low power: 12 mW max at 1.5 MSPS with 3 V supplies
30 mW max at 2 MSPS with 5 V supplies
Wide input bandwidth
70 dB SNR at 100 kHz input frequency
On-chip reference: 2.5 V
–40°C to +125°C operation
Flexible power/throughput rate management
Simultaneous conversion/read
No pipeline delays
High speed serial interface SPI®/QSPI™/MICROWIRE™/DSP
compatible
Shutdown mode: 1 µA max
32-lead LFCSP and TQFP packages

GENERAL DESCRIPTION

The AD72661 is a dual, 12-bit , high speed, low power, successive
approximation ADC that operates from a single 2.7 V to 5.25 V
power supply and features throughput rates up to 2 MSPS. The
device contains two ADCs, each preceded by a 3-channel multi­plexer, and a low noise, wide bandwidth track-and-hold amplifier
that can handle input frequencies in excess of 10 MHz.

The conversion process and data acquisition are controlled using
standard control inputs, allowing easy interfacing to microproces­sors or DSPs. The input signal is sampled on the falling edge of
conversion is also initiated at this point. The conversion time is
determined by the SCLK frequency. There are no pipelined delays
associated with the part.
The AD7266 uses advanced design techniques to achieve very low
power dissipation at high throughput rates. With 5 V supplies and a
2 MSPS throughput rate, the part consumes 4 mA maximum. The
part also offers flexible power/throughput rate management when
operating in sleep mode.

The analog input range for the part can be selected to be a 0 V to
V

range or a 2V

REF

complement output coding. The AD7266 has an on-chip 2.5 V
reference that can be overdriven if an external reference is pre­ferred. This external reference range is 100 mV to 2.5 V. The
AD7266 is available in 32-lead lead frame chip scale (LFCSP) and
thin quad flat (TQFP) packages.

1

Protected by U.S. Patent No. 6,681,332.

Rev. PrG

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

of 2.7 V to 5.25 V

DD

range with either straight binary or twos

REF

CS

;

12-Bit, 3-Channel SAR ADC

AD7266

FUNCTIONAL BLOCK DIAGRAM

REF SELECT D

BUF

REF

A1

MUX

A4

A5

A6

MUX

B6

AGND AGND AGND D

T/H

T/H

BUF

PRODUCT HIGHLIGHTS

1. The AD7266 features two complete ADC functions that allow

simultaneous sampling and conversion of two channels. Each
ADC has 2 analog inputs, 3 fully differential pairs, or 6 single­ended channels as programmed. The conversion result of both
channels is available simultaneously on separate data lines, or
in succession on one data line if only one serial port is
available.

2. High Throughput with Low Power Consumption

The AD7266 offers a 1.5 MSPS throughput rate with 8 mW
maximum power consumption when operating at 3 V.

3. Flexible Power/Throughput Rate Management

The conversion rate is determined by the serial clock, allowing
power consumption to be reduced as conversion time is re­duced through an SCLK frequency increase. Power efficiency
can be maximized at lower throughput rates if the part enters
sleep between conversions.

4. No Pipeline Delay

The part features two standard successive approximation
ADCs with accurate control of the sampling instant via a
input and once off conversion control.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

A AV

CAP

DD

AD7266

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

CONTROL

LOGIC

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

B DGND DGND

CAP

Figure 1

DV

DD

OUTPUT

DRIVERS

OUTPUT

DRIVERS

D

A

OUT

SCLK

CS
RANGE
SGL/DIFF
A0
A1
A2

V

DRIVE

D

B

OUT

04603-PrA-001

CS

AD7266 Preliminary Technical Data

TABLE OF CONTENTS

AD7266—Specifications.................................................................. 3

Timing Specifications .................................................................. 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Functional Descriptions.......................... 6

Terminology ...................................................................................... 8

Theory of Operation...................................................................... 10

Circuit Information.................................................................... 10

Converter Operation.................................................................. 10

Analog Input............................................................................... 11

REVISION HISTORY

Revision PrG: Preliminary Version

Output Coding............................................................................ 11

Transfer Functions ..................................................................... 12

Digital Inputs .............................................................................. 12

V

............................................................................................ 12

DRIVE

Modes of Operation ....................................................................... 13

Normal Mode.............................................................................. 13

Partial Power-Down Mode ....................................................... 13

Full Power-Down Mode............................................................ 14

Outline Dimensions....................................................................... 15

Ordering Guide............................................................................... 17

Rev. PrG | Page 2 of 17

Preliminary Technical Data AD7266

AD7266—SPECIFICATIONS1

Table 1. TA = T

= 32 MHz, fS = 2 MSPS, V

f

SCLK

Parameter Specification Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal-to-Noise + Distortion Ratio (SINAD)
Total Harmonic Distortion (THD)
Spurious Free Dynamic Range (SFDR)
Intermodulation Distortion (IMD)

Second Order Terms –88 dB typ
Third Order Terms –88 dB typ
Channel to Channel Isolation –88 dB typ

SAMPLE AND HOLD

Aperture Delay3 10 ns max
Aperture Jitter3 50 ps typ
Aperture Delay Matching3 200 ps max
Full Power Bandwidth 20 MHz typ @ 3 dB

2.5 MHz typ @0.1 dB
DC ACCURACY

Resolution 12 Bits
Integral Nonlinearity

±1.5 LSB max ±0.5 LSB typ; single-ended configuration

Differential Nonlinearity
0 V to V

REF

Offset Error ±3 LSB max
Offset Error Match ±0.5 LSB typ
Gain Error ±2 LSB max
Gain Error Match ±0.6 LSB typ

0 V to 2 × V

Positive Gain Error ±2 LSB max
Zero Code Error ±3 LSB max
Zero Code Error Match ±1 LSB typ
Negative Gain Error ±1 LSB max

ANALOG INPUT

Input Voltage Ranges 0 V to V

0 V to 2 x V

DC Leakage Current ±500 nA max TA = –40°C to +85°C
±1 µA max 85°C < TA ≤ 125°C

Input Capactiance 30 pF typ When in track
10 pF typ When in hold
REFERENCE INPUT/OUTPUT

Reference Output Voltage

Reference Input Voltage Range 0.1/2.5 V min/V max See Typical Performance plots

DC Leakage Current ±30 µA max V
±160 µA max D

Input Capactiance 20 pF typ

V

Output Impedance

REF

Reference Temperature Coefficient 25 ppm/°C max

10 ppm/°C typ
LOGIC INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, IIN ±1 µA max Typically 15 nA, VIN = 0 V or V

Input Capacitance, C

MIN

to T

, VDD = 2.7 V to 3.3 V, f

MAX

= 2.7 V to 5.25 V; Reference = 2.5 V ± 1%, unless otherwise noted

DRIVE

2

2

2

2

2

= 25 MHz, fS = 1.5 MSPS, V

SCLK

2

70 dB min fIN = 100 kHz sine wave

= 2.7 V to 3.3 V; VDD = 4.75 V to 5.25 V,

DRIVE

–75 dB max fIN = 100 kHz sine wave
–76 dB max fIN = 100 kHz sine wave

±1 LSB max ±0.5 LSB typ; differential configuration

±0.95 LSB max Guaranteed no missed codes to 12 bits

Input Range Straight binary output coding

Input Range Twos complement output coding

REF

V

REF

V

REF

4

5

2.8 V min

INH

0.4 V max

INL

3

IN

2.49/2.51 V min/V max

25 Ω typ

10 pF max

RANGE pin low upon

RANGE pin high upon CS falling edge

pin

REF

A, D

CAP

B pins

CAP

CS

falling edge

DRIVE

Rev. PrG | Page 3 of 17

AD7266 Preliminary Technical Data

Parameter Specification Unit Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage, VOH V
Output Low Voltage, VOL 0.4 V max
Floating State Leakage Current ±1 µA max
Floating State Output Capacitance

3

Output Coding Straight (Natural) Binary

Twos Complement

CONVERSION RATE

Conversion Time 14 SCLK Cycles 437.5 ns with SCLK = 32 MHz
Track/Hold Acquisition Time

3

Throughput Rate 2 MSPS max

POWER REQUIREMENTS

V

DD

V

2.7/5.25 V min/V max

DRIVE

6

I

DD

Normal Mode (Static) 2 mA max
Operational, fs = 2 MSPS 6 mA max VDD = 5 V
4 mA max VDD = 3 V
Partial Power-Down Mode TBD mA max fs = 200 kSPS
Partial Power-Down Mode 500 µA max Static
Full Power-Down Mode 1 µA max

Power Dissipation

6

Normal Mode (Operational) 30 mW max VDD = 5 V
Partial Power-Down (Static) 2.5 mW max VDD = 5 V
Full Power-Down (Static) 5 µW max VDD = 5 V

NOTES

1

Temperature ranges as follows: -40°C to +125°C

2

See section. Terminology

3

Sample tested during initial release to ensure compliance.

4

Relates to Pins D

5

See Reference section for D

6

See Power Versus Throughput Rate section.

CAP

A or D

B.

CAP

A, D

B output impedances.

CAP

CAP

TIMING SPECIFICATIONS

Table 2. AVDD = DVDD = 2.7 V to 5.25 V, V

Parameter Limit at T

f

SCLK

10 kHz min
34 MHz max
t

CONVERT

14 × t

437.5 ns max f
560 ns max f
t

35 ns max

QUIET

t

2

t

3

t

4

t5 0.4t
t6 0.4t
t

7

t

8

10 ns min

25 ns max

25 ns max Data access time after SCLK falling edge.

SCLK

SCLK

5 ns min SCLK to data valid hold time

25 ns max

t9 60 ns min

t

10

5 ns min SCLK falling edge to D
30 ns max SCLK falling edge to D

All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used.

, T

MIN

MAX

ns max t

SCLK

ns min SCLK high pulse width

DRIVE

Unit Description

ns min SCLK low pulse width

– 0.2 V min

DRIVE

10 pF max

DIFF

SGL/

SGL/

= 1 with 0 V to V

DIFF

= 0; SGL/

DIFF

100 ns max

2.7/5.25 V min/V max

Digital I/Ps = 0 V or V

= 2.7 V to 5.25 V, TA = T

= 1/f

SCLK

SCLK

SCLK

SCLK

= 32 MHz, VDD = 5 V, F
= 25 MHz, VDD = 3 V, F

MAX

to T

, unless otherwise noted

MIN

= 2 MSPS

SAMPLE

= 1.5 MSPS

SAMPLE

Minimum time between end of serial read and next falling edge of
CS

to SCLK setup time

CS

Delay from

CS

rising edge to D

CS

rising edge to falling edge pulsewidth

until D

OUT

A and D

OUT

A, D

B, high impedance

OUT

A, D

OUT

OUT

A, D

OUT

OUT

B are three-state disabled

OUT

B, high impedance
B, high impedance

range selected

REF

= 1 with 0 V to 2 × V

DRIVE

CS

range

REF

Rev. PrG | Page 4 of 17

Preliminary Technical Data AD7266

ABSOLUTE MAXIMUM RATINGS

Table 3. AD7266 Stress Ratings

Parameter Rating

VDD to AGND –0.3 V to +7 V
DVDD to DGND –0.3 V to +7 V
V

to DGND –0.3 V to DVDD

DRIVE

V

to AGND –0.3 V to AVDD

DRIVE

AVDD to DVDD –0.3 V to +0.3 V
AGND to DGND –0.3 V to +0.3 V
Analog Input Voltage to AGND –0.3 V to AVDD +0.3 V
Digital Input Voltage to DGND –0.3 V to +7 V
Digital Output Voltage to GND –0.3 V to V
V

to AGND –0.3 V to AVDD +0.3 V

REF

Input Current to Any Pin Except

Supplies

1

±10 mA

DRIVE

+0.3 V

Operating Temperature Range –40°C to +125°C
Storage Temperature Range –65°C to +150°C
Junction Temperature 150°C
LFCSP Package

θJA Thermal Impedance 108.2°C/W
θJC Thermal Impedance 32.71°C/W

Lead Temperature, Soldering

Reflow Temperature (10- 30 sec) 255°C

ESD TBD

1

Transient currents of up to 100 mA will not cause SCR latch up.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. PrG | Page 5 of 17

AD7266 Preliminary Technical Data

E

A

B

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

DD

OUT

OUT

D

DGND28D

29

AD7266

TOP VIEW

(Not to Scale)

12

13

A5

A6

B6

V

V

V

SCLK26CS25A0

27

14

15

B5

B4

V

V

24

A1

23

A2

22

SGL/DIFF

21

RANGE

20

D

B

CAP

19

AGND

18

V

B1

17

V

B2

16

B3

V

04603-PrA-002

DD

CS

is held low for 16 SCLK cycles

CS

is held low for a further 16 SCLK

pin. This allows data

OUT

A or D

OUT

and DVDD but

B alone

OUT

DD

REF SELECT

Table 4. AD7266 Pin Function Descriptions

Pin No. Mnemonic Description

4, 20

A,

D

CAP

B

D

CAP

Decoupling capacitors (470nF recommended) are connected to these pins to decouple the reference buffer for
each respective ADC. The on-chip reference can be taken from these pins and applied externally to the rest of a
system. The range of the external reference is dependent on the analog input range selected. See the Reference
Configuration Options section.

7–12 VA1–VA6

Analog Inputs of ADC A. These may be programmed as six single-ended channels or three true differential analog
input channel pairs. See Table 6.

18–13 VB1–VB6

Analog Inputs of ADC B. These may be programmed as six single-ended channels or three true differential analog
input channel pairs. See Table 6.

27 SCLK

Serial Clock. Logic Input. A serial clock input provides the SCLK for accessing the data from the AD7266. This clock
is also used as the clock source for the conversion process.

5, 6, 19 AGND

Analog Ground. Ground reference point for all analog circuitry on the AD7266. All analog input signals and any
external reference signal should be referred to this AGND voltage. All three of these AGND pins should connect to
the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must not
be more than 0.3 V apart, even on a transient basis.

32 DVDD

Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD7266. The DV
and AV

voltages should ideally be at the same potential and must not be more than 0.3 V apart even on a

DD

transient basis. This supply should be decoupled to DGND.

31 V

DRIVE

Logic power supply input. The voltage supplied at this pin determines at what voltage the interface will operate.
This pin should be decoupled to DGND. The voltage at this pin may be different to that at AV
should never exceed either by more than 0.3 V.

1, 29 DGND

Digital Ground. This is the ground reference point for all digital circuitry on the AD7266. Both DGND pins should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.

3 AVDD

Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7266. The

and DVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a

AV

DD

transient basis. This supply should be decoupled to AGND.

26

CS

Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7266
and frames the serial data transfer.

30, 28

A,

D

OUT

B

D

OUT

Serial Data Outputs. The data output is supplied to this pin as a serial data stream. The bits are clocked out on the
falling edge of the SCLK input and 14 SCLKs are required to access the data. The data appears on both pins
simultaneously from the simultaneous conversions of both ADCs. The data stream consists of two leading zeros

followed by the 12 bits of conversion data. The data is provided MSB first. If
rather than 14, then two trailing zeros will appear after the 12 bits of data. If

cycles after this on either D
from a simultaneous conversion on both ADCs to be gathered in serial format on either D
using only one serial port. See the Serial Interface section.

DRIV

DV

V

32

31

30

1

DGND

2

3

AV

DD

4

D

A

CAP

5

AGND

6

AGND

7

V

A1

8

V

A2

9

10

11

A3

A4

V

V

Figure 2. AD7266 Pin Configuration

OUT

A or D

B, the data from the other ADC follows on the D

OUT

Rev. PrG | Page 6 of 17

Preliminary Technical Data AD7266

Pin No. Mnemonic Description

21 RANGE

25–23 A0–A2

22

SGL/

DIFF

2 REF SELECT

Analog Input Range Selection. Logic input. The polarity on this pin will determine what input range the analog

CS

input channels will have. On the falling edge of

, the polarity of this pin is checked to determine the analog
input range of the next conversion. If this pin is tied to a logic low, the analog input range is 0 V to VREF. If this pin
is tied to a logic high when

CS

goes low, the analog input range is 2 × V

REF

.

Multiplexer Select. Logic inputs. Thess inputs are used to select the pair of channels to be converted
simultaneously, i.e., Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC, and so on. The pair of
channels selected may be two single ended channels or two differential pairs. The logic states of these pins are

CS

checked upon the falling edge of
multiplexer address decoding.

Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single ended. A logic

, and the multiplexer is set up for the next conversion. See Table 6 for

low selects differential operation while a logic high selects single ended operation.
Internal/External reference Selection. Logic Input. If this pin is tied to GND, the on-chip 2.5 V reference is used as

the reference source for both ADC A and ADC B. In addition, Pins D

A and D

CAP

B must be tied to decoupling

CAP

capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the AD7266
through the D

A and/or D

CAP

CAP

B pins.

Rev. PrG | Page 7 of 17

AD7266 Preliminary Technical Data

TERMINOLOGY

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

Integral Nonlinearity

This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.

Offset Error

This applies to Straight Binary output coding. It is the deviation
of the first code transition (00 . . . 000) to (00 . . . 001) from the
ideal, i.e., AGND + 1 LSB.

Offset Error Match

This is the difference in Offset Error between the two channels.

Gain Error

This applies to Straight Binary output coding. It is the deviation
of the last code transition (111 . . . 110) to (111 . . . 111) from the
ideal (i.e., VREF – 1 LSB) after the offset error has been adjusted
out.

Gain Error Match

This is the difference in Gain Error between the two channels.

Zero Code Error

This applies when using twos complement output coding in
particular with the 2 x V
about the V

point. It is the deviation of the midscale

REF

input range as –V

REF

transition (all 1s to all 0s) from the ideal V

to +V

REF

voltage, i.e., V

IN

biased

REF

REF

- 1

LSB.

Zero Code Error Match

This refers to the difference in Zero Code Error between the
two channels.

Track-and-Hold Acquisition Time

The track-and-hold amplifier returns into track mode after the
end of conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1/2 LSB, after the end of conversion.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all non-fundamental
signals up to half the sampling frequency (f

/2), excluding dc.

S

The ratio is dependent on the number of quantization levels in
the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal to (noise + distortion)
ratio for an ideal N-bit converter with a sine wave input is given
by:

Signal to (Noise + Distortion) = (6.02N + 1.76) dB

Thus for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7266 it is defined as:

2

2

dBTHD

where V
V

is the rms amplitude of the fundamental and V2, V3,

1

, V5 and V6 are the rms amplitudes of the second through the

4

log20)(

=

4

3

V

1

VVVVV

++++

6

5

2

2

2

2

sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it will
be a noise peak.

Positive Gain Error

This applies when using twos complement output coding in
particular with the 2 x V
about the V

point. It is the deviation of the last code

REF

input range as –V

REF

REF

to +V

biased

REF

transition (011…110) to (011…111) from the ideal (i.e., + V
1 LSB) after the Zero Code Error has been adjusted out.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full­scale (2 x V
channels and determining how much that signal is attenuated in

-

REF

the selected channel with a 10 kHz signal (0 V to V
figure given is the worst-case across all twelve channels for the
AD7266.

Rev. PrG | Page 8 of 17

), 455kHz sine wave signal to all unselected input

REF

). The

REF

Preliminary Technical Data AD7266

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those
for which neither m nor n are equal to zero. For example, the
second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa
– 2fb).

The AD7266 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second order terms are usually distanced in
frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies.

As a result, the second and third order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in dBs.

PSR (Power Supply Rejection)

Variations in power supply will affect the full-scale transition
but not the converter’s linearity. Power supply rejection is the
maximum change in full-scale transition point due to a change
in power supply voltage from the nominal value. See Typical
Performance Curves.

Rev. PrG | Page 9 of 17

AD7266 Preliminary Technical Data

THEORY OF OPERATION

CIRCUIT INFORMATION

The AD7266 is a fast, micropower, dual 12-bit, single supply,
A/D converter that operates from a 2.7 V to 5.25 V supply.
When operated from a 5 V supply, the AD7266 is capable of
throughput rates of 2 MSPS when provided with a TBD MHz
clock, and a throughput rate of 1.5 MSPS at 3 V.

The AD7266 contains two on-chip differential track-and-hold
amplifiers, two successive approximation A/D converters, and a
serial interface with two separate data output pins, and is
housed in a 32-lead LFCSP package, which offers the user
considerable space-saving advantages over alternative solutions.
The serial clock input accesses data from the part but also
provides the clock source for each successive approximation
ADC. The analog input range for the part can be selected to be a
0 V to V

input or a 2 × V

REF

input with the analog inputs

REF

configured as either single ended or differential. The AD7266
has an on-chip 2.5 V reference that can be overdriven if an
external reference is preferred.

The AD7266 also features power-down options to allow power
saving between conversions. The power-down feature is
implemented across the standard serial interface, as described in
the Modes of Operation section.

CONVERTER OPERATION

The AD7266 has two successive approximation analog-to­digital converters, each based around two capacitive DACs.
Figure 3 and Figure 4 show simplified schematics of one of
these ADCs in acquisition and conversion phase, respectively.
The ADC is comprised of control logic, a SAR, and two
capacitive DACs. In Figure 3 (the acquisition phase), SW3, is
closed, SW1 and SW2 are in position A, the comparator is held
in a balanced condition, and the sampling capacitor arrays
acquire the differential signal on the input.

C

B

V

IN+

A

A

V

IN–

B

V

SW1

SW2

REF

S

C

S

COMPARATOR

SW3

Figure 3. ADC Acquisition Phase

When the ADC starts a conversion (Figure 4), SW3 opens and
SW1 and SW2 move to position B, causing the comparator to
become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge redistribu­tion DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the ADC output code. The output impedances of the
sources driving the V

IN+

and V

pins must be matched;

IN–

otherwise, the two inputs will have different settling times,
resulting in errors.

C

B

V

IN+

A

A

V

IN–

B

V

SW1

SW2

REF

S

C

S

Figure 4. ADC Conversion Phase

COMPARATOR

SW3

CAPACITIVE

DAC

CONTROL

LOGIC

CAPACITIVE

DAC

CAPACITIVE

DAC

CONTROL

LOGIC

CAPACITIVE

DAC

04603-PrA-003

04603-PrA-004

Rev. PrG | Page 10 of 17

Preliminary Technical Data AD7266

S

ANALOG INPUT

The analog inputs of the AD7266 may be configured as single
ended or true differential via the SGL/
in Figure 5. On the falling edge of

DIFF

the SGL/

pin is checked to determine the configuration of
the analog input channels for the next conversion. If this pin is
tied to a logic low, the analog input channels to each on-chip
ADC are set up as three true differential pairs. If this pin is at a

CS

logic high when

goes low, the analog input channels to each
on-chip ADC are set up as six single-ended analog inputs. In
Figure 5 at point A, the SGL/

DIFF

analog inputs are configured as single-ended for the next
conversion, i.e. sampling point B. At point B, the logic level of

DIFF

the SGL/

pin has changed to low; there fore, the analog
inputs are configured as differential for the next conversion
after this one, even though this current conversion is on single
ended configured inputs.

CS

SCLK

GL/DIFF

Figure 5. Selecting Differential or Single Ended Configuration

A

114 1 14

DIFF

logic pin, as shown

CS

, point A, the logic level of

pin is at a logic high so the

B

04603-PrA-005

The channels to be converted on simultaneously are selected via
the multiplexer address inputs A0 to A2. The logic states of

CS

these pins are also checked upon the falling edge of

and the
channels are chosen for the next conversion. The selected input
channels are decoded as shown in Table 6.

The analog input range of the AD7266 can be selected as 0 V to

or 0 V to 2 × V

V

REF

made in a similar fashion to that of the SGL/

via the RANGE pin. This selection is

REF

DIFF

pin by

checking the logic state of the RANGE pin upon the falling edge

CS

. The analog input range is set up for the next conversion.

of

CS

If this pin is tied to a logic low upon the falling edge of
analog input range for the next conversion is 0 V to V
pin is tied to a logic high upon the falling edge of
input range for the next conversion is 0 V to 2 × V

CS

REF

, the

. If this

REF

, the analog
.

OUTPUT CODING

The AD7266 output coding is set to either twos complement or
straight binary depending on which analog input configuration
is selected for a conversion. Table 5 shows which output coding
scheme is used for each possible analog input configuration.

Table 5 AD7266 Output Coding

DIFF

SGL/

DIFF 0 V to V
DIFF 0 V to 2 × V
SGL 0 V to V
SGL 0 V to 2 × V
PSUEDO DIFF 0 V to V
PSUEDO DIFF 0 V to 2 × V

Range Output Coding

REF

REF

Straight Binary

REF

REF

Straight Binary

REF

REF

Twos Complement

Twos Complement

Twos Complement

Twos Complement

Table 6. Analog Input Type and Channel Selection

ADC A ADC B

SGL/

DIFF

V

A2 A1 A0

IN+

V

IN–

IN+

V

Comment

IN–

V

1 0 0 0 VA1 AGND VB1 AGND Single Ended
1 0 0 1 VA2 AGND VB2 AGND Single Ended
1 0 1 0 VA3 AGND VB3 AGND Single Ended
1 0 1 1 VA4 AGND VB4 AGND Single Ended
1 1 0 0 VA5 AGND VB5 AGND Single Ended
1 1 0 1 VA6 AGND VB6 AGND Single Ended
0 0 0 0 VA1
0 0 0 1 VA1 VA2 V
0 0 1 0 VA3 VA4 V
0 0 1 1 VA3 VA4 V
0 1 0 0 VA5 VA6 V
0 1 0 1 VA5 V

VA2 V

V

A6

VB2 Fully Differential

B1

V

B1

VB4 Fully Differential

B3

V

B3

VB6 Fully Differential

B5

V

B5

Pseudodifferential

B2

Pseudodifferential

B4

Pseudodifferential

B6

Rev. PrG | Page 11 of 17

AD7266 Preliminary Technical Data

TRANSFER FUNCTIONS

The designed code transitions occur at successive integer LSB
values (i.e., 1 LSB, 2 LSB, and so on). The LSB size is V
The ideal transfer characteristic for the AD7266 when straight
binary coding is output is shown in Figure 6, and the ideal
transfer characteristic for the AD7266 when twos complement
coding is output is shown in Figure 7.

111...111

111...110

111...000

011...111

ADC CODE

000...010

000...001

000...000

1LSB = V

1LSB V

0V

ANALOG INPUT

Figure 6. Straight Binary Transfer Characteristic

REF

REF

/4096

– 1LSB

REF

/4096.

04603-PrA-006

DIGITAL INPUTS

The digital inputs applied to the AD7266 are not limited by the
maximum ratings that limit the analog inputs. Instead, the
digital inputs applied can go to 7 V and are not restricted by the

+ 0.3 V limit as on the analog inputs. See the Absolute

V

DD

Maximum Ratings. Another advantage of SCLK, RANGE,

CS

A0–A2, and
that power supply sequencing issues are avoided. If one of these
digital inputs is applied before V
as there would be on the analog inputs if a signal greater than

0.3 V were applied prior to V

V

DRIVE

The AD7266 also has the V
voltage at which the serial interface operates. V
ADC to easily interface to both 3 V and 5 V processors. For
example, if the AD7266 was operated with a V
V

pin could be powered from a 3 V supply, allowing a large

DRIVE

dynamic range with low voltage digital processors. For example,
the AD7266 could be used with the 2 × V

of 5 V while still being able to interface to 3 V digital parts.

V

DD

not being restricted by the VDD + 0.3 V limit is

, there is no risk of latch-up,

DD

.

DD

feature, which controls the

DRIVE

allows the

DRIVE

of 5 V, the

DD

input range, with a

REF

×

V

/4096

REF

– 1LSB

REF

ANALOG INPUT

+V

– 1 LSB–V

REF

011...111

011...110

000...001

000...000

111...111

ADC CODE

100...010

100...001

100...000
+ 1LSB V

REF

1LSB = 2

Figure 7. Twos Complement Transfer Characteristic with V

Range

04603-PrA-007

±V

Input

REF

REF

Rev. PrG | Page 12 of 17

Preliminary Technical Data AD7266

MODES OF OPERATION

The mode of operation of the AD7266 is selected by controlling
the (logic) state of the CS signal during a conversion. There are
three possible modes of operation: normal mode, partial power­down mode, and full power-down mode. The point at which

CS

is pulled high after the conversion has been initiated determines
which power-down mode, if any, the device enters. Similarly, if

CS

already in a power-down mode,

can control whether the
device returns to normal operation or remains in power-down.
These modes of operation are designed to provide flexible
power management options. These options can be chosen to
optimize the power dissipation/throughput rate ratio for
differing application requirements.

NORMAL MODE

This mode is intended for fastest throughput rate performance
since the user does not have to worry about any power-up times
with the AD7266 remaining fully powered all the time. Figure 8
shows the general diagram of the operation of the AD7266 in
this mode.

CS

SCLK

A

D

OUT

D

B

OUT

The conversion is initiated on the falling edge of CS, as
described in the Serial Interface section. To ensure that the part
remains fully powered up at all times,
at least 10 SCLK falling edges have elapsed after the falling edge

CS

. If CS is brought high any time after the 10th SCLK falling

of
edge but before the 14
powered up but the conversion is terminated and D

B go back into three-state. Fourteen serial clock cycles are

D

OUT

required to complete the conversion and access the conversion
result. The DOUT line does not return to three-state after 14
SCLK cycles have elapsed, but instead does so when
brought high again. If
(e.g. if only a 16 SCLK burst is available), two trailing zeros are
clocked out after the data. If
cycles again, the result from the other ADC on board is also

11014

LEADING ZERO, I.D. BIT + CONVERSION RESULT

Figure 8. Normal Mode Operation

CS

must remain low until

th

SCLK falling edge, the part remains

A and

OUT

CS

is

CS

is left low for another 2 SCLK cycles

CS

is left low for a further 16 SCLK

04603-PrA-008

accessed on the same DOUT line, as shown in Figure TBD (see
the Serial Interface section). The identification bit provided
prior to each conversion result identifies which on-board ADC
the following result is from. Once 32 SCLK cycles have elapsed,

nd

the DOUT line returns to three-state on the 32

CS

edge. If
to three-state at that point. Thus,

is brought high prior to this, the DOUT line returns

CS

may idle low after 32 SCLK

SCLK falling

cycles until it is brought high again sometime prior to the next

CS

conversion (effectively idling

low), if so desired, since the
bus still returns to three-state upon completion of the dual
result read.

Once a data transfer is complete and D

A and D

OUT

OUT

B have
returned to three-state, another conversion can be initiated after
the quiet time, t

, has elapsed by bringing CS low again.

QUIET

PARTIAL POWER-DOWN MODE

This mode is intended for use in applications where slower
throughput rates are required. Either the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate and the ADC is then
powered down for a relatively long duration between these
bursts of several conversions. When the AD7266 is in partial
power-down, all analog circuitry is powered down except for
the on-chip reference and reference buffer.

To enter partial power-down, the conversion process must be

CS

interrupted by bringing
falling edge of SCLK and before the 10
shown in Figure 9. Once
window of SCLKs, the part enters partial power-down, the
conversion that was initiated by the falling edge of
terminated, and D
CS

is brought high before the second SCLK falling edge, the

OUT

part remains in normal mode and does not power down. This
avoids accidental power-down due to glitches on the

CS

SCLK

D

OUT

D

OUT

A

B

1 2 10 14

Figure 9. Entering Partial Power-Down Mode

high anywhere after the second

th

falling edge of SCLK, as

CS

has been brought high in this

A and D

B go back into three-state. If

OUT

TRI-STATE

CS

is

CS

line.

04603-PrA-009

Rev. PrG | Page 13 of 17

AD7266 Preliminary Technical Data

To exit this mode of operation and power up the AD7266 again,
a dummy conversion is performed. On the falling edge of CS,
the device begins to power up, and continues to power up as

CS

long as

is held low until after the falling edge of the 10th
SCLK. The device is fully powered up after approximately 1 µs
has elapsed, and valid data results from the next conversion, as

CS

shown in Figure 10. If

is brought high before the second
falling edge of SCLK, the AD7266 again goes into partial power­down. This avoids accidental power-up due to glitches on the
CS

line. Although the device may begin to power up on the

CS

falling edge of
CS

. If the AD7266 is already in partial power-down mode and

CS

is brought high between the second and 10th falling edges of

, it powers down again on the rising edge of

SCLK, the device enters full power-down mode.

FULL POWER-DOWN MODE

This mode is intended for use in applications where throughput
rates slower than those in the partial power-down mode are
required, as power-up from a full power-down takes substan­tially longer than that from partial power-down. This mode is
more suited to applications where a series of conversions
performed at a relatively high throughput rate are followed by a
long period of inactivity and thus power-down. When the

THE PART BEGINS

TO POWER-UP

T

POWER-UP

AD7266 is in full power-down, all analog circuitry is powered
down. Full power-down is entered in a similar way as partial
power-down, except the timing sequence shown in Figure 9
must be executed twice. The conversion process must be

CS

interrupted in a similar fashion by bringing

high anywhere
after the second falling edge of SCLK and before the 10
edge of SCLK. The device enters partial power-down at this
point. To reach full power-down, the next conversion cycle must
be interrupted in the same way, as shown in Figure TBD. Once
CS

has been brought high in this window of SCLKs, the part

powers down completely.

Note that it is not necessary to complete the 14 SCLKs once
has been brought high to enter a power-down mode.

To exit full power-down and power the AD7266 up again, a
dummy conversion is performed, as when powering up from

CS

partial power-down. On the falling edge of

, the device

begins to power up and continues to power up as long as

th

held low until after the falling edge of the 10

SCLK. The
power-up time required must elapse before a conversion can be
initiated, as shown in Figure TBD. See the Power-Up Times
section for the power-up times associated with the AD7266.

THE PART IS FULLY POWERED UP,

SEE POWER-UP TIMES SECTION

th

falling

CS

CS

is

SCLK

D

OUT

D

OUT

CS

1

A

B

A

INVALID DATA VALID DATA

10 14 1 14

Figure 10. Exiting Partial Power-Down Mode

04603-PrA-010

Rev. PrG | Page 14 of 17

Preliminary Technical Data AD7266

SERIAL INTERFACE

Figure 11 shows the detailed timing diagram for serial
interfacing to the AD7266. The serial clock provides the
conversion clock and controls the transfer of information from
the AD7266 during conversion.

CS

signal initiates the data transfer and conversion process.

The

CS

The falling edge of

puts the track and hold into hold mode
and takes the bus out of three-state; the analog input is sampled
at this point. The conversion is also initiated at this point and
requires a minimum of 14 SCLKs to complete. Once 13 SCLK
falling edges have elapsed, the track-and-hold will go back into
track on the next SCLK rising edge, as shown in Figure 11 at
point B. If a 16 SCK transfer is used then 2 trailing zeros will

CS

appear after the final LSB. On the rising edge of
conversion will be terminated and D

CS

back into three-state. If

is not brought high but is instead

A and D

OUT

held low for a further 14 (or 16) SCLK cycles on D
from conversion B will be output on D

A (followed by 2

OUT

, the

B will go

OUT

OUT

A, the data

trailing zeros). Likewise, if CS is held low for a further 14 (or 16)
SCLK cycles on D
output on D

OUT

B, the data from conversion A will be

OUT

B. This is illustrated in Figure 12 where the case

for D

A is shown. Note that in this case, the D

OUT

will go back into three-state on the 32nd SCLK falling edge or

CS

the rising edge of

, whichever occurs first.

A minimum of fourteen serial clock cycles are required to
perform the conversion process and to access data from one
conversion on either data line of the AD7266.
provides the leading zero to be read in by the microcontroller or
DSP. The remaining data is then clocked out by subsequent
SCLK falling edges, beginning with a second leading zero. Thus
the first falling clock edge on the serial clock has the leading
zero provided and also clocks out the second leading zero. The
12 bit result then follows with the final bit in the data transfer
valid on the fourteenth falling edge, having being clocked out
on the previous (thirteenth) falling edge. In applications with a
slower SCLK, it may be possible to read in data on each SCLK
rising edge depending on the SCLK frequency used, i.e., the first

CS

rising edge of SCLK after the

falling edge would have the
leading zero provided and the thirteenth rising SCLK edge
would have DB0 provided.

line in use

OUT

CS

going low

D

D

D

OUT

+5

SCLK

OUT

OUT

+5

SCLK

A

A

3-STATE

B

3-STATE

t

2

1

t

3

0

2 Leading Zeros

t

2

1

t

3

ZERO

0

2 Leading

Zeros,

0

2

DB11

2

A

t

6

34

DB11

DB10

5

t

4

DB9 DB8

t

7

Figure 11 Serial Interface Timing Diagram

t

6

DB9

5

14

15

t

5

t

t

4

A

7

2 Traiing Zeros,

34

DB10

A

Figure 12. Reading data from Both ADCs on One D

DB2

16

17

ZERO

ZERO ZERO ZERO

2 Leading Zeros,

OUT

13

t

5

DB1

DB11

B

Line with 32 SCLKs

B

DB0

14

t

8

ZERO

2 Traiing Zeros,

3-STATE

t

10

ZERO

t

9

t

quiet

32

3-STATE

Rev. PrG | Page 15 of 17

AD7266 Preliminary Technical Data

OUTLINE DIMENSIONS

1.00

0.85

0.80

12° MAX

SEATING
PLANE

5.00

BSC SQ

PIN 1
INDICATOR

TOP

VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

4.75

BSC SQ

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

0.05 MAX

0.02 NOM

0.60 MAX

0.50

BSC

0.50

0.40

0.30

COPLANARITY

0.08

Figure 13. 32-Lead Frame Chip Scale Package [LFCSP

(CP-32)

Dimensions shown in millimeters

1.20

0.75

0.60

0.45

MAX

25

9.00 SQ

24 17

0.60 MAX

25

24

17

16

BOTTOM

VIEW

16

32

1

8

9

3.50 REF

PIN 1
INDICATOR

3.25

3.10 SQ

2.95

0.25 MIN

TOP VIEW

(PINS DOWN)

32

0.15

0.05

1.05

1.00

0.95

COMPLIANT TO JEDEC STANDARDS MS-026ABA

1

0.80

BSC

SEATING
PLANE

0.45

0.37

0.30

9

8

Figure 14. 32-Lead Thin Flat Quad Package [TQFP]

(SU-32)

Dimensions shown in millimeters

7.00
SQ

7°
0°

Rev. PrG | Page 16 of 17

Preliminary Technical Data AD7266

ORDERING GUIDE

AD7266 Products Temperature Package Package Description Package Outline

AD7266ACP –40°C to +125°C Lead Frame Chip Scale Package CP-32
AD7266BCP –40°C to +125°C Lead Frame Chip Scale Package CP-32
AD7266ASU –40°C to +125°C Thin Quad Flat Package SU-32
AD7266BSU –40°C to +125°C Thin Quad Flat Package SU-32
EVAL-AD7266CB
EVAL-CONTROL BRD2

1

2

Evaluation Board
Controller Board

1

This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL Board for evaluation/demonstration purposes.

2

This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete

evaluation kit, the particular ADC evaluation board, e.g., EVAL-AD7266CB, the EVAL-CONTROL BRD2, and a 12V transformer must be ordered. See relevant Evaluation
Board Technical note for more information.

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

PR04603–0–4/04(PrG)

Rev. PrG | Page 17 of 17