ANALOG DEVICES AD7262 Service Manual

1 MSPS, 12-Bit, Simultaneous Sampling

V

A

SAR ADC with PGA and Four Comparators

FEATURES

Dual simultaneous sampling 12-bit, 2-channel ADC True differential analog inputs Programmable gain stage: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16,

×24, ×32, ×48, ×64, ×96, ×128

Throughput rate per ADC

1 MSPS for AD7262

500 kSPS for AD7262-5 Analog input impedance: >1 GΩ Wide input bandwidth

−3 dB bandwidth: 1.7 MHz at gain = 2 4 on-chip comparators SNR: 73 dB typical at gain = 2, 66 dB typical at gain = 32 Device offset calibration, system gain calibration On-chip reference: 2.5 V –40°C to +105°C operation High speed serial interface

SPI/QSPI™/MICROWIRE™/DSP compatible

48-lead LFCSP and LQFP packages

GENERAL DESCRIPTION

The AD7262/AD7262-5 are dual, 12-bit, high speed, low power, successive approximation ADCs that operate from a single 5 V power supply. The AD7262 features throughput rates of up to 1 MSPS per on-chip ADC. The AD7262-5 features throughput rates of up to 500 kSPS. Two complete ADC functions allow simultaneous sampling and conversion of two channels. Each ADC is preceded by a true differential analog input with a PGA. There are 14 gain settings available: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16, ×24, ×32, ×48, ×64, ×96, and ×128.

The AD7262/AD7262-5 contain four comparators. Comparator A and Comparator B are optimized for low power, while Comparator C and Comparator D have fast propagation delays. The AD7262/AD7262-5 feature a calibration function to remove any device offset error and programmable gain adjust registers to allow for input path (for example, sensor) offset and gain compensation. The AD7262/AD7262-5 have an on-chip 2.5 V reference that can be disabled if an external reference is preferred.

The AD7262/AD7262-5 are ideally suited for monitoring small amplitude signals from a variety of sensors. They include all the functionality needed for monitoring the position feedback signals from a variety of analog encoders used in motor control systems.

AD7262

FUNCTIONAL BLOCK DIAGRAM

V

CC

VA+

V

REF

C

A_CBVCC

C

CA_CB_GND

C

C_CDVCC

C

CC_CD_GND

A

B

A

B

C

D

–

+

–

+

–

+

–

+

–

+

–

REF

PGA T/H

PGA

COMP

BUF

T/H

BUF

OUTPUT

DRIVERS

COMP

OUTPUT

DRIVERS

COMP

AGND DGND

PRODUCT HIGHLIGHTS

1. Integrated PGA with a variety of flexible gain settings to

allow detection and conversion of low level analog signals.

2. Each PGA is followed by a dual simultaneous sampling

ADC, featuring throughput rates of 1 MSPS per ADC for the AD7262. The conversion results of both ADCs are simultaneously available on separate data lines or in succession on one data line if only one serial port is available.

3. Four integrated comparators that can be used to count

signals from pole sensors in motor control applications.

4. Internal 2.5 V reference.

A

REF

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

CONTRO L

LOGIC

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

OUTPUT DRIVERS

Figure 1.

AD7262

OUTPUT

DRIVERS

OUTPUT

DRIVERS

D

OUT

SCLK CAL CS

REFSEL G0 G1 G2 G3 V

DRIVE

D

OUT

PD0/D PD1 PD2

C

OUT

C

OUT

C

OUT

C

OUT

A

B

IN

A

B

C

D

07606-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD7262

REVISION HISTORY

7/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

AD7262

SPECIFICATIONS

AVCC = 4.75 V to 5.25 V, CA_CBVCC = CC_CDVCC = 2.7 V to 5.25 V, V for AD7262, f

= 500 kSPS and f

SAMPLE

= 20 MHz for AD7262-5, V

SCLK

otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio (SNR) Signal-to-(Noise + Distortion) Ratio

(SINAD)

2

Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Common-Mode Rejection Ratio (CMRR)

ADC-to-ADC Isolation Bandwidth

3

1.2 MHz @ −3 dB; PGA gain setting = 128

1

2

f 70 73 dB PGA gain setting = 2 70 72 dB

2

−85 −77 dB

2

−97 dB

3

−76 dB

3

−90 dB

1.7 MHz @ −3 dB; PGA gain setting = 2 DC ACCURACY

Resolution 12 Bits Integral Nonlinearity Differential Nonlinearity Positive Full-Scale Error

2

±0.5 ±1 LSB

2

±0.5 ±0.99 LSB Guaranteed no missed codes to 12 bits

2

±0.122 ±0.305 % FSR Pregain calibration

±0.018 % FSR Postgain calibration Positive Full-Scale Error Match ±0.061 % FSR Zero Code Error

2

±0.092 ±0.244 % FSR Preoffset and pregain calibration

±0.012 % FSR Postoffset and postgain calibration Zero Code Error Match ±0.061 % FSR Negative Full-Scale Error

2

±0.122 ±0.305 % FSR Pregain calibration

±0.018 % FSR Postgain calibration Negative Full-Scale Error Match ±0.061 % FSR Zero Code Error Drift 2.5 µV/°C

ANALOG INPUT

Input Voltage Range, VIN+ and VIN−

V

±

CM

Common-Mode Voltage Range, VCM V

− 100 mV VCM + 100 mV V

CM

(VCC/2) − 0.4 (VCC/2) + 0.2 V VCM = AVCC/2; PGA gain setting = 2 (VCC/2) − 0.4 (VCC/2) + 0.4 V VCM = AVCC/2; 3 ≤ PGA gain setting ≤ 32 (VCC/2) − 0.6 (VCC/2) + 0.8 V VCM = AVCC/2; PGA gain setting ≥ 48 DC Leakage Current ±0.001 ±1 µA Input Capacitance Input Impedance

3

5 pF

3

1 GΩ

REFERENCE INPUT/OUTPUT

Reference Output Voltage

5

2.495 2.5 2.505 V 2.5 V ± 5 mV max @ 25°C Reference Input Voltage Range 2.5 V DC Leakage Current ±0.3 ±1 µA

Input Capacitance V

A, V

REF

B Output Impedance

REF

3

20 pF

3

4 Ω

Reference Temperature Coefficient 20 ppm/°C V

REF

3

Noise

20 µV rms

= 2.7 V to 5.25 V, f

DRIVE

= 2.5 V internal/external; TA = −40°C to +105°C, unless

REF

= 1 MSPS and f

SAMPLE

IN

= 40 MHz

SCLK

= 100 kHz sine wave

For PGA gain setting = 2, ripple frequency of 50 Hz/60 Hz; see Figure 17 and Figure 18

V

REF

Gain2

×

V VCM = AVCC/2; PGA gain setting ≥ 2

= 2; PGA gain setting = 1;

V

CM

see Figure 19

4

External reference applied to Pin V

A/Pin V

REF

B

Rev. 0 | Page 3 of 32

AD7262

Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, IIN ±1 µA VIN = 0 V or V Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, VOH V Output Low Voltage, VOL 0.4 V Floating State Leakage Current ±1 µA Floating State Output Capacitance Output Coding Twos complement

CONVERSION RATE

Conversion Time 19 × t Track-and-Hold Acquisition Time 400 ns Throughput Rate 1 MSPS AD7262 500 kSPS AD7262-5

COMPARATORS

Input Offset

Comparator A and Comparator B ±2 ±4 mV TA = 25°C to 105°C only

Comparator C and Comparator D ±2 ±4 mV Offset Voltage Drift 0.5 V/°C All comparators Input Common-Mode Range 0 to 1.7 V CA_CBVCC = 2.7 V Input Capacitance Input Impedance IDD Normal Mode (Static)

Comparator A and Comparator B 3 µA CA_CBVCC = 3.3 V

6 8.5 µA CA_CBVCC = 5.25 V

Comparator C and Comparator D 60 µA CC_CDVCC = 3.3 V

120 170 µA CC_CDVCC = 5.25 V Propagation Delay Time

High to Low, t

Comparator A and Comparator B 1.4 3.5 µs CA_CBVCC = 2.7 V

0.95 µs CA_CBVCC = 5 V Comparator C and Comparator D 0.20 0.32 µs CC_CDVCC = 2.7 V

0.13 µs CC_CDVCC = 5 V

Low to High, t

Comparator A and Comparator B 2 4 µs CA_CBVCC = 2.7 V

0.93 µs CA_CBVCC = 5 V Comparator C and Comparator D 0.18 0.28 µs CC_CDVCC = 2.7 V

0.12 µs CC_CDVCC = 5 V

Delay Matching

Comparator A and Comparator B ±250 ns

Comparator C and Comparator D ±10 ns

0.7 × V

INH

0.8 V

INL

3

IN

3

0 to 4 V C

3

4 pF

3

1 GΩ

6

4 pF

DRIVE

5 pF

V

DRIVE

− 0.2 V

ns

SCLK

= 5 V

A_CBVCC

25 pF load, C V

V

= 200 mV differential

OVERDRIVE

= AVCC/2, V

CM

DRIVE

x = 0 V, VCM = AVCC/2,

OUT

OVERDRIVE

differential

PHL

PLH

= AVCC 2, V

V

CM

OVERDRIVE

differential

= 200 mV

Rev. 0 | Page 4 of 32

AD7262

Parameter Min Typ Max Unit Test Conditions/Comments

POWER REQUIREMENTS Digital inputs = 0 V or V

AVCC 4.75 5.25 V CA_CBVCC, CC_CDVCC 2.7 5.25 V V

2.7 5.25 V

DRIVE

IDD

ADC Normal Mode (Static) 20 31.5 mA AVCC = 5.25 V ADC Normal Mode (Dynamic) 23 33.3 mA AVCC = 5.25 V Shutdown Mode 0.5 1 A

= 5.25 V, ADCs and comparators

AV

CC

powered down

Power Dissipation

ADC Normal Mode (Static) 105 165 mW ADC Normal Mode (Dynamic) 120 175 mW Shutdown Mode 2.625 5.25 µW

1

These specifications were determined without the use of the gain calibration feature.

2

See the Terminology section.

3

Samples tested during initial release to ensure compliance; they are not subject to production testing.

4

For PGA gain = 1; to use the full analog input range (VCM ± V

5

Refers to Pin V

6

This specification includes the IDD for both comparators. The IDD per comparator is the specified value divided by two.

A or Pin V

REF

B.

REF

/2) of the AD7262, the VCM voltage should be dropped to lie within a range from 1.95 V to 2.05 V.

REF

DRIVE

Rev. 0 | Page 5 of 32

AD7262

TIMING SPECIFICATIONS

AVCC = 4.75 V to 5.25 V, CA_CBVCC = CC_CDVCC = 2.7 V to 5.25 V, V

Table 2.

Limit at T Parameter 2.7 V ≤ V

f

200 200 kHz min

SCLK

t

CONVER T

t

13 13 ns min

QUIET

t

2

3

t

3

t

29 23 ns max Data access time after SCLK falling edge

4

t

5

t

6

40 40 MHz max AD7262 32 32 MHz typ AD7262 20 20 MHz max AD7262-5 19 × t 475 475 ns max AD7262 950 950 ns max AD7262-5

10 10 ns min 15 15 ns max

15 13 ns min SCLK to data valid hold time

0.4 × t

t7 0.4 × t

≤ 3.6 V 4.75 V ≤ V

DRIVE

19 × t

SCLK

0.4 × t

SCLK

, T

MIN

0.4 × t

MAX

≤ 5.25 V Unit Description

DRIVE

ns max t

SCLK

ns min SCLK high pulse width

SCLK

t8 13 13 ns min t

9

t

10

13 13 ns max

5 5 ns min SCLK falling edge to D

35 35 ns max SCLK falling edge to D t11 2 2 s min Minimum CAL pin high time t12 2 2 s min

t13 3 3 ns min DIN setup time prior to SCLK falling edge t14 3 3 ns min DIN hold time after SCLK falling edge t

240 240 s max Internal reference, with a 1 F decoupling capacitor

POWER-UP

15 15 s max With an external reference, 10 s typical

1

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of AVCC) and timed from a voltage level of 1.6 V.

All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the Terminology section.

2

See the Serial Interface section.

3

The time required for the output to cross 0.4 V or 2.4 V.

= 2.5 V internal/external; TA = T

REF

2

SCLK

= 1/f

SCLK

Minimum time between end of serial read/bus relinquish and next falling edge of CS

to SCLK setup time

CS

th

Delay from 19

SCLK falling edge until D

three-state disabled

ns min SCLK low pulse width

rising edge to falling edge pulse width

CS

rising edge to D

CS

OUT

relinquish

Minimum time between the CAL pin high and the CS falling edge

to T

MIN

A, D

OUT

A, D A, D

, unless otherwise noted.1

MAX

B, high impedance/bus

OUT

B, high impedance

OUT

B, high impedance

OUT

A and D

OUT

B are

TIMING DIAGRAM

CS

SCLK

D

OUT

D

OUT

A

B

1519

t

2

234 20

THREE-STAT E

18

t

3

Figure 2. Serial Interface Timing Diagram

Rev. 0 | Page 6 of 32

DB11

t

8

t

6

21 29 30 31

t

7

t

4

DB9

DB10

A

DB9

DB10

B

t

5

A

B

DB1

A

B

DB0

t

9

t

QUIET

A

THREESTATE

B

THREESTATE

07606-002

AD7262

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

V

to DGND −0.3 V to AVCC

DRIVE

V

to AGND −0.3 V to AVCC

DRIVE

AVCC to AGND/DGND −0.3 V to +7 V CA_CBVCC to CA_CB_GND −0.3 V to +7 V CC_CDVCC to CC_CD_GND −0.3 V to +7 V AGND to DGND −0.3 V to +0.3 V CA_CB_GND/CC_CD_GND to DGND −0.3 V to +0.3 V Analog Input Voltage to AGND −0.3 V to AVCC + 0.3 V Digital Input Voltage to DGND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to V V

A/V

REF

C

OUT

CA±/CB±/CC±/CD± to

B Input to AGND −0.3 V to AVCC + 0.3 V

REF

A/C

B/C

C/C

OUT

D to GND −0.3 V to V

OUT

−0.3 V to

_GND/CC_CD_GND

C

A_CB

CA_CBVCC/CC_CDVCC + 0.3 V

DRIVE

+ 0.3 V

Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C LFCSP Package

θJA Thermal Impedance 30°C/W θJC Thermal Impedance 3°C/W

LQFP Package

θJA Thermal Impedance 55°C/W θJC Thermal Impedance 16°C/W

Pb-Free Temperature, Soldering

Reflow 255°C

ESD 2 kV

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. 0 | Page 7 of 32

AD7262

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

_GND

B

A

CC

_C

A

REF

AV

AGND

C

V

42

434445

B

CC

REF

AV

_GND

AGND

V

D

_C

C

37G338G239G140G041

36

CAL

35

CS

34

SCLK

33

AV

CC

32

D

A

OUT

31

D

B

OUT

30

C

A

OUT

C

B

29

OUT

DGND

28

27

V

DRIVE

26

C

OUT

25

C

D

OUT

IN

PD2

PD1

PD0/D

REFSEL

7606-003

CA_CBV

CC_CDV

NOTES

1. THE EXPOSED METAL PADDLE ON THE BOTTOM OF THE L FCSP PACKAGE MUST BE SOLDERED T O PCB GROUND F OR PROPER HEAT DISSIPATION AND ALSO FOR NOISE AND MECHANICAL STRENGT H BENEFITS.

AV

VA– V

AGND AGND

AV

AGND

V

VB–

AV

1

CC

2

CC

3

+

4

A

5 6

7

CC

8

+

9

B

10 11

CC

12

CC

CA_CBV

AGND

CC_CDV

AV

–

+

–

+

B

A

C

46

47

48

1

VA–

V

VB–

CC

+

A

CC

+

B

CC

PIN 1

2

INDICATO R

3 4 5 6 7 8 9

10

11

12

13 15 16 17 18 19 20 21 22 23 24

14

+

C

–

C

AD7262

TOP VIEW

(Not to Scale)

–

+

D

C

Figure 3. 48-Lead LQFP Pin Configuration Figure 4. 48-Lead LFCSP Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

2, 7, 11, 20, 33, 41 AVCC

Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the analog circuitry on the AD7262/AD7262-5. All AV

pins can be tied together. This supply should be decoupled to AGND

CC

with a 100 nF ceramic capacitor per supply and a 10 F tantalum capacitor.

1 CA_CBVCC

Comparator Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for Comparator A and Comparator B. This supply should be decoupled to C tied together.

12 C

C_CDVCC

Comparator Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for Comparator C and Comparator D. This supply should be decoupled to C

tied together. 4, 3 VA+, VA− Analog Inputs of ADC A. True differential input pair. 9, 10 V 43, 18 V

+, VB− Analog Inputs of ADC B. True differential input pair.

B

A, V

REF

B

Reference Input/Output. Decoupling capacitors are connected to these pins to decouple the

internal reference buffer for each respective ADC. Typically, 1 F capacitors are required to decouple

the reference. Provided the output is buffered, the on-chip reference can be taken from these pins

and applied externally to the rest of a system. 34 SCLK

Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the

AD7262/AD7262-5. This clock is also used as the clock source for the conversion process. A

minimum of 31 clocks is required to perform the conversion and access the 12-bit result. 36 CAL 21 PD2

Logic Input. Initiates an internal offset calibration.

Logic Input. Places the AD7262/AD7262-5 in selected shutdown mode in conjunction with the PD1

and PD0 pins (see Table 7). 22 PD1

Logic Input. Places the AD7262/AD7262-5 in selected shutdown mode in conjunction with the PD2

and PD0 pins (see Table 7).

_GND

B

A

–

+

–

+

A

C

4847464544434241403938

13141516171819

+

C

A_CB

C_CD

_C

B

A

REF

C

PIN 1 INDICAT OR

–

+

C

D

C

V

AD7262

TOP VIEW

(Not to Scale)

–

B

D

C

REF

_GND

AGND

V

D

_C

C

AVCCAGND

2021222324

CC

AV

G0

PD2

G1

PD1

G3

G2

37

CAL

36

CS

35

SCLK

34

AV

33

D

32

D

31

C

30

C

29

DGND

28

V

27

C

26

C

25

IN

PD0/D

REFSEL

_GND. AVCC, CC_CDVCC, and CA_CBVCC can be

CC

OUT

DRIVE

OUT

A

B

A

B

C

D

07606-004

Rev. 0 | Page 8 of 32

AD7262

Pin No. Mnemonic Description

23 PD0/DIN

35 48, 47, 46, 45

13, 14, 15, 16

CS

+, CA−,

C

A

+, CB−

C

B

+, CC−,

C

+, CD−

C

D

5, 6, 8, 19, 42 AGND

28 DGND

30, 29, 26, 25

32, 31 D

A, C

C

OUT

C, C

C

OUT

A, D

OUT

40, 39, 38, 37 G0, G1, G2, G3

27 V

44, 17

C C

DRIVE

A_CB

C_CD

_GND, _GND

24 REFSEL

Logic Input/Data Input. Places the AD7262/AD7262-5 in selected shutdown mode in conjunction with the PD2 and PD1 pins (see Table 7). If all gain selection pins, G0 to G3, are tied low, this pin acts as the data input pin, and all programming is via the control register (see Table 8). Data to be written to the AD7262/AD7262-5 control register is provided on this input and is clocked into the register on the falling edge of SCLK.

Chip Select. Active low logic input. This input initiates conversions on the AD7262/AD7262-5. Comparator Inputs. These pins are the inverting and noninverting analog inputs for Comparator A

and Comparator B. These two comparators have very low power consumption. Comparator Inputs. These pins are the inverting and noninverting analog inputs for Comparator C

and Comparator D. This pair of comparators offers very fast propagation delays. Analog Ground. Ground reference point for all analog circuitry on the AD7262/AD7262-5. All

analog input signals and any external reference signal should be referred to this AGND voltage. All AGND pins should connect to the AGND plane of a system. The AGND, DGND, C C

_GND voltages ideally should be at the same potential and must not be more than 0.3 V apart,

C_CD

even on a transient basis. C

_GND and CC_CD_GND can be tied to AGND.

A_CB

Digital Ground. This is the ground reference point for all digital circuitry on the AD7262/AD7262-5. The DGND pin should be connected to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

Comparator Outputs. These pins provide a CMOS (push-pull) output from each respective

B, D

comparator. These are digital output pins with logic levels determined by the V

B

Serial Data Outputs. The data output from the AD7262/AD7262-5 is supplied to each pin as a serial

DRIVE

supply.

data stream in twos complement format. The bits are clocked out on the falling edge of the SCLK input. A total of 31 SCLKs is required to perform the conversion and access the 12-bit data. During the conversion process, the data output pins are in three-state and, when the conversion is completed, the 19

th

SCLK edge clocks out the MSB. The data simultaneously appears on both pins from the simultaneous conversions of both ADCs. The data is provided MSB first. If CS an additional 12 SCLK cycles on either D the other ADC follows on the D

pin. This allows data from a simultaneous conversion on both

OUT

ADCs to be gathered in serial format on either D

OUT

A or D

B following the initial 31 SCLKs, the data from

OUT

A or D

B using only one serial port.

OUT

Logic Inputs. These pins are used to program the gain setting of the front-end amplifiers. If all four pins are tied low, the PD0 pin acts as a data input pin, DIN, and all programming is made via the control register (see Table 6 ).

Logic Power Supply Input, 2.7 V to 5.25 V. The voltage supplied at this pin determines at what voltage the interface operates, including the comparator outputs. This pin should be decoupled to DGND.

Comparator Ground. This is the ground reference point for all comparator circuitry on the AD7262/ AD7262-5. Both the CA_CB_GND pin and the CC_CD_GND pin should connect to the GND plane of a system and can be tied to AGND. The DGND, AGND, C

_GND, and CC_CD_GND voltages should

A_CB

ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Internal/External Reference Selection. Logic input. If this pin is tied to a logic high voltage, the on-

chip 2.5 V reference is used as the reference source for both ADC A and ADC B. If the REFSEL pin is tied to GND, an external reference can be supplied to the AD7262/AD7262-5 through the V and/or V

REF

B pin.

_GND, and

is held low for

A

REF

Rev. 0 | Page 9 of 32

AD7262

TYPICAL PERFORMANCE CHARACTERISTICS

0.6 AVCC = 5V

V

= 5V

DRIVE

f

= 1MSPS

S

0.4 T

= 25°C

A

INTERNAL REFERENCE PGA GAIN = 2

0.2

0.6 AVCC = 5V

V

= 5V

DRIVE

f

= 1MSPS

S

0.4 T

= 25°C

A

INTERNAL REFERENCE PGA GAIN = 32

0.2

0

–0.2

DNL ERRO R (LSB)

–0.4

–0.6

0400035003000250020001 5001000500

1.0

0.8

0.6

0.4

0.2

0

–0.2

INL ERROR (LS B)

–0.4

AVCC = 5V V

DRIVE

–0.6

f

= 1MSPS

S

T

= 25°C

A

–0.8

INTERNAL REFERENCE PGA GAIN = 2

–1.0

0400035003000250020001 5001000500

CODE

Figure 5. Typical DNL at Gain of 2

= 5V

CODE

Figure 6. Typical INL at Gain of 2

0

–0.2

DNL ERRO R (LSB)

–0.4

–0.6

0435003000250020001 5001000500

07606-005

CODE

000

07606-008

Figure 8. Typical DNL at Gain of 32

1.0

0.8

0.6

0.4

0.2

0

–0.2

INL ERROR (LS B)

–0.4

AVCC = 5V V

= 5V

DRIVE

–0.6

f

= 1MSPS

S

T

= 25°C

A

–0.8

INTERNAL REFERENCE PGA GAIN = 32

–1.0

0435003000250020001 5001000500

07606-006

CODE

000

07606-009

Figure 9. Typical INL at Gain of 32

0

–20

–40

–60

(dB)

–80

–100

–120

–140

0 400k 450k350k300k250k200k150k100k50k

FREQUENCY (Hz)

AVCC = 5V V

= 2.7V

DRIVE

f

= 1MSPS

S

T

= 25°C

A

f

= 100kHz

IN

INTERNAL REFERENCE SNR = 73dB, T HD = –82.5dB PGA GAIN = 2

07606-007

Figure 7. 3 dB Typical FFT at Gain of 2

0

–20

–40

–60

(dB)

–80

–100

–120

–140

0 400k 450k 500k350k300k250k200k150k100k50k

AVCC = 5V V

= 5V

DRIVE

f

= 1MSPS

S

T

= 25°C

A

f

= 100kHz

IN

INTERNAL REFERENCE SNR = 68.38dB, THD = –82dB PGA GAIN = 32

FREQUENCY (Hz)

07606-010

Figure 10. Typical FFT at Gain of 32

Rev. 0 | Page 10 of 32

ANALOG DEVICES AD7262 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING SPECIFICATIONS

TIMING DIAGRAM

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS