Analog Devices AD7226TQ, AD7226TE, AD7226KR, AD7226KP, AD7226KN Datasheet
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REV. A
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a
LC2MOS
Quad 8-Bit D/A Converter
AD7226
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Four 8-Bit DACs with Output Amplifiers
Skinny 20-Pin DIP, SOIC and 20-Terminal
Surface Mount Packages
Microprocessor Compatible
TTL/CMOS Compatible
No User Trims
Extended Temperature Range Operation
Single Supply Operation Possible
APPLICATIONS
Process Control
Automatic Test Equipment
Automatic Calibration of Large System Parameters,
e.g., Gain/Offset
PRODUCT HIGHLIGHTS
1. DAC-to-DAC Matching
Since all four DACs are fabricated on the same chip at the
same time, precise matching and tracking between the DACs
is inherent.
2. Single Supply Operation
The voltage mode configuration of the DACs allows the
AD7226 to be operated from a single power supply rail.
3. Microprocessor Compatibility
The AD7226 has a common 8-bit data bus with individual
DAC latches, providing a versatile control architecture for
simple interface to microprocessors. All latch enable signals
are level triggered.
4. Small Size
Combining four DACs and four op amps plus interface logic
into a 20-pin DIP or SOIC or a 20-terminal surface mount
package allows a dramatic reduction in board space requirements and offers increased reliability in systems using multiple converters. Its pinout is aimed at optimizing board
layout with all the analog inputs and outputs at one end of the
package and all the digital inputs at the other.
GENERAL DESCRIPTION
The AD7226 contains four 8-bit voltage-output digital-toanalog converters, with output buffer amplifiers and interface
logic on a single monolithic chip. No external trims are required
to achieve full specified performance for the part.
Separate on-chip latches are provided for each of the four D/A
converters. Data is transferred into one of these data latches
through a common 8-bit TTL/CMOS (5 V) compatible input
port. Control inputs A0 and A1 determine which DAC is loaded
when
WR goes low. The control logic is speed-compatible with
most 8-bit microprocessors.
Each D/A converter includes an output buffer amplifier capable
of driving up to 5 mA of output current. The amplifiers’ offsets
are laser-trimmed during manufacture, thereby eliminating any
requirement for offset nulling.
Specified performance is guaranteed for input reference voltages
from +2 V to +12.5 V with dual supplies. The part is also specified for single supply operation at a reference of +10 V.
The AD7226 is fabricated in an all ion-implanted high speed
Linear Compatible CMOS (LC
2
MOS) process which has been
specifically developed to allow high speed digital logic circuits
and precision analog circuits to be integrated on the same chip.
REV. A
–2–
AD7226–SPECIFICA TIONS
DUAL SUPPLY
Parameter K, B, T Versions
2
Units Conditions/Comments
STATIC PERFORMANCE
Resolution 8 Bits
Total Unadjusted Error ±2 LSB max V
DD
= +15 V ± 5%, V
REF
= +10 V
Relative Accuracy ±1 LSB max
Differential Nonlinearity ±1 LSB max Guaranteed Monotonic
Full Scale Error ±1 1/2 LSB max
Full Scale Temperature Coefficient ±20 ppm/°C typ V
DD
= 14 V to 16.5 V, V
REF
= +10 V
Zero Code Error ±30 mV max
Zero Code Error Temperature Coefficient ±50 µV/°C typ
REFERENCE INPUT
Voltage Range 2 to (V
DD
– 4) V min to V max
Input Resistance 2 kΩ min
Input Capacitance
3
65 pF min Occurs when each DAC is loaded with all 0s.
300 pF max Occurs when each DAC is loaded with all 1s.
DIGITAL INPUTS
Input High Voltage, V
INH
2.4 V min
Input Low Voltage, V
INL
0.8 V max
Input Leakage Current ±1 µA max VIN = 0 V or V
DD
Input Capacitance 8 pF max
Input Coding Binary
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
4
2.5 V/µs min
Voltage Output Settling Time
4
Positive Full Scale Change 5 µs max V
REF
= +10 V; Settling Time to ±1/2 LSB
Negative Full Scale Change 7 µs max V
REF
= +10 V; Settling Time to ±1/2 LSB
Digital Crosstalk 50 nV secs typ
Minimum Load Resistance 2 kΩ min V
OUT
= +10 V
POWER SUPPLIES
VDD Range 11.4/16.5 V min/V max For Specified Performance
I
DD
13 mA max Outputs Unloaded; VIN = V
INL
or V
INH
I
SS
11 mA max Outputs Unloaded; VIN = V
INL
or V
INH
SWITCHING CHARACTERISTICS
4, 5
Address to Write Setup Time, t
AS
@ 25°C 0 ns min
T
MIN
to T
MAX
0 ns min
Address to Write Hold Time, t
AH
@ 25°C 10 ns min
T
MIN
to T
MAX
10 ns min
Data Valid to Write Setup Time, t
DS
@ 25°C 90 ns min
T
MIN
to T
MAX
100 ns min
Data Valid to Write Hold Time, t
DH
@ 25°C 10 ns min
T
MIN
to T
MAX
10 ns min
Write Pulse Width, t
WR
@ 25°C 150 ns min
T
MIN
to T
MAX
200 ns min
NOTES
1
Maximum possible reference voltage.
2
Temperature ranges are as follows:
K Version: –40°C to +85°C
B Version: –40°C to +85°C
T Version: –55°C to +125°C
3
Guanteed by design. Not production tested.
4
Sample Tested at 25°C to ensure compliance.
5
Switching Characteristics apply for single and dual supply operation.
Specifications subject to change without notice.
(VDD = 11.4 V to 16.5 V, VSS = –5 V 6 10%; AGND = DGND = O V; V
REF
= +2 V to (VDD – 4 V)1 unless otherwise noted.
All specifications T
MIN
to T
MAX
unless otherwise noted.)
AD7226
REV. A
–3–
ORDERING GUIDE
Total
Temperature Unadjusted Package
Model
1
Range Error Option
2
AD7226KN –40°C to +85°C ±2 LSB N-20
AD7226KP –40°C to +85°C ±2 LSB P-20A
AD7226KR –40°C to +85°C ±2 LSB R-20
AD7226BQ –40°C to +85°C ±2 LSB Q-20
AD7226TQ –55 °C to +125°C ±2 LSB Q-20
AD7226TE –55°C to +125°C ±2 LSB E-20A
NOTES
1
To order MIL-STD-883, Class B processed parts, add /883B to part number.
Contact your local sales office for Military data sheet, for U.S. Standard Military
Drawing (SMD), see DESC drawing #5962–87802.
2
E = Leadless Ceramic Chip Carrier; N = Plastic DIP;
P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.
SINGLE SUPPLY
Parameter K, B, T Versions
2
Units Conditions/Comments
STATIC PERFORMANCE
Resolution 8 Bits
Total Unadjusted Error ±2 LSB max
Differential Nonlinearity ±1 LSB max Guaranteed Monotonic
REFERENCE INPUT
Input Resistance 2 kΩ min
Input Capacitance
3
65 pF min Occurs when each DAC is loaded with all 0s.
300 pF max Occurs when each DAC is loaded with all 1s.
DIGITAL INPUTS
Input High Voltage, V
INH
2.4 V min
Input Low Voltage, V
INL
0.8 V max
Input Leakage Current ±1 µA max VIN = 0 V or V
DD
Input Capacitance 8 pF max
Input Coding Binary
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
4
2V/µs min
Voltage Output Settling Time
4
Positive Full Scale Change 5 µs max Settling Time to ±1/2 LSB
Negative Full Scale Change 20 µs max Settling Time to ±1/2 LSB
Digital Crosstalk 50 nV secs typ
Minimum Load Resistance 2 kΩ min V
OUT
= +10 V
POWER SUPPLIES
VDD Range 14.25/15.75 V min/V max For Specified Performance
I
DD
13 mA max Outputs Unloaded; VIN = V
INL
or V
INH
NOTES
1
Maximum possible reference voltage.
2
Temperature ranges are as follows:
K Version: –40°C to +85°C
B Version: –40°C to +85°C
T Version: –55°C to +125°C
3
Guanteed by design. Not production tested.
4
Sample Tested at 25°C to ensure compliance.
5
Switching Characteristics apply for single and dual supply operation.
Specifications subject to change without notice.
(VDD = +15 V 6 5%; VSS = AGND = DGND = O V; V
REF
= +10 V1 unless otherwise noted.
All specifications T
MIN
to T
MAX
unless otherwise noted.)
AD7226
REV. A
–4–
ABSOLUTE MAXIMUM RATINGS*
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +17 V
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +17 V
V
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–7 V, V
DD
VSS to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–7 V, V
DD
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +24 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD + 0.3 V
V
REF
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
V
OUT
to AGND1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, V
DD
Power Dissipation (Any Package) to +75°C . . . . . . . . 500 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 2.0 mW/°C
Operating Temperature
Commercial (K Version) . . . . . . . . . . . . . . –40°C to +85°C
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
NOTES
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
1
Outputs may be shorted to AGND provided that the power dissipation of the
package is not exceeded. Typically short circuit current to AGND is 60 mA.
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7226 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATIONS
DIP and SOIC LCCC PLCC
TERMINOLOGY
TOTAL UNADJUSTED ERROR
This is a comprehensive specification which includes full-scale
error, relative accuracy and zero code error. Maximum output
voltage is V
REF
– 1 LSB (ideal), where 1 LSB (ideal) is V
REF
/
256. The LSB size will vary over the V
REF
range. Hence the zero
code error will, relative to the LSB size, increase as V
REF
decreases. Accordingly, the total unadjusted error, which includes
the zero code error, will also vary in terms of LSB’s over the
V
REF
range. As a result, total unadjusted error is specified for a
fixed reference voltage of +10 V.
RELATIVE ACCURACY
Relative Accuracy or endpoint nonlinearity, is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after allowing for zero and full-scale error and is normally expressed in
LSB’s or as a percentage of full-scale reading.
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB max over
the operating temperature range ensures monotonicity.
DIGITAL CROSSTALK
The glitch impulse transferred to the output of one converter
due to a change in the digital input code to another of the converters. It is specified in nV secs and is measured at V
REF
= 0 V.
FULL SCALE ERROR
Full-Scale Error is defined as:
Measured Value – Zero Code Error – Ideal Value
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