Analog Devices AD722 Datasheet

a

RGB to NTSC/PAL Encoder

AD722

FEATURES
Low Cost, Integrated Solution
+5 V Operation
Accepts FSC Clock or Crystal, or 4FSC Clock
Composite Video and Separate Y/C (S-Video) Outputs
Minimal External Components:

No External Filters or Delay Lines Required
Onboard DC Restoration
Accepts Either HSYNC & VSYNC or CSYNC

Phase Lock to External Subcarrier
Drives 75 Ω Reverse-Terminated Loads
Logic Selectable NTSC or PAL Encoding Modes
Compact 16-Pin SOIC

APPLICATIONS
RGB to NTSC or PAL Encoding

PRODUCT DESCRIPTION

The AD722 is a low cost RGB to NTSC/PAL Encoder that
converts red, green and blue color component signals into their
corresponding luminance (baseband amplitude) and chromi­nance (subcarrier amplitude and phase) signals in accordance
with either NTSC or PAL standards. These two outputs are
also combined to provide composite video output. All three out­puts can simultaneously drive 75 Ω, reverse-terminated cables.
All logical inputs are CMOS compatible. The chip operates
from a single +5 V supply. No external delay lines or filters are
required. The AD722 may be powered down when not in use.

The AD722 accepts either FSC or 4FSC clock. When a clock is
not available, a low cost parallel-resonant crystal (3.58 MHz
(NTSC) or 4.43 MHz (PAL)) and the AD722’s on-chip oscilla­tor generate the necessary subcarrier clock. The AD722 also ac­cepts the subcarrier clock from an external video source.

The interface to VGA Controllers and MPEG Video Decoders
is simple: an on-chip logic “XNOR” accepts the available verti­cal (VSYNC) and horizontal sync (HSYNC) signals and creates
the composite sync (CSYNC) signal on-chip. If available, the
AD722 will also accept a standard CSYNC signal by connecting
VSYNC to +5 V and applying CSYNC to HSYNC pin. The
AD722 contains decoding logic to identify valid HSYNC pulses
for correct burst insertion.

Delays in the U and V chroma filters are matched by an on-chip
sampled-data delay line in the Y signal path. To prevent
aliasing, a prefilter at 5 MHz is included ahead of the delay line
and a post-filter at 5 MHz is added after the delay line to sup­press harmonics in the output. These low-pass filters are opti­mized for minimum pulse overshoot. The overall luma delay,
relative to chroma, has been designed to be 170 ns, which
precompensates for delays in the filters used in the IF section of
a television receiver. This precompensation delay is already
present in TV broadcasts. The AD722 comes in a space-saving
SOIC and is specified for the 0°C to +70°C commercial tem­perature range.

FUNCTIONAL BLOCK DIAGRAM

PHASE

SUB-

CARRIER

NTSC/PAL

HSYNC
VSYNC

FSC

4FSC

RED

GREEN

BLUE

4FSC

4FSC

XNOR

XNOR

CLAMP

CLAMP

CLAMP

SEPARATOR

CSYNC

QUADRATURE

DECODER

DC

DC

DC

XOSC

XOSC

SYNC

+4

RGB-TO-YUV

ENCODING

MATRIX

DETECTOR

BURST

CHARGE

CHARGE

FSC

BURST

FSC 90

FSC 0

°

Y 3-POLE

LP PRE-

U

V

PUMP

PUMP

°

FILTER

4-POLE

LPF

4-POLE

LPF

FILTER

FILTER

LOOP

LOOP

NTSC/PAL

±180°

(PAL ONLY)

U

CLAMP

V

CLAMP

CSYNC

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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

4FSC

4FSC

VCO

VCO

SC 90

°

/270

°

NTSC/PAL

CLOCK

AT 4FSC

CSYNC

INSERTION

BALANCED

MODULATORS

SAMPLED-

DATA

DELAY

LINE

2-POLE

LP POST-

FILTER

NTSC/PAL

3-POLE LPF

3.6MHz (NTSC)

4.4MHz (PAL)

X2

X2

X2

LUMINANCE
OUTPUT

COMPOSITE
OUTPUT

CHROMINANCE
OUTPUT

© Analog Devices, Inc., 1995

One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

(Unless otherwise noted, VS = +5, TA = +25°C, using FSC synchronous clock. All loads are

AD722–SPECIFICATIONS

150 Ω ± 5% at the IC pins. Outputs are measured at the 75 Ω reverse terminated load.)

Parameter Conditions Min Typ Max Units

SIGNAL INPUTS (RDIN, GRIN, BLIN)

Input Amplitude NTSC 714 mV p-p

PAL 700 mV p-p
Black Level 03V
Input Resistance

1

Red, Green, Blue 1 MΩ
Input Capacitance 5pF

LOGIC INPUTS (SYNC, FSC, ENCD, NTSC) CMOS Logic Levels

Logic LO Input Voltage 1V
Logic HI Input Voltage 4 V
Logic LO Input Current (DC) <1 µA
Logic HI Input Current (DC) <1 µA

VIDEO OUTPUTS

2

Luminance (LUMA)

Roll-off @ 5 MHz NTSC –10 dB

PAL –7 dB

Gain Error –15 –5 +15 %
Linearity ±0.6 %
Sync Level NTSC 243 286 329 mV

PAL 300 mV

DC Black Level 1.3 V

Chrominance (CRMA)

Bandwidth NTSC 3.6 MHz

PAL 4.4 MHz

Color Burst Amplitude NTSC 170 240 330 mV p-p

PAL 252 mV

Color Signal to Burst Ratio Error –15 ±315 %
Color Burst Width NTSC 2.51 µs

PAL 2.28 µs

±3 Degrees

Phase Error

3

DC Black Level 2.1 V

Chroma Feedthrough R, G, B = 0 10 40 mV p-p
Chroma/Luma Time Alignment –140 ns

Composite (COMP)

Absolute Gain Error –5 ±15 %
Differential Gain With Respect to Chroma 0.5 %
Differential Phase With Respect to Chroma 2.0 %
DC Black Level 1.6 V

POWER SUPPLIES

Recommended Supply Range Single Supply +4.75 +5.25 V
Quiescent Current—Encode Mode 30 40 mA
Quiescent Current—Power Down 1 mA

NOTES

1

R, G, and B signals are inputted to an on-chip AC coupling capacitor.

2

All outputs measured at a 75 Ω reverse-terminated load; voltages at the IC output pins are twice those specified here.

3

Difference between ideal color-bar phases and the actual values.

Specifications are subject to change without notice.

–2–

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AD722

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V

Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . .600 mW

Operating Temperature Range . . . . . . . . . . . . . . 0°C to +70°C

16-Pin Small Outline Package (Wide Body)

PIN CONFIGURATION

(R-16)

Storage Temperature Range . . . . . . . . . . . . .–65°C to +125°C

Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C

NOTE
*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

Thermal Characteristics: 16-Pin SOIC Package: θJA = 100°C/W.

ORDERING GUIDE

STND HSYNC

1
2

AGND

3

FIN
APOS
ENCD

RIN

GIN

BIN

AD722

4

TOP VIEW

5

(Not to Scale)

6
7
89

Temperature Package Package

Model Range Description Option

AD722JR-16 0°C to +70°C 16-Pin SOIC R-16
AD722JR-16-Reel 0°C to +70°C 16-Pin SOIC R-16
AD722JR-16-Reel7 0°C to +70°C 16-Pin SOIC R-16

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD722 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

16
15
14
13
12
11
10

VSYNC
DPOS
DGND

SELECT
LUMA
COMP
CRMA

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–3–

AD722

PIN DESCRIPTIONS

Pin Mnemonic Description Equivalent Circuit

1 STND A Logical HIGH input selects NTSC encoding. Circuit A

A Logical LOW input selects PAL encoding.

CMOS Logic Levels.
2 AGND Analog Ground Connection.
3 FIN FSC clock or parallel-resonant crystal, or 4FSC clock input. Circuit B

For NTSC: 3.579 545 MHz or 14.318 180 MHz.

For PAL: 4.433 619 MHz or 17.734 480 MHz.

CMOS Logic Levels for subcarrier clocks.
4 APOS Analog Positive Supply (+5 V ± 5%).
5 ENCD A Logical HIGH input enables the encode function. Circuit A

A Logical LOW input powers down chip when not in use.

CMOS Logic Levels.
6 RIN Red Component Video Input. Circuit C

0 to 714 mV for NTSC; 0 to 700 mV for PAL.
7 GIN Green Component Video Input. Circuit C

0 to 714 mV for NTSC.

0 to 700 mV for PAL.
8 BIN Blue Component Video Input. Circuit C

0 to 714 mV for NTSC.

0 to 700 mV for PAL.
9 CRMA Chrominance Output (Subcarrier Only).* Circuit D

Approximately 1.8 V peak-to-peak for both NTSC and PAL.
10 COMP Composite Video Output.* Circuit D

Approximately 2.5 V peak-to-peak for both NTSC and PAL.
11 LUMA Luminance plus SYNC Output.* Circuit D

Approximately 2 V peak-to-peak for both NTSC and PAL.
12 SELECT A Logical LOW input selects the FSC operating mode. Circuit A

A Logical HIGH input selects the 4FSC operating mode.

CMOS Logic Levels.
13 DGND Digital Ground Connections.
14 DPOS Digital Positive Supply (+5 V ± 5%) .
15 VSYNC Vertical Sync Signal (if using external CSYNC set at +5 V). Circuit A
16 HSYNC Horizontal Sync Signal (or CSYNC signal). Circuit A

*The Luminance, Chrominance, and Composite Outputs are at twice normal levels for driving 75 Ω reverse-terminated lines.

1

5
12

15
16

3

DPOS

Circuit A

APOS

Circuit B

V

BIAS

Equivalent Circuits

–4–

APOS

4pF

6

7
8

TYP

V

CLAMP

Circuit C

APOS

9
10
11

Circuit D

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