ANALOG DEVICES AD7195 Service Manual
4.8 kHz, Ultralow Noise, 24-Bit
Sigma-Delta ADC with PGA and AC Excitation
FEATURES
AC or DC sensor excitation
RMS noise: 8.5 nV at 4.7 Hz (gain = 128)
16 noise-free bits at 2.4 kHz (gain = 128)
Up to 22.5 noise-free bits (gain = 1)
Offset drift: 5 nV/°C
Gain drift: 1 ppm/°C
Specified drift over time
2 differential/4 pseudo differential input channels
Automatic channel sequencer
Programmable gain (1 to 128)
Output data rate: 4.7 Hz to 4.8 kHz
Internal or external clock
Simultaneous 50 Hz/60 Hz rejection
Power supply
AV
: 4.75 V to 5.25 V
DD
DV
: 2.7 V to 5.25 V
DD
Current: 6 mA
Temperature range: –40°C to +105°C
Package: 32-lead LFCSP
INTERFACE
3-wire serial
SPI, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
APPLICATIONS
Weigh scales
Strain gage transducers
Pressure measurement
Temperature measurement
AD7195
Chromatography
PLC/DCS analog input modules
Data acquisition
Medical and scientific instrumentation
GENERAL DESCRIPTION
The AD7195 is a low noise, complete analog front end for high
precision measurement applications. It contains a low noise,
24-bit sigma-delta (Σ-) analog-to-digital converter (ADC).
The on-chip low noise gain stage means that signals of small
amplitude can be interfaced directly to the ADC. The AD7195
contains ac excitation, which is used to remove dc-induced
offsets from bridge sensors.
The device can be configured to have two differential inputs or
four pseudo differential inputs. The on-chip channel sequencer
allows several channels to be enabled, and the AD7195 sequentially
converts on each enabled channel. This simplifies communication
with the part. The on-chip 4.92 MHz clock can be used as the
clock source to the ADC or, alternatively, an external clock or
crystal can be used. The output data rate from the part can be
varied from 4.7 Hz to 4.8 kHz.
The device has two digital filter options. The choice of filter
affects the rms noise/noise-free resolution at the programmed
output data rate, the settling time, and the 50 Hz/60 Hz rejection. For applications that require all conversions to be settled,
the AD7195 includes a zero latency feature.
The part operates with a 5 V analog power supply and a digital
power supply from 2.7 V to 5.25 V. It consumes a current of
6 mA. It is housed in a 32-lead LFCSP package.
FUNCTIONAL BLOCK DIAGRAM
AV
DD
AIN1
AIN2
AIN3
AIN4
AINCOM
BPDSW
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
MUX
AD7195
DV
DD
AGND
AGND
SENSOR
AV
TEMP
DGND REFIN(+) REFIN(–)
DD
PGA
ACX1 ACX1 ACX2ACX2
REFERENCE
DETECT
SERIAL
Σ-Δ
ADC
AC
EXCITATION
CLOCK
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.
INTERFACE
AND
CONTROL
LOGIC
CLOCK
CIRCUITRY
MCLK1 MCLK2
DOUT/RDY
DIN
SCLK
CS
SYNC
08771-001
AD7195
TABLE OF CONTENTS
Features .............................................................................................. 1
Interface ............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings ............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution .................................................................................. 8
Pin Configuration and Function Descriptions ............................. 9
Typical Performance Characteristics ........................................... 11
RMS Noise and Resolution ............................................................ 13
Sinc4 Chop Disabled ................................................................... 13
Sinc3 Chop Disabled ................................................................... 14
Sinc4 Chop Enabled .................................................................... 15
Sinc3 Chop Enabled .................................................................... 16
On-Chip Registers .......................................................................... 17
Communications Register ......................................................... 18
Status Register ............................................................................. 19
Mode Register ............................................................................. 19
Configuration Register .............................................................. 21
Data Register ............................................................................... 23
ID Register ................................................................................... 23
GPOCON Register ..................................................................... 23
Offset Register ............................................................................. 24
Full-Scale Register ...................................................................... 24
ADC Circuit Information .............................................................. 25
Overview ..................................................................................... 25
Analog Input Channel ............................................................... 26
PGA .............................................................................................. 26
Reference ..................................................................................... 26
Reference Detect ......................................................................... 26
Bipolar/Unipolar Configuration .............................................. 27
Data Output Coding .................................................................. 27
Burnout Currents ....................................................................... 27
AC Excitation .............................................................................. 27
Channel Sequencer .................................................................... 28
Digital Interface .......................................................................... 28
Reset ............................................................................................. 32
System Synchronization ............................................................ 32
Clock ............................................................................................ 32
Enable Parity ............................................................................... 32
Temperature Sensor ................................................................... 32
Bridge Power-Down Switch ...................................................... 33
Calibration ................................................................................... 33
Digital Filter ................................................................................ 34
Sinc4 Filter (Chop Disabled) ..................................................... 34
Sinc3 Filter (Chop Disabled) ..................................................... 36
Chop Enabled (Sinc4 Filter) ...................................................... 38
Chop Enabled (Sinc3 Filter) ...................................................... 40
Summary of Filter Options ....................................................... 41
Grounding and Layout .............................................................. 42
Applications Information .............................................................. 43
Weigh Scales ................................................................................ 43
Outline Dimensions ....................................................................... 44
Ordering Guide .......................................................................... 44
REVISION HISTORY
1/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 44
AD7195
SPECIFICATIONS
AVDD = 4.75 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFIN(+) = AVDD, REFIN(−) = AGND, MCLK = 4.92 MHz,
T
= T
MIN
to T
A
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments1
ADC
Output Data Rate 4.7 4800 Hz Chop disabled
1.17 1200 Hz Chop enabled, sinc4 filter
1.56 1600 Hz Chop enabled, sinc3 filter
No Missing Codes2 24 Bits FS > 1, sinc4 filter3
24 Bits FS > 4, sinc3 filter3
Resolution See the RMS Noise and Resolution section
RMS Noise and Output
Data Rates
Integral Nonlinearity
Gain = 12 ±1 ±5 ppm of FSR
Gain > 1 ±5 ±15 ppm of FSR
Offset Error
±0.5 μV Chop enabled
Offset Error Drift vs.
Temperature
±5 nV/°C Gain = 32 to 128; chop disabled
±5 nV/°C Chop enabled
Offset Error Drift vs. Time 25 nV/1000
Gain Error4 ±0.001 ±0.005 % max AVDD = 5 V, gain = 1, TA = 25°C (factory calibration
±0.006 % Gain > 1, post internal full-scale calibration
Gain Drift vs. Temperature ±1 ppm/°C
Gain Drift vs. Time 10 ppm/1000
Power Supply Rejection 95 dB Gain = 1, VIN = 1 V
98 103 Gain = 8, VIN = 1 V/gain
100 110 dB Gain > 8, VIN = 1 V/gain
Common-Mode Rejection
@ DC2 100 115 dB min Gain = 1, VIN = 1 V
@ DC 115 140 dB min Gain > 1, VIN = 1 V/gain
@ 50 Hz, 60 Hz2 120 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz
@ 50 Hz, 60 Hz2 120 dB 50 ± 1 Hz (50 Hz output data rate), 60 ± 1 Hz
Normal Mode Rejection2
Sinc4 Filter
Internal Clock
@ 50 Hz, 60 Hz 100 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz
74 dB 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1
@ 50 Hz 96 dB 50 Hz output data rate, 50 ± 1 Hz
@ 60 Hz 97 dB 60 Hz output data rate, 60 ± 1 Hz
External Clock
@ 50 Hz, 60 Hz 120 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz
82 dB 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz
@ 50 Hz 120 dB 50 Hz output data rate, 50 ± 1 Hz
@ 60 Hz 120 dB 60 Hz output data rate, 60 ± 1 Hz
Sinc3 Filter
Internal Clock
@ 50 Hz, 60 Hz 75 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz
60 dB 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz
@ 50 Hz 70 dB 50 Hz output data rate, 50 ± 1 Hz
@ 60 Hz 70 dB 60 Hz output data rate, 60 ± 1 Hz
, unless otherwise noted.
MAX
See the RMS Noise and Resolution section
4, 5
±75/gain μV Chop disabled
±100/gain nV/°C Gain = 1 to 16; chop disabled
hours
hours
Rev. 0 | Page 3 of 44
Gain > 32
conditions)
Gain = 1
(60 Hz output data rate)
Hz
AD7195
Parameter Min Typ Max Unit Test Conditions/Comments1
External Clock
@ 50 Hz, 60 Hz 100 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz
67 dB 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz
@ 50 Hz 95 dB 50 Hz output data rate, 50 ± 1 Hz
@ 60 Hz 95 dB 60 Hz output data rate, 60 ± 1 Hz
ANALOG INPUTS
Differential Input Voltage
Ranges
−(AVDD −
Absolute AIN Voltage Limits2
Unbuffered Mode AGND − 0.05 AVDD + 0.05 V
Buffered Mode AGND + 0.25 AV
Analog Input Current
Buffered Mode
Input Current2 −2 +2 nA Gain = 1
−4.5 +4.5 nA Gain > 1
Input Current Drift ±5 pA/°C
Unbuffered Mode
Input Current ±5 μA/V Gain = 1, input current varies with input voltage
±1 μA/V Gain > 1
Input Current Drift ±0.05 nA/V/°C External clock
±1.6 nA/V/°C Internal clock
REFERENCE INPUT
REFIN Voltage 1 AVDD AVDD V REFIN = REFIN(+) − REFIN(−). The differential input must
Absolute REFIN Voltage
2
Limits
Average Reference Input
Current
Average Reference Input
Current Drift
±1.3 nA/V/°C Internal clock
Normal Mode Rejection2 Same as for
Common-Mode Rejection 95 dB
Reference Detect Levels 0.3 0.6 V
TEMPERATURE SENSOR
Accuracy ±2 °C Applies after user calibration at 25°C
Sensitivity 2815 Codes/°C Bipolar mode
BRIDGE POWER-DOWN SWITCH
RON 10 Ω
Allowable Current2 30 mA Continuous current
BURNOUT CURRENTS
AIN Current 500 nA Analog inputs must be buffered and chop disabled
DIGITAL OUTPUTS (ACXx,
Output High Voltage, V
Output Low Voltage, V
ACXx
OH
OL
INTERNAL/EXTERNAL CLOCK
Internal Clock
Frequency 4.72 5.12 MHz
Duty Cycle 50:50 %
External Clock/Crystal2
Frequency 2.4576 4.9152 5.12 MHz
Input Low Voltage V
INL
0.4 V DVDD = 3 V
Input High Voltage, V
3.5 V DVDD = 5 V
Input Current −10 +10 μA
±V
1.25 V)/gain
/gain V VREF = REFIN(+) − REFIN(−), gain = 1 to 128
REF
+(AVDD −
V Gain > 1
1.25 V)/gain
− 0.25 V
DD
be limited to ±(AV
GND − 0.05 AV
+ 0.05 V
DD
7 μA/V
±0.03 nA/V/°C External clock
analog inputs
)
2
4 V AVDD = 5 V, I
2
0.4 V AVDD = 5 V, I
0.8 V DVDD = 5 V
2.5 V DVDD = 3 V
INH
− 1.25 V)/gain when gain > 1
DD
= 200 μA
SOURCE
= 800 μA
SINK
Rev. 0 | Page 4 of 44
AD7195
Parameter Min Typ Max Unit Test Conditions/Comments1
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
Hysteresis2 0.1 0.25 V
Input Currents −10 +10 μA
LOGIC OUTPUT (DOUT/
Output High Voltage, V
Output Low Voltage, V
Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage
Current
Floating-State Output
Capacitance
Data Output Coding Offset binary
SYSTEM CALIBRATION2
Full-Scale Calibration Limit 1.05 × FS V
Zero-Scale Calibration Limit −1.05 × FS V
Input Span 0.8 × FS 2.1 × FS V
POWER REQUIREMENTS7
Power Supply Voltage
AVDD − AGND 4.75 5.25 V
DVDD − DGND 2.7 5.25 V
Power Supply Currents
AIDD Current 0.85 1 mA gain = 1, buffer off
1.1 1.3 mA gain = 1, buffer on
3.5 4.5 mA gain = 8, buffer off
4 5 mA gain = 8, buffer on
5 6.4 mA gain = 16 to 128, buffer off
5.5 6.9 mA gain = 16 to 128, buffer on
DIDD Current 0.35 0.4 mA DVDD = 3 V
0.5 0.6 mA DVDD = 5 V
1.5 mA External crystal used
IDD (Power-Down Mode) 2 μA
1
Temperature range: −40°C to +105°C.
2
Specification is not production tested, but is supported by characterization data at initial product release.
3
FS is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register.
4
Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full-
scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.
5
The analog inputs are configured for differential mode.
6
REJ60 is a bit in the mode register. When the output data rate is set to 50 Hz, setting REJ60 to 1 places a notch at 60 Hz, allowing simultaneous 50 Hz/60 Hz rejection.
7
Digital inputs equal to DVDD or DGND.
2
2 V
INH
2
0.8 V
INL
RDY
OH
OL
OH
OL
)
2
DVDD − 0.6 V DVDD = 3 V, I
2
0.4 V DVDD = 3 V, I
2
4 V DVDD = 5 V, I
2
0.4 V DVDD = 5 V, I
−10 +10 μA
10 pF
SOURCE
= 100 μA
SINK
SOURCE
= 1.6 mA
SINK
= 100 μA
= 200 μA
Rev. 0 | Page 5 of 44
AD7195
TIMING CHARACTERISTICS
AVDD = 4.75 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless
otherwise noted.
Table 2.
Parameter Limit at T
MIN
, T
(B Version) Unit Conditions/Comments
MAX
1, 2
READ AND WRITE OPERATIONS
t3 100 ns min SCLK high pulse width
t4 100 ns min SCLK low pulse width
READ OPERATION
t1 0 ns min
falling edge to DOUT/RDY active time
CS
60 ns max DVDD = 4.75 V to 5.25 V
80 ns max DVDD = 2.7 V to 3.6 V
3
t
0 ns min SCLK active edge to data valid delay4
2
60 ns max DVDD = 4.75 V to 5.25 V
80 ns max DVDD = 2.7 V to 3.6 V
5, 6
t
10 ns min
5
Bus relinquish time after CS
inactive edge
80 ns max
t6 0 ns min
t7 10 ns min
SCLK inactive edge to CS
SCLK inactive edge to DOUT/RDY
inactive edge
high
WRITE OPERATION
t8 0 ns min
falling edge to SCLK active edge setup time4
CS
t9 30 ns min Data valid to SCLK edge setup time
t10 25 ns min Data valid to SCLK edge hold time
t11 0 ns min
1
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.
2
See Figure 3 and Figure 4.
3
These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
4
The SCLK active edge is the falling edge of SCLK.
5
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number
is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
6
RDY
returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while
is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the
digital word can be read only once.
rising edge to SCLK edge hold time
CS
RDY
Rev. 0 | Page 6 of 44
AD7195
S
Circuit and Timing Diagram
I
(1.6mA WITH DVDD = 5V,
SINK
100µA WIT H DV
TO
OUTPUT
PIN
50pF
I
SOURCE
100µA WIT H DV
Figure 2. Load Circuit for Timing Characterization
CS (I)
t
1
DOUT/RDY (O)
SCLK (I)
t
2
I = INPUT, O = OUTPUT
MSB LSB
t
3
Figure 3. Read Cycle Timing Diagram
= 3V)
DD
1.6V
(200µA WIT H DVDD = 5V,
= 3V)
DD
t
7
t
4
8771-002
t
6
t
5
8771-003
CS (I)
t
11
8771-004
CLK (I)
DIN (I)
I = INPUT, O = OUT PUT
t
8
t
9
t
10
MSB LSB
Figure 4. Write Cycle Timing Diagram
Rev. 0 | Page 7 of 44
AD7195
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
AVDD to AGND
DVDD to AGND
AGND to DGND
Analog Input Voltage to AGND
Reference Input Voltage to AGND
Digital Input Voltage to DGND
Digital Output Voltage to DGND
AIN/Digital Input Current 10 mA
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature 150°C
Lead Temperature, Soldering
Reflow 260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−40°C to +105°C
−65°C to +150°C
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA θ
32-Lead LFCSP_WQ 32.5 32.71 °C/W
Unit
JC
ESD CAUTION
Rev. 0 | Page 8 of 44
AD7195
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SCLK
MCLK2NCDOUT/RDY
DIN
MCLK1
CS
32313029282726
1
ACX2
2
ACX2
3
ACX1
ACX1
AV
DD
AGND
NC
AINCOM
NOTES
1. NC = NO CONNECT.
2. CONNECT EX P OSED PAD TO AGND.
4
5
6
7
8
AD7195
TOP VIEW
(Not to Scale)
9
10111213141516
NC
NC
AIN2
AIN1
Figure 5.Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 ACX2
Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac
excited bridge applications. In ac mode, ACX2 toggles in anti-phase with ACX1. If the ACX bit equals zero (ac
excitation turned off), the ACX2 output remains low. When toggling, it is guaranteed to be nonoverlapping
with ACX1. The nonoverlap interval between ACX1 and ACX2 is 1/(master clock) which is equal to 200 ns
when a 4.92 MHz clock is used.
2
Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac
ACX2
excited bridge applications. This output is the inverse of ACX2. If the ACX bit equals zero (ac excitation turned
off), the ACX2 output remains high.
3 ACX1
Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac
excited bridge applications. When ACX1 is high, the bridge excitation is taken as normal and when ACX1 is
low, the bridge excitation is reversed (chopped). If the Bit ACX equals zero (ac excitation turned off), the ACX1
output remains high.
4
Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac
ACX1
excited bridge applications. This output is the inverse of ACX1. When ACX1 is low, the bridge excitation is
taken as normal and when ACX1 is high, the bridge excitation is reversed (chopped). If the ACX bit equals
zero (ac excitation turned off), the ACX1
5 AVDD Analog Supply Voltage, 4.75 V to 5.25 V. AVDD is independent of DVDD.
6 AGND Analog Ground Reference Point.
7 NC No Connect. This pin should be tied to AGND.
8 AINCOM Analog inputs AIN1 to AIN4 are referenced to this input when configured for pseudo differential operation.
9 AIN1
Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with
AIN2 or as a pseudo differential input when used with AINCOM.
10 AIN2
Analog Input. This pin can be configured as the negative input of a fully differential input pair when used
with AIN1 or as a pseudo differential input when used with AINCOM.
11 NC No Connect. This pin should be tied to AGND.
12 NC No Connect. This pin should be tied to AGND.
13 NC No Connect. This pin should be tied to AGND.
14 NC No Connect. This pin should be tied to AGND.
15 AIN3
Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with
AIN4 or as a pseudo differential input when used with AINCOM.
16 AIN4
Analog Input. This pin can be configured as the negative input of a fully differential input pair when used
with AIN3 or as a pseudo differential input when used with AINCOM.
17 REFIN(+)
Positive Reference Input. An external reference can be applied between REFIN(+) and REFIN(−). REFIN(+) can
lie anywhere between AV
and AGND + 1 V. The nominal reference voltage, (REFIN(+) − REFIN(−)), is AVDD,
DD
but the part functions with a reference from 1 V to AV
18 REFIN(−) Negative Reference Input. This reference input can lie anywhere between AGND and AVDD − 1 V.
19 NC No Connect. This pin should be tied to AGND.
Rev. 0 | Page 9 of 44
SYNC
25
DV
24
DD
23
AV
DD
22
DGND
AGND
21
20
BPDSW
NC
19
REFIN(–)
18
REFIN(+)
17
NC
NC
AIN3
AIN4
08771-005
output remains low.
.
DD
AD7195
Pin No. Mnemonic Description
20 BPDSW Bridge Power-Down Switch to AGND.
21 AGND Analog Ground Reference Point.
22 DGND Digital Ground Reference Point.
23 AVDD Analog Supply Voltage, 4.75 V to 5.25 V. AVDD is independent of DVDD.
24 DVDD Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD.
25
26 NC No Connect. This pin should be tied to AGND.
27
28 DIN
29 MCLK1
30 MCLK2
31 SCLK
32
Logic input that allows for synchronization of the digital filters and analog modulators when using a number
SYNC
of AD7195 devices. While SYNC
calibration control logic are reset, and the analog modulator is also held in its reset state. SYNC does not
affect the digital interface but does reset RDY
to DV
.
DD
DOUT/RDY
Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in
CS
Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output
pin to access the output shift register of the ADC. The output shift register can contain data from any of the
on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate
the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next
update occurs. The DOUT/RDY
data is available. With an external serial clock, the data can be read using the DOUT/RDY
data-/control-word information is placed on the DOUT/RDY
SCLK rising edge.
Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control
registers in the ADC, with the register selection bits of the communications register identifying the appropriate register.
When the master clock for the device is provided externally by a crystal, the crystal is connected between
MCLK1 and MCLK2.
Master Clock Signal for the Device. The AD7195 has an internal 4.92 MHz clock. This internal clock can be
made available on the MCLK2 pin. The clock for the AD7195 can be provided externally also in the form of a
crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin
can be driven with a CMOS-compatible clock and the MCLK1 pin left unconnected.
Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitttriggered input, making the interface suitable for opto-isolated applications. The serial clock can be
continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous
clock with the information transmitted to or from the ADC in smaller batches of data.
systems with more than one device on the serial bus or as a frame synchronization signal in communicating
with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and
DOUT used to interface with the device.
is low, the nodes of the digital filter, the filter control logic, and the
to a high state if it is low. SYNC has a pull-up resistor internally
falling edge can be used as an interrupt to a processor, indicating that valid
pin on the SCLK falling edge and is valid on the
pin. With CS low, the
Rev. 0 | Page 10 of 44
AD7195
TYPICAL PERFORMANCE CHARACTERISTICS
8,388,760
30
8,388,758
8,388,756
8,388,754
CODE
8,388,752
8,388,750
8,388,748
8,388,746
0 200 400 600 800 1000
Figure 6. Noise (V
= 5 V, Output Data Rate = 4.7 Hz, Gain = 128,
REF
Chop Disabled, Sinc
250
200
150
100
FREQUENCY
50
0
8,388,746
8,388,748
Figure 7. Noise Distribution Histogram (V
8,388,750
SAMPLE
8,388,752
CODE
4
Filter)
8,388,754
8,388,756
REF
8,388,758
= 5 V,
Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc4 Filter)
8,388,950
8,388,900
8,388,850
8,388,800
8,388,750
8,388,700
CODE
8,388,650
8,388,600
8,388,550
8,388,500
8,388,450
0 200 400 600 800 1000100 300 500 700 900
Figure 8. Noise (V
= 5 V, Output Data Rate = 4800 Hz, Gain = 128,
REF
Chop Disabled, Sinc
SAMPLES
4
Filter)
8,388,760
25
20
15
FREQUENCY
10
5
0
8,388,490 8,388,576 8,388,662 8,388,748 8,388,834 8,388,920
08771-006
Figure 9. Noise Distribution Histogram (V
CODE
REF
= 5 V,
08771-009
Output Data Rate = 4800 Hz, Gain = 128, Chop Disabled, Sinc4 Filter)
8,388,820
8,388,800
8,388,780
8,388,760
8,388,740
8,388,720
CODE
8,388,700
8,388,680
8,388,660
8,388,640
8,388,620
0 200 400 600 800 1000100 300 500 700 900
08771-007
Figure 10. Noise (V
= 5 V, Output Data Rate = 4800 Hz, Gain = 1,
REF
Chop Disabled, Sinc
80
70
60
50
40
FREQUENCY
30
20
10
0
8,388,620 8,388,660 8,388,700 8,388,740 8,388,780 8,388,820
08771-008
Figure 11. Noise Distribution Histogram (V
Output Data Rate = 4800 Hz, Gain = 1, Chop Disabled, Sinc
SAMPLES
CODE
4
Filter)
REF
= 5 V,
4
Filter)
08771-010
08771-011
Rev. 0 | Page 11 of 44
AD7195
3.0
0
2.0
1.0
0
INL (ppm of FSR)
–1.0
–2.0
–3.0
–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5
VIN (V)
Figure 12. INL (Gain = 1)
6
4
2
0
INL (ppm of FSR)
–2
–4
–0.1
–0.2
–0.3
–0.4
OFFSET (µV)
–0.5
–0.6
–0.7
–60 –40 –20 0 20 40 60 80 100 120
08771-012
TEMERATURE (°C)
08771-015
Figure 15. Offset Error (Gain = 128, Chop Disabled)
1.000008
1.000007
1.000006
1.000005
1.000004
GAIN
1.000003
1.000002
1.000001
–6
–0.020 –0.015 –0.010 –0.005 0 0.005 0.010 0.015 0.020
VIN (V)
Figure 13. INL (Gain = 128)
66
64
62
60
58
OUTPUT VO LTAGE (µ V )
56
54
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE ( °C)
Figure 14. Offset Error (Gain = 1, Chop Disabled)
1.000000
–60 –40 –20 0 20 40 60 80 100 120
08771-013
TEMPERATURE ( °C)
08771-016
Figure 16. Gain Error (Gain = 1, Chop Disabled)
128.003
128.002
128.001
128.000
GAIN
127.999
127.998
127.997
127.996
–60 –40 –20 0 20 40 60 80 100 120
08771-014
TEMPERATURE ( °C)
08771-017
Figure 17. Gain Error (Gain = 128, Chop Disabled)
Rev. 0 | Page 12 of 44
AD7195
RMS NOISE AND RESOLUTION
The tables in this section show the rms noise, peak-to-peak
noise, effective resolution, and noise-free (peak-to-peak) resolution of the AD7195 for various output data rates and gain settings,
with chop disabled and chop enabled for the sinc
4
and sinc3
filters. The numbers given are for the bipolar input range with
the external 5 V reference. These numbers are typical and are
SINC4 CHOP DISABLED
Table 6. RMS Noise (nV) vs. Gain and Output Data Rate
Filter Wo rd
(Decimal)
1023 4.7 852.5 280 96 50 22 10 8.5
640 7.5 533 390 120 54 28 12 10.5
480 10 400 470 130 56 31 14 11.5
96 50 80 1000 150 78 45 33 28
80 60 66.7 1100 170 88 52 36 31
32 150 26.7 1460 220 125 75 55 48
16 300 13.3 1900 285 170 100 75 67
5 960 4.17 3000 480 280 175 140 121
2 2400 1.67 5000 780 440 280 220 198
1 4800 0.83 14,300 1920 1000 550 380 295
Output Data
Rate (Hz)
Settling
Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128
generated with a differential input voltage of 0 V when the ADC
is continuously converting on a single channel. It is important
to note that the effective resolution is calculated using the rms
noise, whereas the peak-to-peak resolution is calculated based
on peak-to-peak noise. The peak-to-peak resolution represents
the resolution for which there is no code flicker.
Table 7. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate
Filter Wo rd
(Decimal)
1023 4.7 852.5 1600 500 250 130 65 56
640 7.5 533 2200 650 290 150 80 65
480 10 400 3000 670 300 190 100 70
96 50 80 6000 900 450 280 180 170
80 60 66.7 7200 1100 480 300 220 190
32 150 26.7 8300 1500 750 410 340 310
16 300 13.3 11,000 1700 1000 600 440 430
5 960 4.17 20,000 3000 1800 1100 810 710
2 2400 1.67 32,000 5100 2800 1700 1400 1200
1 4800 0.83 86,000 13,000 6000 3500 2400 1900
Output Data
Rate (Hz)
Settling
Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128
Table 8. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate
Filter Wo rd
(Decimal)
1023 4.7 852.5 24 (22.6) 23.6 (21.3) 23.6 (21.3) 23.6 (21.2) 23.6 (21.2) 23.1 (20.4)
640 7.5 533 24 (22.1) 23.4 (20.9) 23.4 (20.9) 23.4 (20.9) 23.4 (20.9) 22.8 (20.2)
480 10 400 24 (21.7) 23.3 (20.8) 23.3 (20.8) 23.3 (20.8) 23.3 (20.6) 22.7 (20.1)
96 50 80 23.3 (20.7) 23 (20.4) 22.9 (20.4) 22.7 (20.1) 22.2 (19.7) 21.4 (18.8)
80 60 66.7 23.1 (20.4) 22.8 (20.1) 22.8 (20) 22.5 (20 ) 22.1 (19.4) 21.3 (18.6)
32 150 26.7 22.7 (20.2) 22.4 (19.7) 22.3 (19.7) 22 (19.5) 21.5 (18.8) 20.6 (17.9)
16 300 13.3 22.3 (19.8) 22.1 (19.5) 21.8 (19.3) 21.6 (19) 21 (18.4) 20.1 (17.5)
5 960 4.17 21.7 (18.9) 21.3 (18.7) 21.1 (18.4) 20.8 (18.1) 20.2 (17.6) 19.3 (16.7)
2 2400 1.67 20.9 (18.3) 20.6 (17.9) 20.4 (17.7) 20.1 (17.5) 19.5 (16.8) 18.6 (16)
1 4800 0.83 19.4 (16.8) 19.3 (16.6) 19.3 (16.4) 19.1 (16.4) 18.8 (16) 18 (15.3)
1
The output peak-to-peak (p-p) resolution is listed in parentheses.
Output Data
Rate (Hz)
Settling
Time (ms)
Gain of 1
1
Gain of 81 Gain of 161 Gain of 321 Gain of 641 Gain of 1281
Rev. 0 | Page 13 of 44
AD7195
SINC3 CHOP DISABLED
Table 9. RMS Noise (nV) vs. Gain and Output Data Rate
Filter Wo rd
(Decimal)
1023 4.7 639.4 290 125 53 24 10.5 9
640 7.5 400 470 135 56 29 13 11.5
480 10 300 610 145 58 32 16 12.5
96 50 60 1100 160 86 50 35 29
80 60 50 1200 170 95 55 40 32
32 150 20 1500 230 130 80 58 50
16 300 10 1950 308 175 110 83 73
5 960 3.13 4000 590 330 200 150 133
2 2400 1.25 56,600 7000 3500 1800 900 490
1 4800 0.625 442,000 55,000 28,000 14,000 7000 3450
Table 10. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate
Filter Wo rd
(Decimal)
1023 4.7 639.4 1700 750 260 140 65 56
640 7.5 400 2400 800 340 150 84 60
480 10 300 3000 900 360 200 100 70
96 50 60 6600 1000 480 290 200 180
80 60 50 6800 1100 600 300 240 200
32 150 20 8900 1400 710 470 360 310
16 300 10 13,000 2000 1000 670 470 500
5 960 3.13 25,000 3400 2200 1200 850 800
2 2400 1.25 310,000 41,000 22,000 12,000 5600 3100
1 4800 0.625 2,600,000 300,000 170,000 79,000 41,000 24,000
Output Data
Rate (Hz)
Output Data
Rate (Hz)
Settling
Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128
Settling
Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128
Table 11. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate
Filter Wo rd
(Decimal)
Output Data
Rate (Hz)
Settling
Time (ms)
Gain of 1
1
Gain of 81 Gain of 161 Gain of 321 Gain of 641 Gain of 1281
1023 4.7 639.4 24 (22.5) 23.5 (21) 23.5 (21) 23.5 (21) 23.5 (21) 23 (20.4)
640 7.5 400 24 (22) 23.3 (20.8) 23.3 (20.8) 23.3 (20.8) 23.3 (20.8) 22.7 (20.3)
480 10 300 24 (22) 23.2 (20.5) 23.2 (20.5) 23.2 (20.5) 23.2 (20.5) 22.6 (20.1)
96 50 60 23.1 (20.5) 22.9 (20.3) 22.8 (20.3) 22.6 (20) 22.1 (19.6) 21.4 (18.7)
80 60 50 23 (20.5) 22.8 (20.1) 22.6 (20) 22.4 (20) 21.9 (19.3) 21.2 (18.6)
32 150 20 22.7 (20) 22.4 (19.8) 22.2 (19.7) 21.9 (19.3) 21.4 (18.7) 20.6 (17.9)
16 300 10 22.3 (19.5) 22 (19.3) 21.8 (19.3) 21.4 (18.8) 20.8 (18.3) 20 (17.3)
5 960 3.13 21.3 (18.5) 21 (18.5) 20.9 (18.1) 20.6 (18) 20 (17.5) 19.2 (16.6)
2 2400 1.25 17.4 (14.9) 17.4 (14.9) 17.4 (14.8) 17.4 (14.7) 17.4 (14.7) 17.3 (14.6)
1 4800 0.625 14.5 (11.9) 14.5 (11.9) 14.4 (11.8) 14.4 (11.8) 14.4 (11.8) 14.4 (11.7)
1
The output peak-to-peak (p-p) resolution is listed in parentheses.
Rev. 0 | Page 14 of 44
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