Datasheet AD7195 Datasheet (ANALOG DEVICES)

4.8 kHz, Ultralow Noise, 24-Bit

Sigma-Delta ADC with PGA and AC Excitation

FEATURES

AC or DC sensor excitation RMS noise: 8.5 nV at 4.7 Hz (gain = 128) 16 noise-free bits at 2.4 kHz (gain = 128) Up to 22.5 noise-free bits (gain = 1) Offset drift: 5 nV/°C Gain drift: 1 ppm/°C Specified drift over time 2 differential/4 pseudo differential input channels Automatic channel sequencer Programmable gain (1 to 128) Output data rate: 4.7 Hz to 4.8 kHz Internal or external clock Simultaneous 50 Hz/60 Hz rejection Power supply

: 4.75 V to 5.25 V

: 2.7 V to 5.25 V

Current: 6 mA Temperature range: –40°C to +105°C Package: 32-lead LFCSP

INTERFACE

3-wire serial SPI, QSPI™, MICROWIRE™, and DSP compatible Schmitt trigger on SCLK

APPLICATIONS

Weigh scales Strain gage transducers Pressure measurement Temperature measurement

AD7195

Chromatography PLC/DCS analog input modules Data acquisition Medical and scientific instrumentation

GENERAL DESCRIPTION

The AD7195 is a low noise, complete analog front end for high precision measurement applications. It contains a low noise, 24-bit sigma-delta (Σ-) analog-to-digital converter (ADC). The on-chip low noise gain stage means that signals of small amplitude can be interfaced directly to the ADC. The AD7195 contains ac excitation, which is used to remove dc-induced offsets from bridge sensors.

The device can be configured to have two differential inputs or four pseudo differential inputs. The on-chip channel sequencer allows several channels to be enabled, and the AD7195 sequentially converts on each enabled channel. This simplifies communication with the part. The on-chip 4.92 MHz clock can be used as the clock source to the ADC or, alternatively, an external clock or crystal can be used. The output data rate from the part can be varied from 4.7 Hz to 4.8 kHz.

The device has two digital filter options. The choice of filter affects the rms noise/noise-free resolution at the programmed output data rate, the settling time, and the 50 Hz/60 Hz rejection. For applications that require all conversions to be settled, the AD7195 includes a zero latency feature.

The part operates with a 5 V analog power supply and a digital power supply from 2.7 V to 5.25 V. It consumes a current of 6 mA. It is housed in a 32-lead LFCSP package.

FUNCTIONAL BLOCK DIAGRAM

AIN1 AIN2 AIN3 AIN4

AINCOM

BPDSW

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

MUX

AD7195

AGND

SENSOR

TEMP

DGND REFIN(+) REFIN(–)

PGA

ACX1 ACX1 ACX2ACX2

REFERENCE

DETECT

SERIAL

Σ-Δ

ADC

EXCITATION

CLOCK

Figure 1.

INTERFACE

AND

CONTROL

LOGIC

CLOCK

CIRCUITRY

MCLK1 MCLK2

DOUT/RDY DIN SCLK

CS SYNC

08771-001

AD7195

Features .............................................................................................. 1

Interface ............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ................................................................ 6

Absolute Maximum Ratings ............................................................ 8

Thermal Resistance ...................................................................... 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ............................. 9

Typical Performance Characteristics ........................................... 11

RMS Noise and Resolution ............................................................ 13

Sinc4 Chop Disabled ................................................................... 13

Sinc3 Chop Disabled ................................................................... 14

Sinc4 Chop Enabled .................................................................... 15

Sinc3 Chop Enabled .................................................................... 16

On-Chip Registers .......................................................................... 17

Communications Register ......................................................... 18

Status Register ............................................................................. 19

Mode Register ............................................................................. 19

Configuration Register .............................................................. 21

Data Register ............................................................................... 23

ID Register ................................................................................... 23

GPOCON Register ..................................................................... 23

Offset Register ............................................................................. 24

Full-Scale Register ...................................................................... 24

ADC Circuit Information .............................................................. 25

Overview ..................................................................................... 25

Analog Input Channel ............................................................... 26

PGA .............................................................................................. 26

Reference ..................................................................................... 26

Reference Detect ......................................................................... 26

Bipolar/Unipolar Configuration .............................................. 27

Data Output Coding .................................................................. 27

Burnout Currents ....................................................................... 27

AC Excitation .............................................................................. 27

Channel Sequencer .................................................................... 28

Digital Interface .......................................................................... 28

Reset ............................................................................................. 32

System Synchronization ............................................................ 32

Clock ............................................................................................ 32

Enable Parity ............................................................................... 32

Temperature Sensor ................................................................... 32

Bridge Power-Down Switch ...................................................... 33

Calibration ................................................................................... 33

Digital Filter ................................................................................ 34

Sinc4 Filter (Chop Disabled) ..................................................... 34

Sinc3 Filter (Chop Disabled) ..................................................... 36

Chop Enabled (Sinc4 Filter) ...................................................... 38

Chop Enabled (Sinc3 Filter) ...................................................... 40

Summary of Filter Options ....................................................... 41

Grounding and Layout .............................................................. 42

Applications Information .............................................................. 43

Weigh Scales ................................................................................ 43

Outline Dimensions ....................................................................... 44

Ordering Guide .......................................................................... 44

REVISION HISTORY

1/10—Revision 0: Initial Version

Rev. 0 | Page 2 of 44

AD7195

SPECIFICATIONS

AVDD = 4.75 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFIN(+) = AVDD, REFIN(−) = AGND, MCLK = 4.92 MHz, T

= T

MIN

to T

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments1

ADC

Output Data Rate 4.7 4800 Hz Chop disabled

1.17 1200 Hz Chop enabled, sinc4 filter

1.56 1600 Hz Chop enabled, sinc3 filter No Missing Codes2 24 Bits FS > 1, sinc4 filter3 24 Bits FS > 4, sinc3 filter3 Resolution See the RMS Noise and Resolution section RMS Noise and Output

Data Rates

Integral Nonlinearity

Gain = 12 ±1 ±5 ppm of FSR

Gain > 1 ±5 ±15 ppm of FSR Offset Error ±0.5 μV Chop enabled Offset Error Drift vs.

Temperature ±5 nV/°C Gain = 32 to 128; chop disabled ±5 nV/°C Chop enabled Offset Error Drift vs. Time 25 nV/1000

Gain Error4 ±0.001 ±0.005 % max AVDD = 5 V, gain = 1, TA = 25°C (factory calibration

±0.006 % Gain > 1, post internal full-scale calibration Gain Drift vs. Temperature ±1 ppm/°C Gain Drift vs. Time 10 ppm/1000

Power Supply Rejection 95 dB Gain = 1, VIN = 1 V 98 103 Gain = 8, VIN = 1 V/gain 100 110 dB Gain > 8, VIN = 1 V/gain Common-Mode Rejection

@ DC2 100 115 dB min Gain = 1, VIN = 1 V

@ DC 115 140 dB min Gain > 1, VIN = 1 V/gain

@ 50 Hz, 60 Hz2 120 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz

@ 50 Hz, 60 Hz2 120 dB 50 ± 1 Hz (50 Hz output data rate), 60 ± 1 Hz

Normal Mode Rejection2

Sinc4 Filter

Internal Clock

@ 50 Hz, 60 Hz 100 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz 74 dB 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1

@ 50 Hz 96 dB 50 Hz output data rate, 50 ± 1 Hz @ 60 Hz 97 dB 60 Hz output data rate, 60 ± 1 Hz

External Clock

@ 50 Hz, 60 Hz 120 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz 82 dB 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz @ 50 Hz 120 dB 50 Hz output data rate, 50 ± 1 Hz @ 60 Hz 120 dB 60 Hz output data rate, 60 ± 1 Hz

Sinc3 Filter

Internal Clock

@ 50 Hz, 60 Hz 75 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz 60 dB 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz @ 50 Hz 70 dB 50 Hz output data rate, 50 ± 1 Hz @ 60 Hz 70 dB 60 Hz output data rate, 60 ± 1 Hz

, unless otherwise noted.

MAX

See the RMS Noise and Resolution section

4, 5

±75/gain μV Chop disabled

±100/gain nV/°C Gain = 1 to 16; chop disabled

hours

Rev. 0 | Page 3 of 44

Gain > 32

conditions)

Gain = 1

(60 Hz output data rate)

AD7195

Parameter Min Typ Max Unit Test Conditions/Comments1

External Clock

@ 50 Hz, 60 Hz 100 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz

67 dB 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz

@ 50 Hz 95 dB 50 Hz output data rate, 50 ± 1 Hz

@ 60 Hz 95 dB 60 Hz output data rate, 60 ± 1 Hz

ANALOG INPUTS

Differential Input Voltage

Ranges

−(AVDD −

Absolute AIN Voltage Limits2

Unbuffered Mode AGND − 0.05 AVDD + 0.05 V Buffered Mode AGND + 0.25 AV

Analog Input Current

Buffered Mode

Input Current2 −2 +2 nA Gain = 1

−4.5 +4.5 nA Gain > 1 Input Current Drift ±5 pA/°C

Unbuffered Mode

Input Current ±5 μA/V Gain = 1, input current varies with input voltage

±1 μA/V Gain > 1

Input Current Drift ±0.05 nA/V/°C External clock

±1.6 nA/V/°C Internal clock

REFERENCE INPUT

REFIN Voltage 1 AVDD AVDD V REFIN = REFIN(+) − REFIN(−). The differential input must

Absolute REFIN Voltage

Limits

Average Reference Input

Current

Average Reference Input

Current Drift ±1.3 nA/V/°C Internal clock Normal Mode Rejection2 Same as for

Common-Mode Rejection 95 dB Reference Detect Levels 0.3 0.6 V

TEMPERATURE SENSOR

Accuracy ±2 °C Applies after user calibration at 25°C Sensitivity 2815 Codes/°C Bipolar mode

BRIDGE POWER-DOWN SWITCH

RON 10 Ω Allowable Current2 30 mA Continuous current

BURNOUT CURRENTS

AIN Current 500 nA Analog inputs must be buffered and chop disabled

DIGITAL OUTPUTS (ACXx,

Output High Voltage, V Output Low Voltage, V

ACXx

INTERNAL/EXTERNAL CLOCK

Internal Clock

Frequency 4.72 5.12 MHz Duty Cycle 50:50 %

External Clock/Crystal2

Frequency 2.4576 4.9152 5.12 MHz Input Low Voltage V

INL

0.4 V DVDD = 3 V Input High Voltage, V

3.5 V DVDD = 5 V Input Current −10 +10 μA

±V

1.25 V)/gain

/gain V VREF = REFIN(+) − REFIN(−), gain = 1 to 128

REF

+(AVDD −

V Gain > 1

1.25 V)/gain

− 0.25 V

be limited to ±(AV

GND − 0.05 AV

+ 0.05 V

7 μA/V

±0.03 nA/V/°C External clock

analog inputs

)

4 V AVDD = 5 V, I

0.4 V AVDD = 5 V, I

0.8 V DVDD = 5 V

2.5 V DVDD = 3 V

INH

− 1.25 V)/gain when gain > 1

= 200 μA

SOURCE

= 800 μA

SINK

Rev. 0 | Page 4 of 44

AD7195

Parameter Min Typ Max Unit Test Conditions/Comments1

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Hysteresis2 0.1 0.25 V Input Currents −10 +10 μA

LOGIC OUTPUT (DOUT/

Output High Voltage, V Output Low Voltage, V Output High Voltage, V Output Low Voltage, V Floating-State Leakage

Current

Floating-State Output

Capacitance

Data Output Coding Offset binary

SYSTEM CALIBRATION2

Full-Scale Calibration Limit 1.05 × FS V Zero-Scale Calibration Limit −1.05 × FS V Input Span 0.8 × FS 2.1 × FS V

POWER REQUIREMENTS7

Power Supply Voltage AVDD − AGND 4.75 5.25 V DVDD − DGND 2.7 5.25 V Power Supply Currents AIDD Current 0.85 1 mA gain = 1, buffer off

1.1 1.3 mA gain = 1, buffer on

3.5 4.5 mA gain = 8, buffer off 4 5 mA gain = 8, buffer on 5 6.4 mA gain = 16 to 128, buffer off

5.5 6.9 mA gain = 16 to 128, buffer on DIDD Current 0.35 0.4 mA DVDD = 3 V

0.5 0.6 mA DVDD = 5 V

1.5 mA External crystal used

IDD (Power-Down Mode) 2 μA

Temperature range: −40°C to +105°C.

Specification is not production tested, but is supported by characterization data at initial product release.

FS is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register.

Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full-

scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.

The analog inputs are configured for differential mode.

REJ60 is a bit in the mode register. When the output data rate is set to 50 Hz, setting REJ60 to 1 places a notch at 60 Hz, allowing simultaneous 50 Hz/60 Hz rejection.

Digital inputs equal to DVDD or DGND.

2 V

INH

0.8 V

INL

RDY

)

DVDD − 0.6 V DVDD = 3 V, I

0.4 V DVDD = 3 V, I

4 V DVDD = 5 V, I

0.4 V DVDD = 5 V, I

−10 +10 μA

10 pF

SOURCE

= 100 μA

SINK

SOURCE

= 1.6 mA

SINK

= 100 μA

= 200 μA

Rev. 0 | Page 5 of 44

AD7195

TIMING CHARACTERISTICS

AVDD = 4.75 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.

Table 2.

Parameter Limit at T

MIN

, T

(B Version) Unit Conditions/Comments

MAX

1, 2

READ AND WRITE OPERATIONS

t3 100 ns min SCLK high pulse width t4 100 ns min SCLK low pulse width

READ OPERATION

t1 0 ns min

falling edge to DOUT/RDY active time

CS 60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V

0 ns min SCLK active edge to data valid delay4

60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V

5, 6

10 ns min

Bus relinquish time after CS

inactive edge

80 ns max

t6 0 ns min t7 10 ns min

SCLK inactive edge to CS

SCLK inactive edge to DOUT/RDY

inactive edge

high

WRITE OPERATION

t8 0 ns min

falling edge to SCLK active edge setup time4

t9 30 ns min Data valid to SCLK edge setup time t10 25 ns min Data valid to SCLK edge hold time t11 0 ns min

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.

See Figure 3 and Figure 4.

These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.

The SCLK active edge is the falling edge of SCLK.

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number

is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.

RDY

returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once.

rising edge to SCLK edge hold time

RDY

Rev. 0 | Page 6 of 44

AD7195

Circuit and Timing Diagram

(1.6mA WITH DVDD = 5V,

SINK

100µA WIT H DV

OUTPUT

50pF

SOURCE

100µA WIT H DV

Figure 2. Load Circuit for Timing Characterization

CS (I)

DOUT/RDY (O)

SCLK (I)

I = INPUT, O = OUTPUT

MSB LSB

Figure 3. Read Cycle Timing Diagram

= 3V)

1.6V

(200µA WIT H DVDD = 5V,

= 3V)

8771-002

8771-003

CS (I)

8771-004

CLK (I)

DIN (I)

I = INPUT, O = OUT PUT

MSB LSB

Figure 4. Write Cycle Timing Diagram

Rev. 0 | Page 7 of 44

AD7195

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to AGND DVDD to AGND

AGND to DGND

Analog Input Voltage to AGND

Reference Input Voltage to AGND

Digital Input Voltage to DGND

Digital Output Voltage to DGND

AIN/Digital Input Current 10 mA Operating Temperature Range

Storage Temperature Range Maximum Junction Temperature 150°C

Lead Temperature, Soldering

Reflow 260°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

−0.3 V to +6.5 V

−0.3 V to +0.3 V

−0.3 V to AVDD + 0.3 V

−0.3 V to DVDD + 0.3 V

−40°C to +105°C

−65°C to +150°C

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θJA θ

32-Lead LFCSP_WQ 32.5 32.71 °C/W

Unit

ESD CAUTION

Rev. 0 | Page 8 of 44

AD7195

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SCLK

MCLK2NCDOUT/RDY

DIN

MCLK1

CS 32313029282726

ACX2

ACX1 ACX1 AV

AGND

AINCOM

NOTES

1. NC = NO CONNECT.

2. CONNECT EX P OSED PAD TO AGND.

4 5 6 7 8

AD7195

TOP VIEW

(Not to Scale)

10111213141516

AIN2

AIN1

Figure 5.Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 ACX2

Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac excited bridge applications. In ac mode, ACX2 toggles in anti-phase with ACX1. If the ACX bit equals zero (ac

excitation turned off), the ACX2 output remains low. When toggling, it is guaranteed to be nonoverlapping

with ACX1. The nonoverlap interval between ACX1 and ACX2 is 1/(master clock) which is equal to 200 ns when a 4.92 MHz clock is used.

Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac

ACX2

excited bridge applications. This output is the inverse of ACX2. If the ACX bit equals zero (ac excitation turned

off), the ACX2 output remains high.

3 ACX1

Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac excited bridge applications. When ACX1 is high, the bridge excitation is taken as normal and when ACX1 is low, the bridge excitation is reversed (chopped). If the Bit ACX equals zero (ac excitation turned off), the ACX1 output remains high.

Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac

ACX1

excited bridge applications. This output is the inverse of ACX1. When ACX1 is low, the bridge excitation is taken as normal and when ACX1 is high, the bridge excitation is reversed (chopped). If the ACX bit equals

zero (ac excitation turned off), the ACX1 5 AVDD Analog Supply Voltage, 4.75 V to 5.25 V. AVDD is independent of DVDD. 6 AGND Analog Ground Reference Point. 7 NC No Connect. This pin should be tied to AGND. 8 AINCOM Analog inputs AIN1 to AIN4 are referenced to this input when configured for pseudo differential operation. 9 AIN1

Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with

AIN2 or as a pseudo differential input when used with AINCOM. 10 AIN2

Analog Input. This pin can be configured as the negative input of a fully differential input pair when used

with AIN1 or as a pseudo differential input when used with AINCOM. 11 NC No Connect. This pin should be tied to AGND. 12 NC No Connect. This pin should be tied to AGND. 13 NC No Connect. This pin should be tied to AGND. 14 NC No Connect. This pin should be tied to AGND. 15 AIN3

Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with

AIN4 or as a pseudo differential input when used with AINCOM. 16 AIN4

Analog Input. This pin can be configured as the negative input of a fully differential input pair when used

with AIN3 or as a pseudo differential input when used with AINCOM. 17 REFIN(+)

Positive Reference Input. An external reference can be applied between REFIN(+) and REFIN(−). REFIN(+) can

lie anywhere between AV

and AGND + 1 V. The nominal reference voltage, (REFIN(+) − REFIN(−)), is AVDD,

but the part functions with a reference from 1 V to AV 18 REFIN(−) Negative Reference Input. This reference input can lie anywhere between AGND and AVDD − 1 V. 19 NC No Connect. This pin should be tied to AGND.

Rev. 0 | Page 9 of 44

SYNC

DGND AGND

21 20

BPDSW NC

REFIN(–)

REFIN(+)

AIN3

AIN4

08771-005

output remains low.

AD7195

Pin No. Mnemonic Description

20 BPDSW Bridge Power-Down Switch to AGND. 21 AGND Analog Ground Reference Point. 22 DGND Digital Ground Reference Point. 23 AVDD Analog Supply Voltage, 4.75 V to 5.25 V. AVDD is independent of DVDD. 24 DVDD Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. 25

26 NC No Connect. This pin should be tied to AGND. 27

28 DIN

29 MCLK1

30 MCLK2

31 SCLK

Logic input that allows for synchronization of the digital filters and analog modulators when using a number

SYNC

of AD7195 devices. While SYNC calibration control logic are reset, and the analog modulator is also held in its reset state. SYNC does not affect the digital interface but does reset RDY to DV

DOUT/RDY

Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in

Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output

pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY data is available. With an external serial clock, the data can be read using the DOUT/RDY data-/control-word information is placed on the DOUT/RDY SCLK rising edge.

Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers in the ADC, with the register selection bits of the communications register identifying the appropriate register.

When the master clock for the device is provided externally by a crystal, the crystal is connected between MCLK1 and MCLK2.

Master Clock Signal for the Device. The AD7195 has an internal 4.92 MHz clock. This internal clock can be made available on the MCLK2 pin. The clock for the AD7195 can be provided externally also in the form of a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin can be driven with a CMOS-compatible clock and the MCLK1 pin left unconnected.

Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitttriggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information transmitted to or from the ADC in smaller batches of data.

systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device.

is low, the nodes of the digital filter, the filter control logic, and the

to a high state if it is low. SYNC has a pull-up resistor internally

falling edge can be used as an interrupt to a processor, indicating that valid

pin on the SCLK falling edge and is valid on the

pin. With CS low, the

Rev. 0 | Page 10 of 44

AD7195

TYPICAL PERFORMANCE CHARACTERISTICS

8,388,760

8,388,758

8,388,756

8,388,754

CODE

8,388,752

8,388,750

8,388,748

8,388,746

0 200 400 600 800 1000

Figure 6. Noise (V

= 5 V, Output Data Rate = 4.7 Hz, Gain = 128,

REF

Chop Disabled, Sinc

250

200

150

100

FREQUENCY

8,388,746

8,388,748

Figure 7. Noise Distribution Histogram (V

8,388,750

SAMPLE

8,388,752

CODE

Filter)

8,388,754

8,388,756

REF

8,388,758

= 5 V,

Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc4 Filter)

8,388,950

8,388,900

8,388,850

8,388,800

8,388,750

8,388,700

CODE

8,388,650

8,388,600

8,388,550

8,388,500

8,388,450

0 200 400 600 800 1000100 300 500 700 900

Figure 8. Noise (V

= 5 V, Output Data Rate = 4800 Hz, Gain = 128,

REF

Chop Disabled, Sinc

SAMPLES

Filter)

8,388,760

FREQUENCY

8,388,490 8,388,576 8,388,662 8,388,748 8,388,834 8,388,920

08771-006

Figure 9. Noise Distribution Histogram (V

CODE

REF

= 5 V,

08771-009

Output Data Rate = 4800 Hz, Gain = 128, Chop Disabled, Sinc4 Filter)

8,388,820

8,388,800

8,388,780

8,388,760

8,388,740

8,388,720

CODE

8,388,700

8,388,680

8,388,660

8,388,640

8,388,620

0 200 400 600 800 1000100 300 500 700 900

08771-007

Figure 10. Noise (V

= 5 V, Output Data Rate = 4800 Hz, Gain = 1,

REF

Chop Disabled, Sinc

FREQUENCY

8,388,620 8,388,660 8,388,700 8,388,740 8,388,780 8,388,820

08771-008

Figure 11. Noise Distribution Histogram (V

Output Data Rate = 4800 Hz, Gain = 1, Chop Disabled, Sinc

SAMPLES

CODE

Filter)

REF

= 5 V,

Filter)

08771-010

08771-011

Rev. 0 | Page 11 of 44

AD7195

3.0

2.0

1.0

INL (ppm of FSR)

–1.0

–2.0

–3.0

–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5

VIN (V)

Figure 12. INL (Gain = 1)

INL (ppm of FSR)

–2

–4

–0.1

–0.2

–0.3

–0.4

OFFSET (µV)

–0.5

–0.6

–0.7

–60 –40 –20 0 20 40 60 80 100 120

08771-012

TEMERATURE (°C)

08771-015

Figure 15. Offset Error (Gain = 128, Chop Disabled)

1.000008

1.000007

1.000006

1.000005

1.000004

GAIN

1.000003

1.000002

1.000001

–6 –0.020 –0.015 –0.010 –0.005 0 0.005 0.010 0.015 0.020

VIN (V)

Figure 13. INL (Gain = 128)

OUTPUT VO LTAGE (µ V )

–60 –40 –20 0 20 40 60 80 100 120 140

TEMPERATURE ( °C)

Figure 14. Offset Error (Gain = 1, Chop Disabled)

1.000000 –60 –40 –20 0 20 40 60 80 100 120

08771-013

TEMPERATURE ( °C)

08771-016

Figure 16. Gain Error (Gain = 1, Chop Disabled)

128.003

128.002

128.001

128.000

GAIN

127.999

127.998

127.997

127.996 –60 –40 –20 0 20 40 60 80 100 120

08771-014

TEMPERATURE ( °C)

08771-017

Figure 17. Gain Error (Gain = 128, Chop Disabled)

Rev. 0 | Page 12 of 44

AD7195

RMS NOISE AND RESOLUTION

The tables in this section show the rms noise, peak-to-peak noise, effective resolution, and noise-free (peak-to-peak) resolution of the AD7195 for various output data rates and gain settings, with chop disabled and chop enabled for the sinc

and sinc3 filters. The numbers given are for the bipolar input range with the external 5 V reference. These numbers are typical and are

SINC4 CHOP DISABLED

Table 6. RMS Noise (nV) vs. Gain and Output Data Rate

Filter Wo rd (Decimal)

1023 4.7 852.5 280 96 50 22 10 8.5 640 7.5 533 390 120 54 28 12 10.5 480 10 400 470 130 56 31 14 11.5 96 50 80 1000 150 78 45 33 28 80 60 66.7 1100 170 88 52 36 31 32 150 26.7 1460 220 125 75 55 48 16 300 13.3 1900 285 170 100 75 67 5 960 4.17 3000 480 280 175 140 121 2 2400 1.67 5000 780 440 280 220 198 1 4800 0.83 14,300 1920 1000 550 380 295

Output Data Rate (Hz)

Settling Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

generated with a differential input voltage of 0 V when the ADC is continuously converting on a single channel. It is important to note that the effective resolution is calculated using the rms noise, whereas the peak-to-peak resolution is calculated based on peak-to-peak noise. The peak-to-peak resolution represents the resolution for which there is no code flicker.

Table 7. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate

Filter Wo rd (Decimal)

1023 4.7 852.5 1600 500 250 130 65 56 640 7.5 533 2200 650 290 150 80 65 480 10 400 3000 670 300 190 100 70 96 50 80 6000 900 450 280 180 170 80 60 66.7 7200 1100 480 300 220 190 32 150 26.7 8300 1500 750 410 340 310 16 300 13.3 11,000 1700 1000 600 440 430 5 960 4.17 20,000 3000 1800 1100 810 710 2 2400 1.67 32,000 5100 2800 1700 1400 1200 1 4800 0.83 86,000 13,000 6000 3500 2400 1900

Output Data Rate (Hz)

Settling Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

Table 8. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate

Filter Wo rd (Decimal)

1023 4.7 852.5 24 (22.6) 23.6 (21.3) 23.6 (21.3) 23.6 (21.2) 23.6 (21.2) 23.1 (20.4) 640 7.5 533 24 (22.1) 23.4 (20.9) 23.4 (20.9) 23.4 (20.9) 23.4 (20.9) 22.8 (20.2) 480 10 400 24 (21.7) 23.3 (20.8) 23.3 (20.8) 23.3 (20.8) 23.3 (20.6) 22.7 (20.1) 96 50 80 23.3 (20.7) 23 (20.4) 22.9 (20.4) 22.7 (20.1) 22.2 (19.7) 21.4 (18.8) 80 60 66.7 23.1 (20.4) 22.8 (20.1) 22.8 (20) 22.5 (20 ) 22.1 (19.4) 21.3 (18.6) 32 150 26.7 22.7 (20.2) 22.4 (19.7) 22.3 (19.7) 22 (19.5) 21.5 (18.8) 20.6 (17.9) 16 300 13.3 22.3 (19.8) 22.1 (19.5) 21.8 (19.3) 21.6 (19) 21 (18.4) 20.1 (17.5) 5 960 4.17 21.7 (18.9) 21.3 (18.7) 21.1 (18.4) 20.8 (18.1) 20.2 (17.6) 19.3 (16.7) 2 2400 1.67 20.9 (18.3) 20.6 (17.9) 20.4 (17.7) 20.1 (17.5) 19.5 (16.8) 18.6 (16) 1 4800 0.83 19.4 (16.8) 19.3 (16.6) 19.3 (16.4) 19.1 (16.4) 18.8 (16) 18 (15.3)

The output peak-to-peak (p-p) resolution is listed in parentheses.

Output Data Rate (Hz)

Settling Time (ms)

Gain of 1

Gain of 81 Gain of 161 Gain of 321 Gain of 641 Gain of 1281

Rev. 0 | Page 13 of 44

AD7195

SINC3 CHOP DISABLED

Table 9. RMS Noise (nV) vs. Gain and Output Data Rate

Filter Wo rd (Decimal)

1023 4.7 639.4 290 125 53 24 10.5 9 640 7.5 400 470 135 56 29 13 11.5 480 10 300 610 145 58 32 16 12.5 96 50 60 1100 160 86 50 35 29 80 60 50 1200 170 95 55 40 32 32 150 20 1500 230 130 80 58 50 16 300 10 1950 308 175 110 83 73 5 960 3.13 4000 590 330 200 150 133 2 2400 1.25 56,600 7000 3500 1800 900 490 1 4800 0.625 442,000 55,000 28,000 14,000 7000 3450

Table 10. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate

Filter Wo rd (Decimal)

1023 4.7 639.4 1700 750 260 140 65 56 640 7.5 400 2400 800 340 150 84 60 480 10 300 3000 900 360 200 100 70 96 50 60 6600 1000 480 290 200 180 80 60 50 6800 1100 600 300 240 200 32 150 20 8900 1400 710 470 360 310 16 300 10 13,000 2000 1000 670 470 500 5 960 3.13 25,000 3400 2200 1200 850 800 2 2400 1.25 310,000 41,000 22,000 12,000 5600 3100 1 4800 0.625 2,600,000 300,000 170,000 79,000 41,000 24,000

Output Data Rate (Hz)

Settling Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

Table 11. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate

Filter Wo rd (Decimal)

Output Data Rate (Hz)

Settling Time (ms)

Gain of 1

Gain of 81 Gain of 161 Gain of 321 Gain of 641 Gain of 1281

1023 4.7 639.4 24 (22.5) 23.5 (21) 23.5 (21) 23.5 (21) 23.5 (21) 23 (20.4) 640 7.5 400 24 (22) 23.3 (20.8) 23.3 (20.8) 23.3 (20.8) 23.3 (20.8) 22.7 (20.3) 480 10 300 24 (22) 23.2 (20.5) 23.2 (20.5) 23.2 (20.5) 23.2 (20.5) 22.6 (20.1) 96 50 60 23.1 (20.5) 22.9 (20.3) 22.8 (20.3) 22.6 (20) 22.1 (19.6) 21.4 (18.7) 80 60 50 23 (20.5) 22.8 (20.1) 22.6 (20) 22.4 (20) 21.9 (19.3) 21.2 (18.6) 32 150 20 22.7 (20) 22.4 (19.8) 22.2 (19.7) 21.9 (19.3) 21.4 (18.7) 20.6 (17.9) 16 300 10 22.3 (19.5) 22 (19.3) 21.8 (19.3) 21.4 (18.8) 20.8 (18.3) 20 (17.3) 5 960 3.13 21.3 (18.5) 21 (18.5) 20.9 (18.1) 20.6 (18) 20 (17.5) 19.2 (16.6) 2 2400 1.25 17.4 (14.9) 17.4 (14.9) 17.4 (14.8) 17.4 (14.7) 17.4 (14.7) 17.3 (14.6) 1 4800 0.625 14.5 (11.9) 14.5 (11.9) 14.4 (11.8) 14.4 (11.8) 14.4 (11.8) 14.4 (11.7)

The output peak-to-peak (p-p) resolution is listed in parentheses.

Rev. 0 | Page 14 of 44

AD7195

SINC4 CHOP ENABLED

Table 12. RMS Noise (nV) vs. Gain and Output Data Rate

Filter Wo rd (Decimal)

1023 1.175 1702 198 85 41 18 7 6 640 1.875 1067 276 92 45 22 8.5 7 480 2.5 800 332 99 46 23 10 8 96 12.5 160 707 127 61 34 23 18 80 15 133 778 141 62 35 24 21 32 37.5 53.3 990 156 85 51 38 33 16 75 26.7 1344 191 106 67 51 45 5 240 8.33 2192 325 184 120 92 78 2 600 3.33 3606 523 297 191 148 134 1 1200 1.67 9900 1345 680 368 248 200

Table 13. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate

Filter Wo rd (Decimal)

1023 1.175 1702 1131 474 212 92 46 40 640 1.875 1067 1556 495 248 106 57 46 480 2.5 800 2121 530 255 134 71 50 96 12.5 160 4243 707 368 198 127 120 80 15 133 5091 849 424 212 156 134 32 37.5 53.3 5870 1061 530 290 240 219 16 75 26.7 7780 1202 707 424 311 304 5 240 8.33 14,142 2121 1273 778 573 502 2 600 3.33 22,627 3606 1980 1202 990 850 1 1200 1.67 60,800 9192 4950 2475 1697 1345

Output Data Rate (Hz)

Settling Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

Settling Time (ms)

Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

Table 14. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate

Filter Wo rd (Decimal)

Output Data Rate (Hz)

Settling Time (ms) Gain of 1

Gain of 81 Gain of 161 Gain of 321 Gain of 641 Gain of 1281

1023 1.175 1702 24 (23.1) 24 (21.8) 24 (21.8) 24 (21.7) 24 (21.7) 23.6 (20.9) 640 1.875 1067 24 (22.6) 23.9 (21.4) 23.9 (21.4) 23.9 (21.4) 23.9 (21.4) 23.3 (20.7) 480 2.5 800 24 (22.2) 23.8 (21.3) 23.8 (21.3) 23.8 (21.3) 23.8 (21.1) 23.2 (20.6) 96 12.5 160 23.8 (21.2) 23.5 (20.9) 23.4 (20.9) 23.2 (20.6) 22.7 (20.2) 21.9 (19.3) 80 15 133 23.6 (20.9) 23.3 (20.6) 23.3 (20.5) 23 (20.5) 22.6 (19.9) 21.8 (19.1) 32 37.5 53.3 23.2 (20.7) 22.9 (20.2) 22.8 (20.2) 22.5 (20) 22 (19.3) 21.1 (18.4) 16 75 26.7 22.8 (20.3) 22.6 (20) 22.3 (19.8) 22.1 (19.5) 21.5 (18.9) 20.6 (18) 5 240 8.33 22.2 (19.4) 21.8 (19.2) 21.6 (18.9) 21.3 (18.6) 20.7 (18.1) 19.8 (17.2) 2 600 3.33 21.4 (18.8) 21.1 (18.4) 20.9 (18.2) 20.6 (18) 20 (17.3) 19.1 (16.5) 1 1200 1.67 19.9 (17.3) 19.8 (17.1) 19.8 (16.9) 19.6 (16.9) 19.3 (16.5) 18.5 (15.8)

The output peak-to-peak (p-p) resolution is listed in parentheses.

When ac excitation is enabled, the rms noise and resolution is the same as for chop enabled mode.

Rev. 0 | Page 15 of 44

AD7195

SINC3 CHOP ENABLED

Table 15. RMS Noise (nV) vs. Gain and Output Data Rate

Filter Wo rd (Decimal)

1023 1.56 1282 205 88 37 17 7.5 6.5 640 2.5 800 332 95 40 21 9 8 480 3.33 600 431 103 41 23 11.5 9 96 16.6 120 778 113 61 35 25 21 80 20 100 849 120 67 39 28 23 32 50 40 1061 163 92 57 41 35 16 100 20 1379 218 124 78 59 52 5 320 6.25 2828 417 233 141 106 94 2 800 2.5 40,022 4950 2475 1273 636 346 1 1600 1.25 312,540 38,890 19,800 9900 4950 2440

Table 16. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate

Filter Wo rd (Decimal)

1023 1.56 1282 1202 530 184 92 46 40 640 2.5 800 1697 566 240 120 59 42 480 3.33 600 2121 636 255 141 71 49 96 16.6 120 4667 686 318 198 141 127 80 20 100 4808 707 424 205 170 141 32 50 40 6293 990 474 382 255 219 16 100 20 9192 1414 707 474 332 354 5 320 6.25 17,680 2404 1556 849 601 566 2 800 2.5 219,200 29,000 15,560 8485 3960 2192 1 1600 1.25 1,838,500 212,200 120,200 55,870 29,000 16,970

Output Data Rate (Hz)

Settling Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

Settling Time (ms)

Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

Table 17. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate

Filter Wo rd (Decimal)

Output Data Rate (Hz)

Settling Time (ms)

Gain of 1

Gain of 81 Gain of 161 Gain of 321 Gain of 641 Gain of 1281

1023 1.56 1282 24 (23) 24 (21.5) 24 (21.5) 24 (21.5) 24 (21.5) 23.5 (20.9) 640 2.5 800 24 (22.5) 23.8 (21.3) 23.8 (21.3) 23.8 (21.3) 23.8 (21.3) 23.2 (20.8) 480 3.33 600 24 (22.5) 23.7 (21) 23.7 (21) 23.7 (21) 23.7 (21) 23.1 (20.6) 96 16.6 120 23.6 (21) 23.4 (20.8) 23.3 (20.8) 23.1 (20.5) 22.6 (20.1) 21.9 (19.2) 80 20 100 23.5 (21) 23.3 (20.6) 23.1 (20.5) 22.9 (20.5) 22.4 (19.8) 21.7 (19.1) 32 320 40 23.2 (20.5) 22.9 (20.3) 22.7 (20.2) 22.4 (19.8) 21.9 (19.2) 21.1 (18.4) 16 100 20 22.8 (20) 22.5 (19.8) 22.3 (19.8) 21.9 (19.3) 21.3 (18.8) 20.5 (17.8) 5 320 6.25 21.8 (19) 21.5 (19) 21.4 (18.6) 21.1 (18.5) 20.5 (18) 19.7 (17.1) 2 800 2.5 17.9 (15.4) 17.9 (15.4) 17.9 (15.3) 17.9 (15.2) 17.9 (15.2) 17.8 (15.1) 1 1600 1.25 15 (12.4) 15 (12.4) 14.9 (12.3) 14.9 (12.3) 14.9 (12.3) 14.9 (12.2)

The output peak-to-peak (p-p) resolution is listed in parentheses.

When ac excitation is enabled, the rms noise and resolution is the same as for chop enabled mode.

Rev. 0 | Page 16 of 44

AD7195

ON-CHIP REGISTERS

The ADC is controlled and configured via a number of on-chip registers described on the following pages. In the following descriptions, the term set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise noted.

Table 18. Register Summary

Communications 00 W 00

Status 00 R 80

Mode 01 R/W 080060 Mode select DAT_STA CLK1 CLK0 0 0 SINC3 0 ENPAR 0 SINGLE REJ60 FS9 FS8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0 (LSB) Configuration 02 R/W 000117 Chop (MSB) ACX 0 0 0 0 0 0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 BURN REFDET 0 BUF

Data 03 R 000000 D23 (MSB) D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) ID 04 R A6 1 0 1 0 0 1 1 0 GPOCON 05 R/W 00 0 BPDSW 0 0 0 0 0 0 Offset 06 R/W 800000 OF23 (MSB) OF22 OF21 OF20 OF19 OF18 OF17 OF16 OF15 OF14 OF13 OF12 OF11 OF10 OF9 OF8 OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0 (LSB) Full Scale 07 R/W 5XXXX0 FS23 (MSB) FS22 FS21 FS20 FS19 FS18 FS17 FS16 FS15 FS14 FS13 FS12 FS11 FS10 FS9 FS8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0 (LSB)

R/W

WEN

RDY

ERR NOREF PARITY 0 CHD2 CHD1 CHD0

U/B

CREAD 0 0

G2 G1 G0 (LSB)

Rev. 0 | Page 17 of 44

AD7195

COMMUNICATIONS REGISTER

(RS2, RS1, RS0 = 0, 0, 0)

The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register. The data written to the communications register determines whether the next operation is a read or a write operation and in which register this operation takes place. For read or write operations, when the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the communications register. This is the default

CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0

WEN(0) R/W(0)

Table 19. Communications Register Bit Designations

Bit Location Bit Name Description

CR7

CR6

CR5 to CR3 RS2 to RS0

CR2 CREAD

CR1 to CR0 0 These bits must be programmed to Logic 0 for correct operation.

Write enable bit. For a write to the communications register to occur, 0 must be written to this bit. If a 1 is

WEN

A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position

R/W

RS2(0) RS1(0) RS0(0) CREAD(0) 0 0

the first bit written, the part does not clock on to subsequent bits in the register; rather, it stays at this bit location until a 0 is written to this bit. After a 0 is written to the WEN the communications register. Idling the DIN pin high between data transfers minimizes the effects of spurious SCLK pulses on the serial interface.

indicates that the next operation is a read from the designated register. Register address bits. These address bits are used to select which registers of the ADC are selected during

the serial interface communication (see Tabl e 20). Continuous read of the data register. When this bit is set to 1 (and the data register is selected), the serial

interface is configured so that the data register can be continuously read; that is, the contents of the data register are automatically placed on the DOUT pin when the SCLK pulses are applied after the RDY goes low to indicate that a conversion is complete. The communications register does not have to be written to for subsequent data reads. To enable continuous read, the Instruction 01011100 must be written to the communications register. To disable continuous read, the Instruction 01011000 must be written to the communications register while the RDY activity on the DIN line so that it can receive the instruction to disable continuous read. Additionally, a reset occurs if 40 consecutive 1s are seen on DIN. Therefore, hold DIN low until an instruction is written to the device.

state of the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications register. In situations where the interface sequence is lost, a write operation of at least 40 serial clock cycles with DIN high returns the ADC to this default state by resetting the entire part. Tabl e 19 outlines the bit designations for the communications register. CR0 through CR7 indicate the bit location, CR denoting that the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit.

bit, the next seven bits are loaded to

pin is low. While continuous read is enabled, the ADC monitors

Table 20. Register Selection

RS2 RS1 RS0 Register Register Size

0 0 0 Communications register during a write operation 8 bits 0 0 0 Status register during a read operation 8 bits 0 0 1 Mode register 24 bits 0 1 0 Configuration register 24 bits 0 1 1 Data register/data register plus status information 24 bits/32 bits 1 0 0 ID register 8 bits 1 0 1 GPOCON register 8 bits 1 1 0 Offset register 24 bits 1 1 1 Full-scale register 24 bits

Rev. 0 | Page 18 of 44

AD7195

STATUS REGISTER

(RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80)

The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Ta b le 2 1 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, SR denoting that the bits are in the status register. SR7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit.

SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

RDY(1)

Table 21. Status Register Bit Designations

Bit Location Bit Name Description

SR7

SR6 ERR

SR5 NOREF

SR4 PARITY

SR3 0 This bit is set to 0. SR2 to SR0

ERR(0) NOREF(0) PARITY(0) 0 CHD2(0) CHD1(0) CHD0(0)

Ready bit for the ADC. This bit is cleared when data is written to the ADC data register. The RDY bit is set

RDY

automatically after the ADC data register is read, or a period of time before the data register is updated, with a new conversion result to indicate to the user that the conversion data should not be read. It is also

CHD2 to CHD0

set when the part is placed in power-down mode or idle mode or when SYNC conversion is also indicated by the DOUT/RDY pin. This pin can be used as an alternative to the status register for monitoring the ADC for conversion data.

ADC error bit. This bit is written to at the same time as the RDY written to the ADC data register is clamped to all 0s or all 1s. Error sources include overrange or under-

range, or the absence of a reference voltage. This bit is cleared when the result written to the data register is within the allowed analog input range again.

No external reference bit. This bit is set to indicate that the reference is at a voltage that is below a specified threshold. When set, conversion results are clamped to all 1s. This bit is cleared to indicate that a valid reference is applied to the selected reference pins. The NOREF bit is enabled by setting the REFDET bit in the configuration register to 1.

Parity check of the data register. If the ENPAR bit in the mode register is set, the PARITY bit is set if there is an odd number of 1s in the data register. It is cleared if there is an even number of 1s in the data register. The DAT_STA bit in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the contents of the status register are transmitted along with the data for each data register read.

These bits indicate which channel corresponds to the data register contents. They do not indicate which channel is presently being converted but indicate which channel was selected when the conversion contained in the data register was generated.

bit. This bit is set to indicate that the result

is taken low. The end of a

MODE REGISTER

(RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x080060)

The mode register is a 24-bit register from which data can be read or to which data can be written. This register is used to select the operating mode, the output data rate, and the clock source. Ta b le 22 outlines the bit designations for the mode register. MR0 through MR23 indicate the bit locations, MR denoting that the bits are in the mode register. MR23 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. Any write to the mode register resets the modulator and filter and sets the

MR23 MR22 MR21 MR20 MR19 MR18 MR17 MR16 MD2(0) MD1(0) MD0(0) DAT_STA(0) CLK1(1) CLK0(0) 0 0 MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8

SINC3(0) 0 ENPAR(0) 0 SINGLE(0) REJ60(0) FS9(0) FS8(0)

MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0

FS7(0) FS6(1) FS5(1) FS4(0) FS3(0) FS2(0) FS1(0) FS0(0)

RDY

bit.

Rev. 0 | Page 19 of 44

AD7195

Table 22. Mode Register Bit Designations

Bit Location Bit Name Description MR23 to MR21 MD2 to MD0 Mode select bits. These bits select the operating mode of the AD7195 (see Table 23). MR20 DAT_STA

MR19, MR18 CLK1, CLK0

MR17, MR16 0 These bits must be programmed with a Logic 0 for correct operation. MR15 SINC3

MR14 0 This bit must be programmed with a Logic 0 for correct operation. MR13 ENPAR

MR12 0 This bit must be programmed with a Logic 0 for correct operation. MR11 SINGLE

MR10 REJ60

MR9 to MR0 FS9 to FS0

This bit enables the transmission of status register contents after each data register read. When DAT_STA is set, the contents of the status register are transmitted along with each data register read. This function is useful when several channels are selected because the status register identifies the channel to which the data register value corresponds.

These bits select the clock source for the AD7195. Either the on-chip 4.92 MHz clock or an external clock can be used. The ability to use an external clock allows several AD7195 devices to be synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7195.

CLK1 CLK0 ADC Clock Source

0 0 External crystal. The external crystal is connected from MCLK1 to MCLK2. 0 1 External clock. The external clock is applied to the MCLK2 pin. 1 0 Internal 4.92 MHz clock. Pin MCLK2 is tristated. 1 1 Internal 4.92 MHz clock. The internal clock is available on MCLK2.

filter select bit. When this bit is cleared, the sinc4 filter is used (default value). When this bit is set,

Sinc

the sinc For a given output data rate, f settling time of 4/f

filter is used. The benefit of the sinc3 filter compared to the sinc4 filter is its lower settling time.

, the sinc3 filter has a settling time of 3/f

when chop is disabled. The sinc4 filter, due to its deeper notches, gives better

ADC

while the sinc4 filter has a

ADC

50 Hz/60 Hz rejection. At low output data rates, both filters give similar rms noise and similar no missing codes for a given output data rate. At higher output data rates (FS values less than 5), the

sinc

filter gives better performance than the sinc3 filter for rms noise and no missing codes.

Enable parity bit. When ENPAR is set, parity checking on the data register is enabled. The DAT_STA bit in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the contents of the status register are transmitted along with the data for each data register read.

Single cycle conversion enable bit. When this bit is set, the AD7195 settles in one conversion cycle so that it functions as a zero-latency ADC. This bit has no effect when multiple analog input channels are enabled or when the single conversion mode is selected.

This bit enables a notch at 60 Hz when the first notch of the sinc filter is at 50 Hz. When REJ60 is set, a filter notch is placed at 60 Hz when the sinc filter first notch is at 50 Hz. This allows simultaneous 50 Hz/ 60 Hz rejection.

Filter output data rate select bits. The 10 bits of data programmed into these bits determine the filter cut-off frequency, the position of the first notch of the filter, and the output data rate for the part. In association with the gain selection, they also determine the output noise (and, therefore, the effective resolution) of the device (see Table 6 through Table 1 7 ). When chop is disabled and continuous conversion mode is selected,

Output Data Rate = (MCLK/1024)/FS where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 and is in the range 1 to 1023, and MCLK is the master clock frequency. With a nominal MCLK of 4.92 MHz, this results in an output data rate from 4.69 Hz to 4.8 kHz. With chop disabled, the first notch frequency is equal to the output data

rate when converting on a single channel. When chop is enabled,

Output Data Rate = (MCLK/1024)/(N × FS) where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 and is in the range 1 to 1023, and MCLK is the master clock frequency. With a nominal MCLK of 4.92 MHz, this results in a conversion rate

from 4.69/N Hz to 4.8/N kHz, where N is the order of the sinc filter. The sinc filter’s first notch frequency is equal to N × output data rate. The chopping introduces notches at odd integer multiples of (output data rate/2).

Rev. 0 | Page 20 of 44

AD7195

Table 23. Operating Modes

MD2 MD1 MD0 Mode

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. The DOUT/RDY go low when a conversion is complete. The user can read these conversions by setting the CREAD bit in the communications register to 1, which enables continuous read. When continuous read is enabled, the conversions are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output each conversion by writing to the communications register. After power-on, a reset, or a reconfiguration of the ADC, the complete settling time of the filter is required to generate the first valid conversion. Subsequent conversions are available at the selected output data rate, which is dependent on filter choice.

Single conversion mode. When single conversion mode is selected, the ADC powers up and performs a single conversion on the selected channel. The internal clock requires up to 1 ms to power up and settle. The ADC then performs the conversion, which requires the complete settling time of the filter. The conversion result is placed in the data register. RDY

Idle mode. In idle mode, the ADC filter and modulator are held in a reset state even though the modulator clocks are still provided.

Power-down mode. In power-down mode, all AD7195 circuitry, except the bridge power-down switch, is powered down. The bridge power-down switch remains active because the user may need to power up the sensor prior to powering up the AD7195 for settling reasons. The external crystal, if selected, remains active.

Internal zero-scale calibration. An internal short is automatically connected to the input. RDY calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel.

Internal full-scale calibration. A full-scale input voltage is automatically connected to the input for this calibration. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is required each time the gain of a channel is changed to minimize the fullscale error.

System zero-scale calibration. The user should connect the system zero-scale input to the channel input pins as selected by the CH7 to CH0 bits in the configuration register. RDY returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. A system zero-scale calibration is required each time the gain of a channel is changed.

System full-scale calibration. The user should connect the system full-scale input to the channel input pins as selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is required each time the gain of a channel is changed.

goes low, and the ADC returns to power-down mode. The conversion remains in the data

remains active (low) until the data is read or another conversion

pin and the RDY bit in the status register

goes high when the

goes high when the calibration is initiated and

CONFIGURATION REGISTER

(RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x000117)

The configuration register is a 24-bit register from which data can be read or to which data can be written. This register is used to configure the ADC for unipolar or bipolar mode, to enable or disable the buffer, to enable or disable the burnout currents, to select the gain, and to select the analog input channel. Tab l e 24 outlines the bit designations for the filter register. CON0 through CON23 indicate the bit locations. CON denotes that the bits are in the configuration register. CON23 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit.

CON23 CON22 CON21 CON20 CON19 CON18 CON17 CON16 CHOP(0) ACX(0) 0 0 0 0 0 0 CON15 CON14 CON13 CON12 CON11 CON10 CON9 CON8

CH7(0) CH6(0) CH5(0) CH4(0) CH3(0) CH2(0) CH1(0) CH0(1)

CON7 CON6 CON5 CON4 CON3 CON2 CON1 CON0

BURN(0) REFDET(0) 0 BUF(1)

Rev. 0 | Page 21 of 44

U/B

(0)

G2(1) G1(1) G0(1)

AD7195

Table 24. Configuration Register Bit Designations

Bit Location Bit Name Description CON23 CHOP

CON22 ACX

CON21 to CON16 0 These bits must be programmed with a Logic 0 for correct operation. CON15 to CON8 CH7 to CH0

CON7 BURN

CON6 REFDET

CON5 0 This bit must be programmed with a Logic 0 for correct operation. CON4 BUF

CON3

CON2 to CON0 G2 to G0 Gain select bits. These bits are written by the user to select the ADC input range as follows:

Polarity select bit. When this bit is set, unipolar operation is selected. When this bit is cleared, bipolar

U/B

Chop enable bit. When the CHOP bit is cleared, chop is disabled. When the CHOP bit is set, chop is enabled. When chop is enabled, the offset and offset drift of the ADC are continuously removed. However, this increases the conversion time and settling time of the ADC. For example, when FS = 96 decimal and the sinc4 filter is selected, the conversion time with chop enabled equals 80 ms and the settling time equals 160 ms. With chop disabled, higher conversion rates are allowed. For an FS word of 96 decimal and the sinc4 filter selected, the conversion time is 20 ms and the settling time is 80 ms. However, at low gains, periodic calibrations may be required to remove the offset and offset drift. When ax excitation is enabled, chop must be enabled also.

AC excitation enable bit. If the signal source to the AD7195 is ac excited, this bit must be set to 1. For dc-excited inputs, this bit must be 0. With the ACX bit at 1, the AD7195 assumes that the voltage at the AIN(+)/AIN(–) and REFIN(+)/REFIN(–) input terminals are reversed on alternate input sampling cycles (that is, chopped). Note that when the AD7195 is performing internal zero-scale or full-scale calibrations, the ACX bit is treated as a 0, that is, the device performs these self-calibrations with dc excitation. TheBitCHOP must be set to 1 when ac excitation is enabled.

Channel select bits. These bits are used to select which channels are enabled on the AD7195 (see Tabl e 25). Several channels can be selected, and the AD7195 automatically sequences them. The conversion on each channel requires the complete settling time. When performing calibrations or when accessing the calibration registers, only one channel can be selected.

When this bit is set to 1, the 500 nA current sources in the signal path are enabled. When BURN = 0, the burnout currents are disabled. The burnout currents can be enabled only when the buffer is active and when chop is disabled.

Enables the reference detect function. When set, the NOREF bit in the status register indicates when the external reference being used by the ADC is open circuit or less than 0.6 V maximum. The reference detect circuitry operates only when the ADC is active.

Enables the buffer on the analog inputs. If cleared, the analog inputs are unbuffered, lowering the power consumption of the device. If this bit is set, the analog inputs are buffered, allowing the user to place source impedances on the front end without contributing gain errors to the system. With the buffer disabled, the voltage on the analog input pins can be from 50 mV below AGND to 50 mV above

. When the buffer is enabled, it requires some headroom; therefore, the voltage on any input pin

must be limited to 250 mV within the power supply rails.

operation is selected.

G2 G1 G0 Gain ADC Input Range (5 V Reference) 0 0 0 1 ±5 V 0 0 1 Reserved 0 1 0 Reserved 0 1 1 8 ±625 mV 1 0 0 16 ±312.5 mV 1 0 1 32 ±156.2 mV 1 1 0 64 ±78.125 mV 1 1 1 128 ±39.06 mV

Rev. 0 | Page 22 of 44

AD7195

Table 25. Channel Selection

Channel Enable Bits in the Configuration Register Channel Enabled

Positive Input

CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0

1 AIN1 AIN2 000 0 1 AIN3 AIN4 001 1 1 Temperature sensor 010 None 1 AIN2 AIN2 011 0 1 AIN1 AINCOM 100 0 1 AIN2 AINCOM 101 1 1 AIN3 AINCOM 110 2 1 AIN4 AINCOM 111 3

AIN(+)

DATA REGISTER

(RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x000000)

The conversion result from the ADC is stored in this data register. This is a read-only, 24-bit register. On completion of a read operation from this register, the

RDY

pin/bit is set. When the DAT_STA bit in the mode register is set to 1, the contents of the status register are appended to each 24-bit conversion. This is advisable when several analog input channels are enabled because the three LSBs of the status register (CHD2 to CHD0) identify the channel from which the conversion originated.

ID REGISTER

(RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0xA6)

The identification number for the AD7195 is stored in the ID register. This is a read-only register.

Negative Input AIN(−)

Status Register Bits CHD[2:0]

Calibration Register Pair

GPOCON REGISTER

(RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00)

The GPOCON register is an 8-bit register from which data can be read or to which data can be written. This register is used to enable the general-purpose digital outputs.

Tabl e 26 outlines the bit designations for the GPOCON register. GP0 through GP7 indicate the bit locations. GP denotes that the bits are in the GPOCON register. GP7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit.

GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0

0 BPDSW(0) 0 0 0 0 0 0

Table 26. Register Bit Designations

Bit Location Bit Name Description GP7 0 This bit must be programmed with a Logic 0 for correct operation. GP 6 BPDSW

GP5 to GP0 0 These bits must be programmed with a Logic 0 for correct operation.

Bridge power-down switch control bit. This bit is s BPDSW to AGND. The switch can sink up to 30 mA. The bit is cleared by the user to open the bridge powerdown switch. When the ADC is placed in power-down mode, the bridge power-down switch remains active.

et by the user to close the bridge power-down switch

Rev. 0 | Page 23 of 44

AD7195

OFFSET REGISTER

(RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x800000)

The offset register holds the offset calibration coefficient for the ADC. The power-on reset value of the offset register is 0x800000. The AD7195 has four offset registers; therefore, each channel has a dedicated offset register (see Ta b le 25 ). Each of these registers is a 24-bit read/write register. This register is used in conjunction with its associated full-scale register to form a register pair. The power-on reset value is automatically overwritten if an internal or system zero-scale calibration is initiated by the user. The AD7195 must be placed in powerdown mode or idle mode when writing to the offset register.

FULL-SCALE REGISTER

(RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXXX0)

The full-scale register is a 24-bit register that holds the full-scale calibration coefficient for the ADC. The AD7195 has four fullscale registers; therefore, each channel has a dedicated full-scale register (see Ta b le 2 5 ). The full-scale registers are read/write registers. However, when writing to the full-scale registers, the ADC must be placed in power-down mode or idle mode. These registers are configured at power-on with factory-calibrated full-scale calibration coefficients, the calibration being performed at gain = 1. Therefore, every device has different default coefficients. The default value is automatically overwritten if an internal or system full-scale calibration is initiated by the user or if the full-scale register is written to.

Rev. 0 | Page 24 of 44

AD7195

ADC CIRCUIT INFORMATION

AIN1 AIN2 AIN3 AIN4

AINCOM

BPDSW

AD7195

MUX

AGND

SENSOR

TEMP

DGND REFIN(+) REFIN(–)

PGA

EXCITATION

CLOCK

Σ-Δ

ADC

REFERENCE

DETECT

SERIAL

INTERFACE

AND

CONTROL

LOGIC

CLOCK

CIRCUITRY

DOUT/RDY DIN SCLK

CS SYNC

ACX1 ACX1 ACX2ACX2

Figure 18. Block Diagram

OVERVIEW

The AD7195 is an ultralow noise ADC that incorporates a Σ- modulator, a buffer, PGA, and on-chip digital filtering intended for the measurement of wide dynamic range signals, such as those in pressure transducers, weigh scales, and strain gage applications. Figure 18 shows the block diagram for the part.

Analog Inputs

The device can be configured to have two differential or four pseudo differential analog inputs. The analog inputs can be buffered or unbuffered.

Multiplexer

The on-chip multiplexer increases the channel count of the device. Because the multiplexer is included on chip, any channel changes are synchronized with the conversion process.

PGA

The analog input signal can be amplified using the PGA. The PGA allows gains of 1, 8, 16, 32, 64, and 128.

Reference Detect

The AD7195 is capable of monitoring the external reference. If the reference is not present, a flag is set in the status register of the device.

Burnout Currents

Two 500 nA burnout currents are included on-chip to detect the presence of the external sensor.

MCLK1 MCLK2

08771-001

Σ-Δ ADC and Filter

The AD7195 contains a fourth-order Σ- modulator followed by a digital filter. The device offers the following filter options:

• Sinc

• Chop enabled/disabled

• Zero latency

AC Excitation

The AD7195 supports ac excitation of load cells. It provides the four logic outputs needed to control the transistors in an ac excited load cell design.

Serial Interface

The AD7195 has a 4-wire SPI. The on-chip registers are accessed via the serial interface.

Clock

The AD7195 has an internal 4.92 MHz clock. Either this clock or an external clock can be used as the clock source to the AD7195. The internal clock can also be made available on a pin if a clock source is required for external circuitry.

Temperature Sensor

The on-chip temperature sensor monitors the die temperature.

Calibration

Both internal and system calibration are included on chip; thus, the user has the option of removing offset/gain errors internal to the AD7195 only, or removing the offset/gain errors of the complete end system.

Rev. 0 | Page 25 of 44

AD7195

ANALOG INPUT CHANNEL

The AD7195 has two differential/four pseudo differential analog input channels, which can be buffered or unbuffered. In buffered mode (the BUF bit in the configuration register is set to 1), the input channel feeds into a high impedance input stage of the buffer amplifier. Therefore, the input can tolerate significant source impedances and is tailored for direct connection to external resistive-type sensors such as strain gages or resistance temperature detectors (RTDs).

When BUF = 0, the part operates in unbuffered mode. This results in a higher analog input current. Note that this unbuffered input path provides a dynamic load to the driving source. Therefore, resistor/capacitor combinations on the input pins can cause gain errors, depending on the output impedance of the source that is driving the ADC input. allowable external resistance/capacitance values for unbuffered mode at a gain of 1 such that no gain error at the 20-bit level is introduced.

Table 27. External R-C Combination for No 20-Bit Gain Error

C (pF) R (Ω)

50 1.4 k 100 850 500 300 1000 230 5000 30

The absolute input voltage range in buffered mode is restricted to a range between AGND + 250 mV and AV must be taken in setting up the common-mode voltage so that these limits are not exceeded. Otherwise, linearity and noise performance degrades.

The absolute input voltage in unbuffered mode includes the range between AGND − 50 mV and AV negative absolute input voltage limit does allow the possibility of monitoring small true bipolar signals with respect to AGND.

PGA

When the gain stage is enabled, the output from the buffer is applied to the input of the PGA. The presence of the PGA means that signals of small amplitude can be gained within the AD7195 while still maintaining excellent noise performance. For example, when the gain is set to 128, the rms noise is 8.5 nV, typically, when the output data rate is 4.7 Hz, which is equivalent to 23 bits of effective resolution or 20.5 bits of noise-free resolution.

The AD7195 can be programmed to have a gain of 1, 8, 16, 32, 64, and 128 using Bit G2 to Bit G0 in the configuration register. Therefore, with an external 2.5 V reference, the unipolar ranges are from 0 mV to 19.53 mV to 0 V to 2.5 V and the bipolar ranges are from ±19.53 mV to ±2.5 V.

The analog input range must be limited to ±(AV because the PGA requires some headroom. Therefore, if AV 5 V, the maximum analog input that can be applied to the

Table 2 7 shows the

− 250 mV. Care

+ 50 mV. The

− 1.25 V)/gain

AD7195 is 0 to 3.75 V/gain in unipolar mode or ±3.75 V/gain in bipolar mode.

REFERENCE

The ADC has a fully differential input capability for the reference channel. The common-mode range for these differential inputs is from AGND to AV (REFIN(+) − REFIN(−)) is AV is functional with reference voltages from 1 V to AV

. The reference voltage REFIN

nominal, but the AD7195

. In

applications where the excitation (voltage or current) for the transducer on the analog input also drives the reference voltage for the part, the effect of the low frequency noise in the excitation source is removed because the application is ratiometric. If the AD7195 is used in a nonratiometric application, a low noise reference should be used.

The reference input is unbuffered; therefore, excessive R-C source impedances introduce gain errors. R-C values similar to those in

Table 2 7 are recommended for the reference inputs.

Deriving the reference input voltage across an external resistor means that the reference input sees significant external source impedance. External decoupling on the REFINx pins is not recommended in this type of circuit configuration. Conversely, if large decoupling capacitors are used on the reference inputs, there should be no resistors in series with the reference inputs.

Recommended 2.5 V reference voltage sources for the AD7195 include the ADR421 and ADR431, which are low noise references. These references tolerate decoupling capacitors on REFIN(+) without introducing gain errors in the system. Figure 19 shows the recommended connections between the ADR421 and the AD7195.

0.1µF

ADR421

GND

OUT

TRIM

10µF 4.7µF

Figure 19. ADR421 to AD7195 Connections

AD7195

REFINx(+)

REFINx(–)

08771-037

REFERENCE DETECT

The AD7195 includes on-chip circuitry to detect whether the part has a valid reference for conversions or calibrations. This feature is enabled when the REFDET bit in the configuration register is set to 1. If the voltage between the REFIN(+) and REFIN(−) pins is between 0.3 V and 0.6 V, the AD7195 detects that it no longer has a valid reference. In this case, the NOREF bit of the status register is set to 1. If the AD7195 is performing normal conversions and the NOREF bit becomes active, the conversion result is all 1s.

Therefore, it is not necessary to continuously monitor the status of the NOREF bit when performing conversions. It is only necessary to verify its status if the conversion result read from the ADC data register is all 1s. If the AD7195 is performing either an offset or full-scale calibration and the NOREF bit becomes active, the updating of the respective calibration

Rev. 0 | Page 26 of 44

AD7195

registers is inhibited to avoid loading incorrect coefficients to these registers, and the ERR bit in the status register is set. If the user is concerned about verifying that a valid reference is in place every time a calibration is performed, the status of the ERR bit should be checked at the end of the calibration cycle.

BIPOLAR/UNIPOLAR CONFIGURATION

The analog input to the AD7195 can accept either unipolar or bipolar input voltage ranges. A bipolar input range does not imply that the part can tolerate negative voltages with respect to system AGND. In pseudo differential mode, signals are referenced to AINCOM while in differential mode, signals are referenced to the negative input of the differential pair. For example, if AINCOM is 2.5 V and the AD7195 AIN1 analog input is configured for unipolar mode with a gain of 2, the input voltage range on the AIN1 pin is 2.5 V to 3.75 V when a 2.5 V reference is used. If AINCOM is 2.5 V and the AD7195 AIN1 analog input is configured for bipolar mode with a gain of 2, the analog input range on AIN1 is 1.25 V to 3.75 V.

The bipolar/unipolar option is chosen by programming the U/

bit in the configuration register.

DATA OUTPUT CODING

When the ADC is configured for unipolar operation, the output code is natural (straight) binary with a zero differential input voltage resulting in a code of 00...00, a midscale voltage resulting in a code of 100...000, and a full-scale input voltage resulting in a code of 111...111. The output code for any analog input voltage can be represented as

Code = (2

× AIN × Gain)/V

REF

When the ADC is configured for bipolar operation, the output code is offset binary with a negative full-scale voltage resulting in a code of 000...000, a zero differential input voltage resulting in a code of 100...000, and a positive full-scale input voltage resulting in a code of 111...111. The output code for any analog input voltage can be represented as

Code = 2

N – 1

× [(AIN × Gain/V

REF

) + 1]

where:

N = 24. AIN is the analog input voltage. Gain is the PGA setting (1 to 128).

BURNOUT CURRENTS

The AD7195 contains two 500 nA constant current generators, one sourcing current from AV current from AIN(−) to AGND, where AIN(+) is the positive analog input terminal and AIN(−) is the negative analog input terminal in differential mode and AINCOM in pseudo differential mode. The currents are switched to the selected analog input pair. Both currents are either on or off, depending on the burnout current enable (BURN) bit in the configuration register. These currents can be used to verify that an external transducer remains operational before attempting to take measurements on that channel. After the burnout currents are

to AIN(+) and one sinking

Rev. 0 | Page 27 of 44

turned on, they flow in the external transducer circuit, and a measurement of the input voltage on the analog input channel can be taken. It will take some time for the burnout currents to detect an open circuit condition as the currents will need to charge any external capacitors

There are several reasons why a fault condition might be detected. The front-end sensor may be open circuit. The frontend sensor may be overloaded, or the reference may be absent and the NOREF bit in the status register is set, thus clamping the data to all 1s. Check these possibilities first. If the voltage measured is 0 V, it may indicate that the transducer has short circuited. The current sources work over the normal absolute input voltage range specifications when the analog inputs are buffered and chop is disabled.

AC EXCITATION

AC excitation of the bridge addresses many of the concerns with thermocouple, offset, and drift effects encountered in dc excited applications. In ac excitation, the polarity of the excitation voltage to the bridge is reversed on alternate cycles. The result is the elimination of dc errors at the expense of a more complex system design. Figure 50 outlines the connections for an ac excited bridge application based on the AD7195.

The excitation voltage to the bridge must be switched on alternate cycles. Transistor T1 to Transistor T4 in Figure 50 perform the switching of the excitation voltage. These transistors can be discrete matched bipolar or MOS transistors, or a dedicated bridge driver chip, such as the MIC4427 available from Micrel Components, can be used to perform the task.

Since the analog input voltage and the reference voltage are reversed on alternate cycles, the AD7195 must be synchronized with this reversing of the excitation voltage. To allow the AD7195 to synchronize itself with this switching, it provides the logic control signals for the switching of the excitation voltage. These signals are the nonoverlapping CMOS outputs ACX1/

One of the problems encountered with ac excitation is the settling time associated with the analog input signals after the excitation voltage is switched. This is particularly true in applications where there are long lead lengths from the bridge to the AD7195. It means that the converter could encounter errors because it is processing signals that are not fully settled. The AD7195 includes a delay between the switching of the ac excitation signals and the processing of data at the analog inputs. The delay equals 100 s when FS[9:0] equals 1 and equals 200 s for all other output data rates.

The AD7195 also scales the ac excitation switching frequency in accordance with the output data rate. This avoids situations where the bridge is switched at an unnecessarily faster rate than the system requires.

The fact that the AD7195 can handle reference voltages, which are the same as the excitation voltages, is particularly useful

ACX1

and ACX2/

ACX2

AD7195

in ac excitation where resistor divider arrangements on the reference input add to the settling time associated with the switching.

When the ACX bit in the configuration register is set to 0, the digital outputs ACX1 and

ACX2 and

are low. Therefore, the bridge is dc excited

ACX1

with the T2 and T4 transistors turned on and the T1 and T3 transistors turned off. When the AD7195 is in power-down mode, outputs ACX1 and ACX2 are low and outputs

and

are high so that the excitation voltage is discon-

ACX2

nected from the bridge.

CHANNEL SEQUENCER

The AD7195 includes a channel sequencer, which simplifies communications with the device in multichannel applications. The sequencer also optimizes the channel throughput of the device because the sequencer switches channels at the optimum rate rather than waiting for instructions via the SPI interface.

Bit CH0 to Bit CH7 in the configuration register are used to enable the required channels. In continuous conversion mode, the ADC selects each of the enabled channels in sequence and performs a conversion on the channel. The

when a valid conversion is available on each channel. When several channels are enabled, the contents of the status register should be attached to the 24-bit word so that the user can identify the channel that corresponds to each conversion. To attach the status register value to the conversion, Bit DAT_STA in the mode register should be set to 1.

DIGITAL INTERFACE

As indicated in the On-Chip Registers section, the programmable functions of the AD7195 are controlled using a set of on-chip registers. Data is written to these registers via the serial interface of the part. Read access to the on-chip registers is also provided by this interface. All communication with the part must start with a write to the communications register. After power-on or reset, the device expects a write to its communications register.

The data written to this register determines whether the next operation is a read operation or a write operation and determines to which register this read or write operation occurs. Therefore, write access to any of the other registers on the part begins with a write operation to the communications register, followed by a write to the selected register. A read operation from any other register (except when continuous read mode is selected) starts with a write to the communications register, followed by a read operation from the selected register.

The serial interface of the AD7195 consists of four signals: DIN, SCLK, and DOUT/ data into the on-chip registers and DOUT/ accessing data from the on-chip registers. SCLK is the serial

clock input for the device, and all data transfers (either on DIN or DOUT/

RDY

) occur with respect to the SCLK signal.

RDY

are high, while outputs

ACX2

ACX1

pin goes low

RDY

. The DIN line is used to transfer

RDY

is used for

When several channels are enabled, the ADC must allow the complete settling time to generate a valid conversion each time that the channel is changed. The AD7195 takes care of this: when a channel is selected, the modulator and filter are reset, and the

complete settling time to generate the first conversion.

pin is taken high. The AD7195 then allows the

RDY

goes low only when a valid conversion is available. The AD7195 then selects the next enabled channel and converts on that channel. The user can then read the data register while the ADC is performing the conversion on the next channel.

The time required to read a valid conversion from all enabled channels is equal to

× number of enabled channels

SETTLE

For example, if the sinc

filter is selected, chop is disabled, and zero latency is disabled, the settling time for each channel is equal to

where f

= 4/f

SETTLE

is the output data rate when continuously converting

ADC

on a single channel. The time required to sample N channels is

4/(f

× N)

ADC

RDY

CONVERSIONS

The DOUT/

CHANNEL A CHANNE L B

1/f

ADC

Figure 20. Channel Sequencer

RDY

pin functions as a data ready signal also; the

CHANNEL C

line goes low when a new data-word is available in the output register. It is reset high when a read operation from the data register is complete. It also goes high prior to the updating of the data register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated.

is used to select a device. It can be used to decode the AD7195 in systems where several components are connected to the serial bus.

Figure 3 and Figure 4 show timing diagrams for interfacing to the AD7195, with

being used to decode the part. shows

Figure 3 the timing for a read operation from the output shift register of the AD7195, and shows the timing for a write operation

Figure 4

to the input shift register.

It is possible to read the same word from the data register several times even though the DOUT/

RDY

line returns high after the first read operation. However, care must be taken to ensure that the read operations are completed before the next output update occurs. In continuous read mode, the data register can be read only once.

08771-028

Rev. 0 | Page 28 of 44

AD7195

The serial interface can operate in 3-wire mode by tying CS low. In this case, the SCLK, DIN, and DOUT/

RDY

lines are used to communicate with the AD7195. The end of the conversion can be monitored using the for interfacing to microcontrollers. If

RDY

bit or pin. This scheme is suitable

is required as a decoding signal, it can be generated from a port pin. For microcontroller interfaces, it is recommended that SCLK idle high between data transfers.

The AD7195 can be operated with

used as a frame synchronization signal. This scheme is useful for DSP interfaces. In this case, the first bit (MSB) is effectively clocked out by CS

normally occurs after the falling edge of SCLK in DSPs. The

because

SCLK can continue to run between data transfers, provided the timing numbers are obeyed.

The serial interface can be reset by writing a series of 1s to the DIN input. If a Logic 1 is written to the AD7195 DIN line for at least 40 serial clock cycles, the serial interface is reset. This ensures that the interface can be reset to a known state if the interface gets lost due to a software error or some glitch in the system. Reset returns the interface to the state in which it expects a write to the communications register. This operation resets the contents of all registers to their power-on values. Following a reset, the user should allow a period of 500 μs before addressing the serial interface.

The AD7195 can be configured to continuously convert or to perform a single conversion (see Figure 21 through Figure 23).

Single Conversion Mode

In single conversion mode, the AD7195 is placed in powerdown mode after conversions. When a single conversion is initiated by setting MD2, MD1, and MD0 to 0, 0, 1, respectively, in the mode register, the AD7195 powers up, performs a single conversion, and then returns to power-down mode. The onchip oscillator requires 1 ms, approximately, to power up.

RDY

DOUT/

goes low to indicate the completion of a conversion. When the data-word has been read from the data register, DOUT/

RDY

goes high. If CS is low, DOUT/

RDY

remains high until another conversion is initiated and completed. The data register can be read several times, if required, even when

RDY

DOUT/

has gone high.

If several channels are enabled, the ADC sequences through the enabled channels and performs a conversion on each channel. When a conversion is started, DOUT/

RDY

goes high and remains high until a valid conversion is available. As soon as the conversion is available, DOUT/

RDY

goes low. The ADC then selects the next channel and begins a conversion. The user can read the present conversion while the next conversion is being performed. As soon as the next conversion is complete, the data register is updated; therefore, the user has a limited period in which to read the conversion. When the ADC has performed a single conversion on each of the selected channels, it returns to power-down mode.

If the DAT_STA bit in the mode register is set to 1, the contents of the status register are output along with the conversion each time that the data read is performed. The four LSBs of the status register indicate the channel to which the conversion corresponds.

DIN

DOUT/RDY

SCLK

0x08 0x58

0x280060

Figure 21. Single Conversion

Rev. 0 | Page 29 of 44

DATA

08771-029

AD7195

Continuous Conversion Mode

Continuous conversion is the default power-up mode. The AD7195 converts continuously, and the register goes low each time a conversion is complete. If low, the DOUT/

RDY

line also goes low when a conversion is completed. To read a conversion, the user writes to the communications register, indicating that the next operation is a read of the data register. When the data-word has been read from the data register, DOUT/

RDY read this register additional times, if required. However, the user must ensure that the data register is not being accessed at the completion of the next conversion or else the new conversion

word is lost.

RDY

bit in the status

goes high. The user can

When several channels are enabled, the ADC continuously loops through the enabled channels, performing one conversion on each channel per loop. The data register is updated as soon as each conversion is available. The DOUT/

RDY

pin pulses low each time a conversion is available. The user can then read the conversion while the ADC converts on the next enabled channel.

If the DAT_STA bit in the mode register is set to 1, the contents of the status register are output along with the conversion each time that the data read is performed. The status register indicates the channel to which the conversion corresponds.

DIN

DOUT/RDY

SCLK

0x58 0x58

DATA DATA

Figure 22. Continuous Conversion

8771-030

Rev. 0 | Page 30 of 44

AD7195

Continuous Read

Rather than write to the communications register each time a conversion is complete to access the data, the AD7195 can be configured so that the conversions are placed on the DOUT/

RDY

line automatically. By writing 01011100 to the communications register, the user need only apply the appropriate number of SCLK cycles to the ADC, and the conversion word is automatically placed on the DOUT/

RDY

line when a conversion is complete. The ADC should be configured for continuous conversion mode.

When DOUT/

RDY

goes low to indicate the end of a conversion, sufficient SCLK cycles must be applied to the ADC; the data conversion is then placed on the DOUT/ conversion is read, DOUT/

RDY

returns high until the next

RDY

line. When the

conversion is available. In this mode, the data can be read only once. Also, the user must ensure that the data-word is read before the next conversion is complete. If the user has not read the conversion before the completion of the next conversion, or if insufficient serial clocks are applied to the AD7195 to read the word, the serial output register is reset when the next

conversion is complete, and the new conversion is placed in the output serial register.

To exit the continuous read mode, Instruction 01011000 must be written to the communications register while the

RDY

pin is low. While in continuous read mode, the ADC monitors activity on the DIN line so that it can receive the instruction to exit the continuous read mode. Additionally, a reset occurs if 40 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to the device.

When several channels are enabled, the ADC continuously steps through the enabled channels and performs one conversion on each channel each time that it is selected. DOUT/ RDY

pulses low when a conversion is available. When the user applies sufficient SCLK pulses, the data is automatically placed on the DOUT/

RDY

pin. If the DAT_STA bit in the mode register is set to 1, the contents of the status register are output along with the conversion. The status register indicates the channel to which the conversion corresponds.

DIN

DOUT/RDY

SCLK

0x5C

DATA DATA DATA

8771-031

Figure 23. Continuous Read

Rev. 0 | Page 31 of 44

AD7195

RESET

The circuitry and serial interface of the AD7195 can be reset by writing consecutive 1s to the device; 40 consecutive 1s are required to perform the reset. This resets the logic, the digital filter, and the analog modulator, whereas all on-chip registers are reset to their default values. A reset is automatically performed on power-up. When a reset is initiated, the user must allow a period of 500 μs before accessing any of the on-chip registers. A reset is useful if the serial interface loses synchronization due to noise on the SCLK line.

SYSTEM SYNCHRONIZATION

SYNC

The digital filter without affecting any of the setup conditions on the part. This allows the user to start gathering samples of the analog input from a known point in time, that is, the rising edge

SYNC

of clock cycles to implement the synchronization function.

If multiple AD7195 devices operate from a common master clock, they can be synchronized so that their data registers are updated simultaneously. A falling edge on the the digital filter and the analog modulator and places the AD7195 into a consistent, known state. While the AD7195 is maintained in this state. On the the modulator and filter are taken out of this reset state and, on the next clock edge, the part starts to gather input samples again. In a system using multiple AD7195 devices, a common signal to their done after each AD7195 has performed its own calibration or has calibration coefficients loaded into its calibration registers. The conversions from the AD7195s are then synchronized.

The part is taken out of reset on the master clock falling edge following the multiple devices are being synchronized, the be taken high on the master clock rising edge to ensure that all devices begin sampling on the master clock falling edge. If the SYNC one master clock cycle may result between the devices; that is, the instant at which conversions are available differs from part to part by a maximum of one master clock cycle.

The In this mode, the rising edge of falling edge of The settling time of the filter has to be allowed for each data

register update. For example, if the ADC is configured to use the sinc settling time equals 4/f when continuously converting on a single channel.

CLOCK

The AD7195 includes an internal 4.92 MHz clock on-chip. This internal clock has a tolerance of ±4%. Either the internal clock or an external crystal/clock can be used as the clock source to

input allows the user to reset the modulator and the

SYNC

needs to be taken low for at least four master

SYNC

pin resets

SYNC

pin is low, the

SYNC

rising edge,

SYNC

pins synchronizes their operation. This is normally

SYNC

low to high transition. Therefore, when

SYNC

pin should

pin is not taken high in sufficient time, a difference of

SYNC

pin can also be used as a start conversion command.

SYNC

starts conversion, and the

RDY

indicates when the conversion is complete.

filter, zero latency is disabled, and chop is disabled, the

ADC

where f

is the output data rate

ADC

Rev. 0 | Page 32 of 44

the AD7195. The clock source is selected using the CLK1 and CLK0 bits in the mode register. When an external crystal is used, it must be connected across the MCLK1 and MCLK2 pins. The crystal manufacturer recommends the load capacitances required for the crystal. The MCLK1 and MCLK2 pins of the AD7195 have a capacitance of 15 pF, typically. If an external clock source is used, the clock source must be connected to the MCLK2 pin, and the MCLK1 pin can be left floating.

The internal clock can also be made available at the MCLK2 pin. This is useful when several ADCs are used in an application and the devices must be synchronized. The internal clock from one device can be used as the clock source for all ADCs in the system. Using a common clock, the devices can be synchronized by applying a common reset to all devices, or the

SYNC

pin can be pulsed.

ENABLE PARITY

The AD7195 also has an on-chip parity check function that detects 1-bit errors in the serial communications between the ADC and the microprocessor. When the ENPAR bit in the mode register is set to 1, parity is enabled. The contents of the status register must be transmitted along with each 24-bit conversion when the parity function is enabled. To append the contents of the status register to each conversion read, the DAT_STA bit in the mode register should be set to 1.

For each conversion read, the parity bit in the status register is programmed so that the overall number of 1s transmitted in the 24-bit data-word is even. Therefore, for example, if the 24-bit conversion contains eleven 1s (binary format), the parity bit is set to 1 so that the total number of 1s in the serial transmission is even. If the microprocessor receives an odd number of 1s, it knows that the data received has been corrupted.

The parity function only detects 1-bit errors. For example, two bits of corrupt data can result in the microprocessor receiving an even number of 1s. Therefore, an error condition is not detected.

TEMPERATURE SENSOR

Embedded in the AD7195 is a temperature sensor. This is selected using the CH2 bit in the configuration register. When the CH2 bit is set to 1, the temperature sensor is enabled. When the temperature sensor is selected and bipolar mode is selected, the device should return a code of 0x800000 when the temperature is 0 K. A one-point calibration is needed to get the optimum performance from the sensor. Therefore, a conversion at 25°C should be recorded and the sensitivity calculated. The sensitivity is approximately 2815 codes/°C. The equation for the temperature sensor is

Temp (K) = (Conversion − 0x800000)/2815 K

Temp (°C) = Temp (K) − 273

Following the one point calibration, the internal temperature sensor has an accuracy of ±2 °C, typically.

AD7195

BRIDGE POWER-DOWN SWITCH

In bridge applications, such as strain gauges and load cells, the bridge itself consumes the majority of the current in the system. For example, a 350  load cell requires 15 mA of current when excited with a 5 V supply. To minimize the current consumption of the system, the bridge can be disconnected (when it is not being used) using the bridge power-down switch. Figure 50 shows how the bridge power-down switch is used. The switch can withstand 30 mA of continuous current, and it has an on resistance of 10  maximum.

CALIBRATION

The AD7195 provides four calibration modes that can be programmed via the mode bits in the mode register. These modes are internal zero-scale calibration, internal full-scale calibration, system zero-scale calibration, and system full-scale calibration. A calibration can be performed at any time by setting the MD2 to MD0 bits in the mode register appropriately. A calibration should be performed when the gain is changed. After each conversion, the ADC conversion result is scaled using the ADC calibration registers before being written to the data register. The offset calibration coefficient is subtracted from the result prior to multiplication by the full-scale coefficient.

To start a calibration, write the relevant value to the MD2 to MD0 bits. The DOUT/

RDY

pin and the register go high when the calibration is initiated. When the calibration is complete, the contents of the corresponding calibration registers are updated, the register is reset, the DOUT/

RDY

low), and the AD7195 reverts to idle mode.

During an internal zero-scale or full-scale calibration, the respective zero input and full-scale input are automatically connected internally to the ADC input pins. A system calibration, however, expects the system zero-scale and system full-scale voltages to be applied to the ADC pins before initiating the calibration mode. In this way, errors external to the ADC are removed.

From an operational point of view, treat a calibration like another ADC conversion. A zero-scale calibration, if required, must always be performed before a full-scale calibration. Set the system software to monitor the

the DOUT/

RDY

pin to determine the end of calibration via a

RDY

polling sequence or an interrupt-driven routine.

With chop disabled, both an internal zero-scale calibration and a system zero-scale calibration require a time equal to the settling time, t

SETTLE

, (4/f

for the sinc4 filter and 3/f

ADC

With chop enabled, an internal zero-scale calibration is not needed because the ADC itself minimizes the offset continuously. However, if an internal zero-scale calibration is performed, the settling time, t

SETTLE,

(2/f

) is required to perform the calibra-

ADC

tion. Similarly, a system zero-scale calibration requires a time of t

to complete.

SETTLE

RDY

bit in the status

RDY

bit in the status

pin returns low (if CS is

bit in the status register or

for the sinc3 filter).

ADC

To perform an internal full-scale calibration, a full-scale input voltage is automatically connected to the selected analog input for this calibration. For a gain of 1, the time required for an internal full-scale calibration is equal to t the internal full-scale calibration requires a time of 2 × t

. For higher gains,

SETTLE

. A full-scale calibration is recommended each time the gain of a channel is changed to minimize the full-scale error.

A system full-scale calibration requires a time of t

SETTLE

. With chop disabled, the zero-scale calibration (internal or system zero-scale) should be performed before the system full-scale calibration is initiated.

An internal zero-scale calibration, system zero-scale calibration and system full-scale calibration can be performed at any output data rate. An internal full-scale calibration can be performed at any output data rate for which the filter word FS[9:0] is divisible by 16, FS[9:0] being the decimal equivalent of the 10-bit word written to Bit FS9 to Bit FS0 in the mode register. Therefore, internal full-scale calibrations can be performed at output data rates such as 10 Hz or 50 Hz when chop is disabled. Using these lower output data rates results in better calibration accuracy.

The offset error is, typically, 100 µV/gain. If the gain is changed, it is advisable to perform a calibration. A zero-scale calibration (an internal zero-scale calibration or system zero-scale calibration) reduces the offset error to the order of the noise.

The gain error of the AD7195 is factory calibrated at a gain of 1 with a 5 V power supply at ambient temperature. Following this calibration, the gain error is 0.001%, typically, at 5 V. Tabl e 28 shows the typical uncalibrated gain error for the different gain settings. An internal full-scale calibration reduces the gain error to 0.001%, typically, when the gain is equal to 1. For higher gains, the gain error post internal full-scale calibration is

0.0075%, typically. A system full-sale calibration reduces the gain error to the order of the noise.

Table 28. Typical Precalibration Gain Error vs. Gain

Gain Precalibration Gain Error (%)

8 −0.11 16 −0.20 32 −0.23 64 −0.29 128 −0.39

The AD7195 gives the user access to the on-chip calibration registers, allowing the microprocessor to read the calibration coefficients of the device and also to write its own calibration coefficients from prestored values in the EEPROM. A read of the registers can be performed at any time. However, the ADC must be placed in power-down or idle mode when writing to the registers. The values in the calibration registers are 24-bits wide. The span and offset of the part can also be manipulated using the registers.

Rev. 0 | Page 33 of 44

AD7195

DIGITAL FILTER

The AD7195 offers a lot of flexibility in the digital filter. The device has four filter options. The device can be operated with a sinc zero latency can be enabled. The option selected affects the output data rate, settling time, and 50 Hz/60 Hz rejection. The following sections describe each filter type, indicating the available output data rates for each filter option. The filter response along with the settling time and 50 Hz/60 Hz rejection is also discussed.

SINC4 FILTER (CHOP DISABLED)

When the AD7195 is powered up, the sinc4 filter is selected by default and chop is disabled. This filter gives excellent noise performance over the complete range of output data rates. It also gives the best 50 Hz/60 Hz rejection, but it has a long settling time.

or sinc

filter, chop can be enabled or disabled, and

ADC

CHOP

MODULATOR

SINC3/SINC

When conversions are performed on a single channel and a step change occurs, the ADC does not detect the change in analog input. Therefore, it continues to output conversions at the programmed output data rate. However, it is at least four conversions later before the output data accurately reflect the analog input. If the step change occurs while the ADC is processing a conversion, then the ADC takes five conversions after the step change to generate a fully settled result.

ANALOG

INPUT

ADC

OUTPUT

ADC

Figure 26. Asynchronous Step Change in Analog Input

FULLY

SETTLED

The 3 dB frequency for the sinc4 filter is equal to

= 0.23 × f

3dB

ADC

Tabl e 29 gives some examples of the relationship between the values in Bits FS[9:0] and the corresponding output data rate and settling time.

8771-039

08771-033

Figure 24. Sinc

Filter (Chop Disabled)

Sinc4 Output Data Rate/Settling Time

The output data rate (the rate at which conversions are available on a single channel when the ADC is continuously converting) is equal to

= f

ADC

/(1024 × FS[9:0])

CLK

where:

is the output data rate.

ADC

is the master clock (4.92 MHz nominal).

CLK

FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the

mode register.

The output data rate can be programmed from 4.7 Hz to 4800 Hz; that is, FS[9:0] can have a value from 1 to 1023.

The settling time for the sinc

SETTLE

= 4/f

ADC

filter is equal to

When a channel change occurs, the modulator and filter are reset. The settling time is allowed to generate the first conversion after the channel change. Subsequent conversions on this channel occur at 1/f

CHANNEL

ADC

CHANNEL A

CHANNEL B

Table 29. Examples of Output Data Rates and the Corresponding Settling Time

FS[9:0] Output Data Rate (Hz) Settling Time (ms)

480 10 400 96 50 80 80 60 66.6

Sinc4 Zero Latency

Zero latency is enabled by setting the single bit (Bit 11) in the mode register to 1. With zero latency, the complete settling time is allowed for each conversion. Therefore, the conversion time when converting on a single channel or when converting on several channels is constant. The user does not need to consider the effects of channel changes on the output data rate.

The output data rate equals

ADC

= 1/t

SETTLE

= f

/(4 × 1024 × FS[9:0])

CLK

where:

is the output data rate.

ADC

is the master clock (4.92 MHz nominal).

CLK

FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the

mode register.

CONVERSIONS

CH A CH A CH A CH B CH B CH B

ADC

Channel Change

Figure 25. Sinc

8771-038

Rev. 0 | Page 34 of 44

AD7195

When the analog input is constant or a channel change occurs, valid conversions are available at a constant output data rate. When conversions are being performed on a single channel and a step change occurs on the analog input, the ADC continues to output fully settled conversions if the step change is synchronized with the conversion process. If the step change is asynchronous, one conversion is output from the ADC, which is not completely settled (see Figure 27).

ANALO

INPUT

ADC

OUTPUT

Figure 27. Sinc

ADC

Zero Latency Operation

FULLY

SETTLED

08771-040

Tabl e 30 shows examples of output data rate and the corresponding FS values.

Table 30. Examples of Output Data Rates and the Corresponding Settling Time (Zero Latency)

FS[9:0] Output Data Rate (Hz) Settling Time (ms)

480 2.5 400 96 12.5 80 80 15 66.6

Sinc4 50 Hz/60 Hz Rejection

Figure 28 shows the frequency response of the sinc4 filter when FS[9:0] is set to 96 and the master clock is 4.92 MHz. With zero latency disabled, the output data rate is equal to 50 Hz. With zero latency enabled, the output data rate is 12.5 Hz. The sinc

filter provides 50 Hz (±1 Hz) rejection in excess of 120 dB minimum, assuming a stable master clock.

0 –10 –20 –30 –40 –50 –60 –70

FILTER GAIN (dB)

–80 –90

–100 –110 –120

Figure 28. Sinc

FREQUENCY (Hz)

Filter Response (FS[9:0] = 96)

08771-041

Figure 29 shows the frequency response when FS[9:0] is programmed to 80 and the master clock is equal to 4.92 MHz. The output data rate is 60 Hz when zero latency is disabled and 15 Hz when zero latency is enabled. The sinc

filter provides 60 Hz (±1 Hz) rejection of 120 dB minimum, assuming a stable master clock.

0 –10 –20 –30 –40 –50 –60 –70

FILTER GAIN (dB)

–80 –90

–100

–110

–120

Figure 29. Sinc

FREQUENCY (Hz)

Filter Response (FS[9:0] = 80)

08771-042

Simultaneous 50 Hz and 60 Hz rejection is obtained when FS[9:0] is programmed to 480 and the master clock equals

4.92 MHz. The output data rate is 10 Hz when zero latency is disabled and 2.5 Hz when zero latency is enabled. The sinc

filter provides 50 Hz (±1 Hz) and 60 Hz (±1 Hz) rejection of 120 dB minimum, assuming a stable master clock.

0 –10 –20 –30 –40 –50 –60 –70

FILTER GAIN (dB)

–80 –90

–100

–110

–120

0 30 60 90 120 150

Figure 30. Sinc

FREQUENCY (Hz)

Filter Response (FS[9:0] = 480)

08771-043

Simultaneous 50 Hz/60 Hz rejection can also be achieved using the REJ60 bit in the mode register. When FS[9:0] is set to 96 and REJ60 is set to 1, notches are placed at 50 Hz and 60 Hz.

Rev. 0 | Page 35 of 44

AD7195

The output data rate is 50 Hz when zero latency is disabled and

12.5 Hz when zero latency is enabled. Figure 31 shows the frequency response of the sinc ±1 Hz and 60 Hz ± 1 Hz rejection of 82 dB minimum, assuming a stable 4.92 MHz master clock.

0 –10 –20 –30 –40 –50 –60 –70

FILTER GAIN (dB)

–80 –90

–100 –110 –120

0 25 50 75 100 125 150

Figure 31. Sinc

Filter Response (FS[9:0] = 96, REJ60 = 1)

SINC3 FILTER (CHOP DISABLED)

A sinc3 filter can be used instead of the sinc4 filter. The filter is selected using the SINC3 bit in the mode register. The sinc filter is selected when the SINC3 bit is set to 1.

This filter has good noise performance when operating with output data rates up to 1 kHz. It has moderate settling time and moderate 50 Hz/60 Hz (±1 Hz) rejection.

CHOP

Figure 32. Sinc

Sinc3 Output Data Rate and Settling Time

The output data rate (the rate at which conversions are available on a single channel when the ADC is continuously converting) is equal to

= f

ADC

where:

is the output data rate.

ADC

is the master clock (4.92 MHz nominal).

CLK

FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register.

The output data rate can be programmed from 4.7 Hz to 4800 Hz; that is, FS[9:0] can have a value from 1 to 1023.

The settling time is equal to

SETTLE

/(1024 × FS[9:0])

CLK

= 3/f

ADC

filter. The filter provides 50 Hz

FREQUENCY (Hz)

ADC

MODULATOR

Filter (Chop Disabled)

SINC3/SINC

08771-044

8771-034

The 3 dB frequency is equal to

= 0.272 × f

3dB

ADC

Tabl e 31 gives some examples of FS settings and the corresponding output data rates and settling times.

Table 31. Examples of Output Data Rates and the Corresponding Settling Time

FS[9:0] Output Data Rate (Hz) Settling Time (ms)

480 10 300 96 50 60 80 60 50

When a channel change occurs, the modulator and filter reset. The complete settling time is allowed to generate the first conversion after the channel change (see Figure 33). Subsequent conversions on this channel are available at 1/f

CHANNEL

CONVERSIONS

CHANNEL A

CH A CH A CH A CH BCH B CH B CH B

Figure 33. Sinc

CHANNEL B

ADC

Channel Change

ADC

8771-045

When conversions are performed on a single channel and a step change occurs, the ADC does not detect the change in analog input. Therefore, it continues to output conversions at the programmed output data rate. However, it is at least three conversions later before the output data accurately reflects the analog input. If the step change occurs while the ADC is processing a conversion, the ADC takes four conversions after the step change to generate a fully settled result.

ANALOG

INPUT

ADC

OUTPUT

ADC

FULLY

SETTLED

08771-046

Figure 34. Asynchronous Step Change in Analog Input

Sinc3 Zero Latency

Rev. 0 | Page 36 of 44

AD7195

The output data rate equals

ADC

= 1/t

SETTLE

= f

/(3 × 1024 × FS[9:0])

CLK

where:

is the output data rate.

ADC

is the master clock (4.92 MHz nominal).

CLK

FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the

mode register.

ANALO

INPUT

ADC

OUTPUT

Figure 35. Sinc

ADC

Zero Latency Operation

FULLY

SETTLED

08771-047

Tabl e 32 provides examples of output data rates and the corresponding FS values.

Table 32. Examples of Output Data Rates and the Corresponding Settling Time (Zero Latency)

FS[9:0] Output Data Rate (Hz) Settling Time (ms)

480 3.3 300 96 16.7 60 80 20 50

Sinc3 50 Hz/60 Hz Rejection

Figure 36 show the frequency response of the sinc3 filter when FS[9:0] is set to 96 and the master clock equals 4.92 MHz. The output data rate is equal to 50 Hz when zero latency is disabled and 16.7 Hz when zero latency is enabled. The sinc

filter gives

50 Hz ± 1 Hz rejection of 95 dB minimum for a stable master clock.

0 –10 –20 –30 –40 –50 –60 –70 –80

FILTER GAIN (dB)

–90

–100

–110

–120

0 25 50 75 100 125 150

Figure 36. Sinc

FREQUENCY ( Hz )

Filter Response (FS[9:0] = 96)

08771-048

When FS[9:0] is set to 80 and the master clock equals

4.92 MHz, 60 Hz rejection is achieved (see Figure 37). The output data rate is equal to 60 Hz when zero latency is disabled and 20 Hz when zero latency is enabled. The sinc

filter has rejection of 95 dB minimum at 60 Hz ± 1 Hz, assuming a stable master clock.

0 –10 –20 –30 –40 –50 –60 –70

FILTER GAIN (dB)

–80 –90

–100

–110

–120

0 30 60 90 120 150

Figure 37. Sinc

FREQUENCY (Hz)

Filter Response (FS[9:0] = 80)

08771-049

Rev. 0 | Page 37 of 44

AD7195

Simultaneous 50 Hz and 60 Hz rejection is obtained when FS[9:0] is set to 480 (master clock = 4.92 MHz), as shown in Figure 38. The output data rate is 10 Hz when zero latency is disabled and 3.3 Hz when zero latency is enabled. The sinc filter has rejection of 100 dB minimum at 50 Hz ± 1 Hz and 60 Hz ± 1 Hz.

0 –10 –20 –30 –40 –50 –60 –70

FILTER GAIN (dB)

–80 –90

–100 –110 –120

0 306090120150

FREQUENCY (Hz)

Figure 38. Sinc

Filter Response (FS[9:0] = 480)

Simultaneous 50 Hz/60 Hz rejection is also achieved using the REJ60 bit in the mode register. When FS[9:0] is programmed to 96 and the REJ60 bit is set to 1, notches are placed at both 50 Hz and 60 Hz for a stable 4.92 MHz master clock. Figure 39 shows the frequency response of the sinc

filter with this configuration. Assuming a stable clock, the rejection at 50 Hz/60 Hz (±1 Hz) is in excess of 67 dB minimum.

0 –10 –20 –30 –40 –50 –60 –70

FILTER GAIN (dB)

–80 –90

–100 –110 –120

0 25 50 75 100 125 150

FREQUENCY ( Hz)

Figure 39. Sinc

Filter Response (FS[9:0] = 96, REJ60 = 1)

08771-050

08771-051

CHOP ENABLED (SINC4 FILTER)

With chop enabled, the ADC offset and offset drift are minimized. The analog input pins are continuously swapped. With the analog input pins connected in one direction, the settling time of the sinc filter is allowed and a conversion is recorded. The analog input pins are then inverted, and another settled conversion is obtained. Subsequent conversions are averaged to minimize the offset. This continuous swapping of the analog input pins and the averaging of subsequent conversions means that the offset drift is also minimized. With chop enabled, the resolution increases by 0.5 bits.

ADC

CHOP

MODULATOR

SINC3/SINC

Figure 40. Chop Enabled

Output Data Rate and Settling Time (Sinc4 Chop Enabled)

For the sinc4 filter, the output data rate is equal to

= f

ADC

/(4 × 1024 × FS[9:0])

CLK

where:

is the output data rate.

ADC

is the master clock (4.92 MHz nominal).

CLK

FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the

mode register.

The value of FS[9:0] can be varied from 1 to 1023. This results in an output data rate of 1.17 Hz to 1200 Hz. The settling time is equal to

SETTLE

= 2/f

ADC

Tabl e 33 gives some examples of FS[9:0] values and the corresponding output data rates and settling times.

Table 33. Examples of Output Data Rates and the Corresponding Settling Time

FS[9:0] Output Data Rate (Hz) Settling Time (ms)

96 12.5 160 80 15 133

08771-035

Rev. 0 | Page 38 of 44

AD7195

When a channel change occurs, the modulator and filter reset. The complete settling time is required to generate the first conversion after the channel change. Subsequent conversions on this channel occur at 1/f

CHANNEL

CONVERSIONS

CHANNEL A

CH A CH A CH A CH BCH B CH B CH B

Figure 41. Channel Change (Sinc

ADC

CHANNEL B

CH B

ADC

Chop Enabled)

When conversions are performed on a single channel and a step change occurs, the ADC does not detect the change in analog input; therefore, it continues to output conversions at the programmed output data rate. However, it is at least two conversions later before the output data accurately reflects the analog input. If the step change occurs while the ADC is processing a conversion, the ADC takes three conversions after the step change to generate a fully settled result.

ANALOG

INPUT

ADC

OUTPUT

ADC

Figure 42. Asynchronous Step Change in Analog Input (Sinc

The cutoff frequency f

= 0.24 × f

3dB

ADC

is equal to

3dB

FULLY

SETTLED

08771-053

Chop Enabled)

50 Hz/60 Hz Rejection (Sinc4 Chop Enabled)

When FS[9:0] is set to 96 and chopping is enabled, the output data rate is equal to 12.5 Hz for a 4.92 MHz master clock. The filter response shown in Figure 43 is obtained. The chopping introduces notches at odd integer multiples of f

/2. The

ADC

notches due to the sinc filter in addition to the notches introduced by the chopping mean that simultaneous 50 Hz and 60 Hz rejection is achieved for an output data rate of 12.5 Hz. The rejection at 50 Hz/60 Hz ± 1 Hz is typically 63 dB, assuming a stable master clock.

0 –10 –20 –30 –40 –50 –60 –70

FILTER GAIN (dB)

–80

8771-052

–90

–100 –110 –120

0 25 50 75 100 125 150

FREQUENCY ( Hz )

8771-054

Figure 43. Sinc4 Filter Response (FS[9:0] = 96, Chop Enabled)

The 50 Hz/60 Hz rejection can be improved by setting the REJ60 bit in the mode register to 1. With FS[9:0] set to 96 and REJ60 set to 1, the filter response shown Figure 44 is achieved. The output data rate is unchanged but the 50 Hz/ 60 Hz (± 1 Hz) rejection is increased to 83 dB typically.

0 –10 –20 –30 –40 –50 –60 –70

FILTER GAIN (dB)

–80 –90

–100

–110

–120

0 25 50 75 100 125 150

Figure 44. Sinc

Filter Response (FS[9:0] = 96, Chop Enabled, REJ60 = 1)

FREQUENCY ( Hz)

08771-055

Rev. 0 | Page 39 of 44

AD7195

CHOP ENABLED (SINC3 FILTER)

With chop enabled, the ADC offset and offset drift are minimized. The analog input pins are continuously swapped. With the analog input pins connected in one direction, the settling time of the sinc filter is allowed and a conversion is recorded. The analog input pins invert and another settled conversion is obtained. Subsequent conversions are averaged to minimize the offset. This continuous swapping of the analog input pins and the averaging of subsequent conversions means that the offset drift is also minimized. With chop enabled, the resolution increases by 0.5 bits. Using the sinc enabled is suitable for output data rates up to 320 Hz.

ADC

CHOP

MODULATOR

Figure 45. Chop Enabled (Sinc

Output Data Rate and Settling Time (Sinc3 Chop Enabled)

For the sinc3 filter, the output data rate is equal to

= f

ADC

/(3 × 1024 × FS[9:0])

CLK

where:

is the output data rate.

ADC

is the master clock (4.92 MHz nominal).

CLK

FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the

mode register.

The value of FS[9:0] can be varied from 1 to 1023. This results in an output data rate of 1.56 Hz to 1600 Hz. The settling time is equal to

SETTLE

= 2/f

ADC

Table 34. Examples of Output Data Rates and the Corresponding Settling Time (Chop Enabled, Sinc

FS[9:0] Output Data Rate (Hz) Settling Time (ms)

96 16.7 120 80 20 100

When a channel change occurs, the modulator and filter are reset. The complete settling time is required to generate the first conversion after the channel change. Subsequent conversions on this channel occur at 1/f

CHANNEL

CHANNEL A

ADC

filter with chop

SINC3/SINC

Chop Enabled)

CHANNEL B

Filter)

08771-036

If conversions are performed on a single channel and a step change occurs, the ADC does not detect the change in analog input; therefore, it continues to output conversions at the programmed output data rate. However, it is at least two conversions later before the output data accurately reflects the analog input. If the step change occurs while the ADC is processing a conversion, then the ADC takes three conversions after the step change to generate a fully settled result.

ANALOG

INPUT

ADC

OUTPUT

ADC

Figure 47. Asynchronous Step Change in Analog Input (Sinc

The cutoff frequency f

= 0.24 × f

3dB

ADC

is equal to

3dB

FULLY

SETTLED

08771-057

Chop Enabled)

50 Hz/60 Hz Rejection (Sinc3 Chop Enabled)

When FS[9:0] is set to 96 and chopping is enabled, the filter response shown in Figure 48 is obtained. The output data rate is equal to 16.7 Hz for a 4.92 MHz master clock. The chopping introduces notches at odd integer multiples of f

ADC

/2. The notches due to the sinc filter in addtion to the notches introduced by the chopping means that simultaneous 50 Hz and 60 Hz rejection is achieved for an output data rate of 16.7 Hz. The rejection at 50 Hz/60 Hz ± 1 Hz is typically 53 dB, assuming a stable master clock.

0 –10 –20 –30 –40 –50 –60 –70

FILTER GAIN (dB)

–80 –90

–100 –110 –120

0 25 50 75 100 125 150

Figure 48. Sinc

FREQUENCY ( Hz )

Filter Response (FS[9:0] = 96, Chop Enabled)

08771-058

CONVERSIONS

CH A CH A CH A CH BCH B CH B CH B

Figure 46. Channel Change (Sinc

CH B

ADC

Chop Enable)

8771-056

Rev. 0 | Page 40 of 44

AD7195

The 50 Hz/60 Hz rejection can be improved by setting the REJ60 bit in the mode register to 1. With FS[9:0] set to 96 and REJ60 set to 1, the filter response shown in Figure 49 is achieved. The output data rate is unchanged, but the 50 Hz/60 Hz ± 1 Hz rejection improves to 73 dB typically.

0 –10 –20 –30 –40 –50 –60 –70

FILTER GAIN (dB)

–80 –90

–100 –110 –120

0 25 50 75 100 125 150

FREQUENCY ( Hz )

Figure 49. Sinc

Filter Response

08771-059

(FS[9:0] = 96, Chop Enabled, REJ60 = 1)

Table 35. Filter Summary

Filter FS[9:0]

Output Data Rate (Hz)

Settling Time (ms) Throughput2 (Hz) REJ60 50 Hz Rejection (dB)

Sinc4, Chop Disabled3 1 4800 0.83 1200 0 No 50 Hz or 60 Hz rejection Sinc4, Chop Disabled 5 960 4.17 240 0 No 50 Hz or 60 Hz rejection

Sinc

, Chop Disabled 5 960 3.125 320 0 No 50 Hz or 60 Hz rejection

Sinc

, Chop Disabled 480 10 400 2.5 0 120 dB ( 50 Hz and 60 Hz)

Sinc

, Chop Disabled 480 10 300 3.33 0 100 dB (50 Hz and 60 Hz)

Sinc

, Chop Disabled 96 50 80 12.5 0 120 dB (50 Hz only)

Sinc

, Chop Disabled 96 50 80 12.5 1 82 dB ( 50 Hz and 60 Hz)

Sinc

, Chop Disabled 96 50 60 16.7 0 95 dB (50 Hz only)

Sinc

, Chop Disabled 96 50 60 16.7 1 67 dB ( 50 Hz and 60 Hz)

Sinc

, Chop Disabled 80 60 66.67 15 0 120 dB (60 Hz only)

Sinc

, Chop Disabled 80 60 50 20 0 95 dB (60 Hz only)

, Chop Disabled, Zero

Sinc

96 12.5 80 12.5 0

Latency

, Chop Disabled, Zero

Sinc

96 12.5 80 12.5 1

Latency

Sinc

, Chop Disabled, Zero

80 15 66.67 15 0

Latency

, Chop Enabled 96 12.5 160 6.25 1 80 dB (50 Hz and 60 Hz)

Sinc

, Chop Enabled 96 16.7 120 8.33 1 67 dB (50 Hz and 60 Hz)

These calculations assume a 4.92 MHz stable master clock.

Throughput is the rate at which conversions are available when several channels are enabled. In zero latency mode, the output data rate and throughput are equal.

For output dates rates greater than 1 kHz, the sinc4 filter is recommended.

SUMMARY OF FILTER OPTIONS

The AD7195 has several filter options. The filter that is chosen affects the output data rate, settling time, the rms noise, the stop band attenuation, and the 50 Hz/60 Hz rejection.

Tabl e 35 shows some sample configurations and the corresponding performance in terms of throughput, settling time and 50 Hz/60 Hz rejection.

120 dB (50 Hz only)

82 dB ( 50 Hz and 60 Hz)

120 dB (60 Hz only)

Rev. 0 | Page 41 of 44

AD7195

GROUNDING AND LAYOUT

Because the analog inputs and reference inputs are differential, most of the voltages in the analog modulator are commonmode voltages. The high common-mode rejection of the part removes common-mode noise on these inputs. The analog and digital supplies to the AD7195 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The digital filter provides rejection of broadband noise on the power supplies, except at integer multiples of the modulator sampling frequency.

Connect an R-C filter to each analog input pin to provide rejection at the modulator sampling frequency. The digital filter also removes noise from the analog and reference inputs provided these noise sources do not saturate the analog modulator. As a result, the AD7195 is more immune to noise interference than a conventional high resolution converter. However, because the resolution of the AD7195 is so high and the noise levels from the converter so low, care must be taken with regard to grounding and layout.

The printed circuit board (PCB) that houses the ADC must be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes because it gives the best shielding.

Although the AD7195 has separate pins for analog and digital ground, the AGND and DGND pins are tied together internally via the substrate. Therefore, the user must not tie these two pins to separate ground planes unless the ground planes are connected together near the AD7195.

In systems where AGND and DGND are connected elsewhere in the system, they should not be connected again at the AD7195 because this would result in a ground loop. In these

situations, it is recommended that the ground pins of the AD7195 be tied to the AGND plane.

In any layout, the user must keep in mind the flow of currents in the system, ensuring that the paths for all currents are as close as possible to the paths the currents took to reach their destinations. Avoid forcing digital currents to flow through the AGND.

Avoid running digital lines under the device because this couples noise onto the die and allow the analog ground plane to run under the AD7195 to prevent noise coupling. The power supply lines to the AD7195 must use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Shield fast switching signals like clocks with digital ground to prevent radiating noise to other sections of the board, and never run clock signals near the analog inputs. Avoid crossover of digital and analog signals. Run traces on opposite sides of the board at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, whereas signals are placed on the solder side.

Good decoupling is important when using high resolution ADCs. Decouple all analog supplies with 10 F tantalum in parallel with

0.1 F capacitors to AGND. To achieve the best from these decoupling components, place them as close as possible to the device, ideally right up against the device. Decouple all logic chips with 0.1 F ceramic capacitors to DGND. In systems in which a common supply voltage is used to drive both the AV of the AD7195, it is recommended that the system AV

and DVDD

supply

be used. For this supply, place the recommended analog supply decoupling capacitors between the AV

pin of the AD7195 and

AGND and the recommended digital supply decoupling capacitor between the DV

pin of the AD7195 and DGND.

Rev. 0 | Page 42 of 44

AD7195

APPLICATIONS INFORMATION

The AD7195 provides a low-cost, high resolution analog-todigital function. Because the analog-to-digital function is provided by a Σ-∆ architecture, the part is more immune to noisy environments, making it ideal for use in sensor measurement and industrial and process control applications.

WEIGH SCALES

Figure 50 shows the AD7195 being used in a weigh scale application which uses ac excitation. The load cell is arranged in a bridge network and gives a differential output voltage between its OUT+ and OUT– terminals. Assuming a 5 V excitation voltage, the full

-scale output range from the transducer is 10 mV when the sensitivity is 2 mV/V. The excitation voltage for the bridge can be used to directly provide the reference for the ADC because the reference input range includes the supply voltage.

With ac-excitation, the excitation voltage to the load cell is changed on each phase. In Phase 1, the T2 and T4 transistors are turned on using ACX1 and transistors are turned off. The bridge is forward biased. During Phase 2, Transistor T1 and Transistor T3 are turned on using

ACX1

while the T1 and T3

ACX2 and bridge is reversed while the analog input signal and the reference voltage are also reversed. The AD7195 averages the conversions from the two phases so that any offsets and thermal affects are cancelled.

AC excitation is enabled by setting Bit ACX in the configuration register to 1. When the ACX bit is set to 0, the bridge is dc excited. When the AD7195 is in power-down mode, the bridge is disconnected from the excitation voltage, which minimizes power consumption of the system. Following a reset, the ac excitation pins are undefined for a few milliseconds. Thus, pullup/pull-down resistors should be used on the pins to prevent the excitation voltage being shorted to AGND.

For simplicity, external filters are not included in Figure 50. However, an R-C antialias filter must be included on each analog input. This is required because the on-chip digital filter does not provide any rejection around the modulator sampling frequency or multiples of this frequency.

ACX2

. In this phase, the excitation voltage to the

DGND

PGA

EXCITATION

CLOCK

Σ-Δ

ADC

REFERENCE

DETECT

SERIAL

INTERFACE

AND

CONTROL

LOGIC

CLOCK

CIRCUITRY

MCLK1 MCLK2

DOUT/RDY DIN SCLK CS SYNC

8771-032

IN+

OUT–

IN–

T3 T4

OUT+

1MΩ

AGND

AD7195

MUX

AGND

TEMP

SENSOR

ACX1 ACX1 ACX2ACX2

REFIN(+) AIN1

AIN2 AIN3 AIN4

AINCOM REFIN(–)

BPDSW

Figure 50. Typical Application (Weigh Scale)

Rev. 0 | Page 43 of 44

AD7195

OUTLINE DIMENSIONS

PIN 1

INDI

ATOR

0.80

0.75

0.70

EATING

PLANE

5.10

5.00 SQ

4.90

0.05 MAX

0.02 NOM

0.20 REF

0.50

BSC

0.50

0.40

0.30

COPLANARITY

0.08

0.30

0.25

0.18

EXPOSED

BOTTOM VI EWTOP VIEW

PAD

916

FOR PROPER CONNECTION O F THE EXPOSED PAD, REFER TO THE PIN CONF IGURATIO N AND FUNCTION DESCRI P T I O NS SECTION O F THIS DATA SHEET.

3.65

3.50 SQ

3.45

0.25 MIN

COMPLIANT TO JEDEC STANDARDS MO-220-W HHD.

112408-A

Figure 51. 32-Lead Lead Frame Chip Scale Package [LFCSP-WQ]

5 mm × 5 mm Body, Very Very Thin Quad

(CP-32-11)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD7195BCPZ –40°C to +105°C 32-Lead LFCSP_WQ CP-32-11 AD7195BCPZ-RL –40°C to +105°C 32-Lead LFCSP_WQ CP-32-11 AD7195BCPZ-RL7 –40°C to +105°C 32-Lead LFCSP_WQ CP-32-11

Z = RoHS Compliant Part.

Rev. 0 | Page 44 of 44

Datasheet AD7195 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

INTERFACE

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING CHARACTERISTICS

Circuit and Timing Diagram

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

RMS NOISE AND RESOLUTION

SINC4 CHOP DISABLED

SINC3 CHOP DISABLED

SINC4 CHOP ENABLED

SINC3 CHOP ENABLED

ON-CHIP REGISTERS

COMMUNICATIONS REGISTER

STATUS REGISTER

MODE REGISTER

CONFIGURATION REGISTER

DATA REGISTER

ID REGISTER

GPOCON REGISTER

OFFSET REGISTER

FULL-SCALE REGISTER

ADC CIRCUIT INFORMATION

CLOCK

OVERVIEW

Analog Inputs

Multiplexer

Reference Detect

Burnout Currents

Σ-Δ ADC and Filter

AC Excitation

Serial Interface

Temperature Sensor

Calibration

ANALOG INPUT CHANNEL

REFERENCE

REFERENCE DETECT

BIPOLAR/UNIPOLAR CONFIGURATION

DATA OUTPUT CODING

BURNOUT CURRENTS

AC EXCITATION

CHANNEL SEQUENCER

Single Conversion Mode

Continuous Conversion Mode

Continuous Read

RESET

SYSTEM SYNCHRONIZATION

CLOCK

ENABLE PARITY

TEMPERATURE SENSOR

BRIDGE POWER-DOWN SWITCH

CALIBRATION

DIGITAL FILTER

SINC4 FILTER (CHOP DISABLED)

Sinc4 Output Data Rate/Settling Time

Sinc4 Zero Latency

Sinc4 50 Hz/60 Hz Rejection

SINC3 FILTER (CHOP DISABLED)

Sinc3 Output Data Rate and Settling Time

Sinc3 Zero Latency

Sinc3 50 Hz/60 Hz Rejection

CHOP ENABLED (SINC4 FILTER)

Output Data Rate and Settling Time (Sinc4 Chop Enabled)

50 Hz/60 Hz Rejection (Sinc4 Chop Enabled)

CHOP ENABLED (SINC3 FILTER)

Output Data Rate and Settling Time (Sinc3 Chop Enabled)

50 Hz/60 Hz Rejection (Sinc3 Chop Enabled)

SUMMARY OF FILTER OPTIONS