ANALOG DEVICES AD7194 Service Manual

8-Channel, 4.8 kHz, Ultralow Noise,

FEATURES

Fast settling filter option 8 differential/16 pseudo differential input channels RMS noise: 11 nV at 4.7 Hz (gain = 128)

15.5 noise-free bits at 2.4 kHz (gain = 128) Up to 22 noise-free bits (gain = 1) Offset drift: ±5 nV/°C Gain drift: ±1 ppm/°C Programmable gain (1 to 128) Output data rate: 4.7 Hz to 4.8 kHz Internal or external clock Simultaneous 50 Hz/60 Hz rejection 4 general-purpose digital outputs Power supply

: 3 V to 5.25 V

: 2.7 V to 5.25 V

Current: 4.65 mA Temperature range: −40°C to +105°C Package: 32-lead LFCSP Interface

3-wire serial SPI, QSPI™, MICROWIRE™, and DSP compatible Schmitt trigger on SCLK

APPLICATIONS

PLC/DCS analog input modules Data acquisition Strain gage transducers

FUNCTIONAL BLOCK DIAGRAM

AVDDAGND

AIN1/P3

AIN2/P2 IN3/P1/REFIN2(+) IN4/P0/REFIN2(–)

AIN5

AIN16

AINCOM

MUX

SENSOR

24-Bit Sigma-Delta ADC with PGA

Pressure measurement Temperature measurement Flow measurement Weigh scales Chromatography Medical and scientific instrumentation

GENERAL DESCRIPTION

The AD7194 is a low noise, complete analog front end for high precision measurement applications. It contains a low noise, 24-bit sigma-delta (Σ-) analog-to-digital converter (ADC). The on-chip low noise gain stage means that signals of small amplitude can interface directly to the ADC.

The device can be configured to have eight differential inputs or sixteen pseudo differential inputs. The on-chip 4.92 MHz clock can be used as the clock source to the ADC or, alternatively, an external clock or crystal can be used. The output data rate from the part can be varied from 4.7 Hz to 4.8 kHz.

The device has a very flexible digital filter, including a fast settling option. Variables such as output data rate and settling time are dependent on the option selected. For applications that require all conversions to be settled, the AD7194 includes zero latency.

The part operates with a power supply from 3 V to 5.25 V. It consumes a current of 4.65 mA, and it is housed in a 32-lead LFCSP package.

DVDDDGND REFIN1(+) REFIN1(–)

AGND

TEMP

AD7194

PGA

Σ-Δ

ADC

REFERENCE

DETECT

SERIAL

INTERFACE

AND

CONTROL

LOGIC

CLOCK

CIRCUITRY

AD7194

DOUT/RDY DIN SCLK CS

MCLK1 MCLK2

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

8566-001

AD7194

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ................................................................ 7

Absolute Maximum Ratings ............................................................ 9

Thermal Resistance ...................................................................... 9

ESD Caution .................................................................................. 9

Pin Configuration and Function Descriptions ........................... 10

Typical Performance Characteristics ........................................... 12

RMS Noise and Resolution ............................................................ 15

Sinc4 Chop Disabled ................................................................... 15

Sinc3 Chop Disabled ................................................................... 16

Fast Settling ................................................................................. 17

On-Chip Registers .......................................................................... 18

Communications Register ......................................................... 19

Status Register ............................................................................. 20

Mode Register ............................................................................. 21

Configuration Register .............................................................. 24

Data Register ............................................................................... 27

ID Register ................................................................................... 27

GPOCON Register ..................................................................... 27

Offset Register ............................................................................. 28

Full-Scale Register ...................................................................... 28

ADC Circuit Information .............................................................. 29

Overview ...................................................................................... 29

Analog Input Channel ............................................................... 30

Programmable Gain Array (PGA) ........................................... 30

Reference ..................................................................................... 30

Reference Detect ......................................................................... 31

Bipolar/Unipolar Configuration .............................................. 31

Data Output Coding .................................................................. 31

Burnout Currents ....................................................................... 31

Digital Interface .......................................................................... 32

Reset ............................................................................................. 36

System Synchronization ............................................................ 36

Enable Parity ............................................................................... 36

Clock ............................................................................................ 36

Temperature Sensor ................................................................... 36

Logic Outputs ............................................................................. 37

Calibration ................................................................................... 37

Digital Filter .................................................................................... 39

Sinc4 Filter (Chop Disabled) ..................................................... 39

Sinc3 Filter (Chop Disabled) ..................................................... 41

Chop Enabled (Sinc4 Filter) ...................................................... 43

Chop Enabled (Sinc3 Filter) ...................................................... 45

Fast Settling Mode (Sinc4 Filter) ............................................... 46

Fast Settling Mode (Sinc3 Filter) ............................................... 48

Fast Settling Mode (Chop Enabled) ......................................... 50

Summary of Filter Options ....................................................... 51

Grounding and Layout .................................................................. 52

Applications Information .............................................................. 53

Flowmeter .................................................................................... 53

Outline Dimensions ....................................................................... 54

Ordering Guide .......................................................................... 54

REVISION HISTORY

10/09—Revision 0: Initial Version

Rev. 0 | Page 2 of 56

AD7194

SPECIFICATIONS

AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFINx(+) = +2.5 V or AVDD, REFINx(−) = AGND, MCLK = 4.92 MHz, T

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments1

ADC

Output Data Rate 4.7 4800 Hz Chop disabled

1.17 1200 Hz Chop enabled, sinc4 filter

1.56 1600 Hz Chop enabled, sinc3 filter No Missing Codes2 24 Bits FS[9:0]3 > 1, sinc4 filter 24 Bits

Resolution See the RMS Noise and Resolution section RMS Noise and Output

Data Rates

Integral Nonlinearity

Gain = 12 ±2 ±10 ppm of FSR AVDD = 5 V ±2 ±15 ppm of FSR AVDD = 3 V

Gain > 1 ±5 ±30 ppm of FSR AVDD = 5 V ±15 ±30 ppm of FSR AVDD = 3 V Offset Error ±1 µV Chop enabled, AVDD = 5 V ±0.5 µV Chop enabled, AVDD = 3 V Offset Error Drift vs.

±5 nV/°C Gain = 32 to 128; chop disabled ±5 nV/°C Chop enabled

Gain Error4 ±0.001 % AVDD = 5 V, gain = 1, TA = 25°C (factory

−0.4 % Gain = 128, before full-scale calibration

±0.003 % Gain > 1, after internal full-scale

±0.005 % Gain > 1, after internal full-scale

Gain Drift vs.

Power Supply Rejection 90 dB Gain = 1, VIN = 1 V 95 110 dB Gain > 1, VIN = 1 V/gain Common-Mode Rejection

4, 5

±150/gain µV Chop disabled

Temperature

@ DC 110 dB Gain = 1, VIN = 1 V

@ DC 105 120 dB Gain > 1, VIN = 1 V/gain

@ 50 Hz, 60 Hz2 120 dB 10 Hz output data rate, 50 Hz ± 1 Hz,

@ 50 Hz2 120 dB 50 Hz output data rate, 50 Hz ± 1 Hz

@ 60 Hz2 120 dB 60 Hz output data rate, 60 Hz ± 1 Hz

@ 50 Hz2 115 dB

@ 60 Hz2 115 dB

= T

to T

MIN

See the RMS Noise and Resolution section

±150/gain nV/°C Gain = 1 to 16; chop disabled

±1 ppm/°C

, unless otherwise noted.

MAX

> 4, sinc3 filter

FS[9:0]

calibration conditions)

(see Table 27)

calibration, AV

60 Hz ± 1 Hz

Fast settling, FS[9:0] 50 Hz ± 1 Hz

Fast settling, FS[9:0] 60 Hz ± 1 Hz

≥ 4.75 V

< 4.75 V

= 6, average by 16,

= 5, average by 16,

Rev. 0 | Page 3 of 56

AD7194

Parameter Min Typ Max Unit Test Conditions/Comments1

Normal Mode Rejection2

Sinc4 Filter

Internal Clock

@ 50 Hz, 60 Hz 100 dB 10 Hz output data rate, 50 Hz ± 1 Hz,

74 dB 50 Hz output data rate, REJ606 = 1,

@ 50 Hz 96 dB 50 Hz output data rate, 50 Hz ± 1 Hz

@ 60 Hz 97 dB 60 Hz output data rate, 60 Hz ± 1 Hz External Clock

@ 50 Hz, 60 Hz 120 dB 10 Hz output data rate, 50 Hz ± 1 Hz,

82 dB

@ 50 Hz 120 dB 50 Hz output data rate, 50 Hz ± 1 Hz

@ 60 Hz 120 dB 60 Hz output data rate, 60 Hz ± 1 Hz

Sinc3 Filter

Internal Clock

@ 50 Hz, 60 Hz 75 dB 10 Hz output data rate, 50 Hz ± 1 Hz,

60 dB 50 Hz output data rate, REJ606 = 1,

@ 50 Hz 70 dB 50 Hz output data rate, 50 Hz ± 1 Hz

@ 60 Hz 70 dB 60 Hz output data rate, 60 Hz ± 1 Hz External Clock

@ 50 Hz, 60 Hz 100 dB 10 Hz output data rate, 50 Hz ± 1 Hz,

@ 50 Hz 67 dB 50 Hz output data rate, REJ606 = 1,

@ 50 Hz 95 dB 50 Hz output data rate, 50 Hz ± 1 Hz

@ 60 Hz 95 dB 60 Hz output data rate, 60 Hz ± 1 Hz

Fast Settling

Internal Clock

@ 50 Hz 26 dB

@ 60 Hz 26 dB

External Clock

@ 50 Hz 40 dB

@ 60 Hz 40 dB

ANALOG INPUTS

Differential Input

±V

/gain V VREF = REFINx(+) − REFINx(−),

REF

Voltage Ranges

−(AVDD − 1.25 V)/gain +(AVDD − 1.25 V)/gain V Gain > 1 Absolute AIN Voltage

Limits Unbuffered Mode AGND − 0.05 AVDD + 0.05 V Buffered Mode AGND + 0.25 AVDD − 0.25 V

Analog Input Current

Buffered Mode

Input Current2 −2 +2 nA Gain = 1

−3 +3 nA Gain > 1 Input Current Drift ±5 pA/°C

Unbuffered Mode

Input Current ±3.5 µA/V Gain = 1, input current varies with input

±1 µA/V Gain > 1 Input Current Drift ±0.05 nA/V/°C External clock

±1.6 nA/V/°C Internal clock

60 Hz ± 1 Hz

50 Hz ± 1 Hz, 60 Hz ± 1 Hz

60 Hz ± 1 Hz 50 Hz output data rate, REJ60

50 Hz ± 1 Hz, 60 Hz ± 1 Hz

60 Hz ± 1 Hz

50 Hz ± 1 Hz, 60 Hz ± 1 Hz

60 Hz ± 1 Hz

50 Hz ± 1 Hz, 60 Hz ± 1 Hz

= 6, average by 16, 50 Hz ± 0.5 Hz

FS[9:0]

= 5, average by 16, 60 Hz ± 0.5 Hz

FS[9:0]

= 6, average by 16, 50 Hz ± 0.5 Hz

FS[9:0]

= 5, average by 16, 60 Hz ± 0.5 Hz

FS[9:0]

gain = 1 to 128

voltage

= 1,

Rev. 0 | Page 4 of 56

AD7194

Parameter Min Typ Max Unit Test Conditions/Comments1

REFERENCE INPUT

REFIN Voltage 1 AVDD V REFIN = REFINx(+) − REFINx(−), the

Absolute REFIN Voltage

Limits Average Reference Input

AGND − 0.05 AV

+ 0.05 V

4.5 µA/V

Current Average Reference Input

±0.03 nA/V/°C External clock

Current Drift ±1.3 nA/V/°C Internal clock Normal Mode Rejection2 Same as for

analog inputs

Common-Mode

100 dB

Rejection Reference Detect Levels 0.3 0.6 V

TEMPERATURE SENSOR

Accuracy ±2 °C Applies after user calibration at 25°C Sensitivity 2815 Codes/°C Bipolar mode

BURNOUT CURRENTS

AIN Current 500 nA Analog inputs must be buffered and chop

DIGITAL OUTPUTS (P0 to P3)

Output High Voltage, VOH AVDD − 0.6 V AVDD = 3 V, I 4 V AVDD = 5 V, I Output Low Voltage, VOL 0.4 V AVDD = 3 V, I

0.4 V AVDD = 5 V, I Floating-State Leakage

Current

Floating-State Output

−100 +100 nA

10 pF

Capacitance

INTERNAL/EXTERNAL CLOCK

Internal Clock

Frequency 4.72 5.12 MHz

Duty Cycle 50:50 % External Clock/Crystal

Frequency 2.4576 4.9152 5.12 MHz

Input Low Voltage, V

0.8 V DVDD = 5 V

INL

0.4 V DVDD = 3 V

Input High Voltage, V

2.5 V DVDD = 3 V

INH

3.5 V DVDD = 5 V

Input Current −10 +10 µA

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V

2 V

INH

0.8 V

INL

Hysteresis2 0.1 0.25 V Input Currents −10 +10 µA

LOGIC OUTPUT (DOUT/

Output High Voltage, V

RDY)

DVDD − 0.6 V DVDD = 3 V, I

4 V DVDD = 5 V, I Output Low Voltage, V

0.4 V DVDD = 3 V, I

0.4 V DVDD = 5 V, I Floating-State Leakage

−10 +10 µA

Current Floating-State Output

10 pF

Capacitance Data Output Coding Offset binary

differential input must be limited to ±(AV

− 1.25 V)/gain when gain > 1

disabled

= 100 A

SOURCE

= 200 A

SOURCE

= 100 A

SINK

= 800 A

SINK

= 100 µA

SOURCE

= 200 µA

SOURCE

= 100 µA

SINK

= 1.6 mA

SINK

Rev. 0 | Page 5 of 56

AD7194

Parameter Min Typ Max Unit Test Conditions/Comments1

SYSTEM CALIBRATION2

Full-Scale Calibration Limit 1.05 × FS V Zero-Scale Calibration

Limit

Input Span 0.8 × FS 2.1 × FS V

POWER REQUIREMENTS7

Power Supply Voltage AVDD − AGND 3 5.25 V DVDD − DGND 2.7 5.25 V Power Supply Currents

AIDD Current 0.85 1.1 mA Gain = 1, buffer off 1 1.35 mA Gain = 1, buffer on

2.8 3.6 mA Gain = 8, buffer off

3.2 3.85 mA Gain = 8, buffer on

3.8 4.7 mA Gain = 16 to 128, buffer off

4.3 5.3 mA Gain = 16 to 128, buffer on DIDD Current 0.35 0.4 mA DVDD = 3 V

0.5 0.6 mA DVDD = 5 V

1.5 mA External crystal used IDD 3 µA Power-down mode

Temperature range: −40°C to +105°C.

Specification is not production tested, but is supported by characterization data at initial product release.

FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register.

Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system

full-scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.

The analog inputs are configured for differential mode.

REJ60 is a bit in the mode register. When the first notch of the sinc filter is at 50 Hz, a notch is placed at 60 Hz when REJ60 is set to 1. This gives simultaneous

50 Hz/60 Hz rejection.

Digital inputs equal to DVDD or DGND.

−1.05 × FS V

Rev. 0 | Page 6 of 56

AD7194

TIMING CHARACTERISTICS

AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.

Table 2.

Parameter Limit at T

MIN

, T

(B Version) Unit Conditions/Comments

MAX

1, 2

READ AND WRITE OPERATIONS

t3 100 ns min SCLK high pulse width t4 100 ns min SCLK low pulse width

READ OPERATION

t1 0 ns min

falling edge to DOUT/RDY active time

CS 60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V

0 ns min SCLK active edge to data valid delay4

60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V

5, 6

10 ns min

Bus relinquish time after CS

inactive edge 80 ns max t6 0 ns min t7 10 ns min

SCLK inactive edge to CS SCLK inactive edge to DOUT/RDY

inactive edge

high

WRITE OPERATION

t8 0 ns min

falling edge to SCLK active edge setup time4

CS t9 30 ns min Data valid to SCLK edge setup time t10 25 ns min Data valid to SCLK edge hold time t11 0 ns min

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.

See Figure 3 and Figure 4.

These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.

The SCLK active edge is the falling edge of SCLK.

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number

is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.

RDY

returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once.

rising edge to SCLK edge hold time

RDY

Rev. 0 | Page 7 of 56

AD7194

Circuit and Timing Diagrams

CS (I)

DOUT/RDY (O)

SCLK (I)

(1.6mA WITH DVDD = 5V,

SINK

OUTPUT

50pF

100µA WIT H DV

SOURCE

100µA WIT H DV

= 3V)

1.6V

(200µA WIT H DVDD = 5V,

= 3V)

Figure 2. Load Circuit for Timing Characterization

MSB LSB

I = INPUT, O = OUTPUT

Figure 3. Read Cycle Timing Diagram

08566-002

08566-003

CS (I)

08566-004

CLK (I)

DIN (I)

I = INPUT, O = OUT PUT

MSB LSB

Figure 4. Write Cycle Timing Diagram

Rev. 0 | Page 8 of 56

AD7194

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to AGND −0.3 V to +6.5 V

to AGND −0.3 V to +6.5 V

AGND to DGND −0.3 V to +0.3 V Analog Input Voltage to AGND −0.3 V to AVDD + 0.3 V Reference Input Voltage to AGND −0.3 V to AVDD + 0.3 V Digital Input Voltage to DGND −0.3 V to DVDD + 0.3 V Digital Output Voltage to DGND −0.3 V to DVDD + 0.3 V AINx/Digital Input Current 10 mA Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C Lead Temperature, Soldering Reflow 260°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θJA θ

32-Lead LFCSP 32.5 32.71 °C/W

Unit

ESD CAUTION

Rev. 0 | Page 9 of 56

AD7194

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SCLK

MCLK2

MCLK1

32313029282726

AIN1/P3

2 AIN3/P1/REFIN2(+) AIN4/P0/REFIN2(–)

NOTES

1. NC = NO CONNECT.

2. CONNECT EXP OSED PAD TO AGND.

AIN2/P2

AINCOM

AGND

AIN5 AIN6

AD7194

TOP VIEW

(Not to S cale)

10111213141516

AIN7

AIN8

AIN9

AIN10

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 AIN1/P3

Analog Input/Digital Output Pin. This pin can function as an analog input pin. When the GP32EN bit is set to 1, the pin functions as a general-purpose output bit referenced between AV

2 AIN2/P2

Analog Input/Digital Output Pin. This pin can function as an analog input pin. When the GP32EN bit is set to 1, the pin functions as a general-purpose output bit referenced between AVDD and AGND.

3 AIN3/P1/REFIN2(+)

Analog Input/Digital Output Pin/Positive Reference Input. This pin functions as an analog input pin. When the GP10EN bit is set to 1, the pin functions as a general-purpose output bit referenced between AV AGND. When the REFSEL bit in the configuration register is set to 1, this pin functions as REFIN2(+). An external reference can be applied between REFIN2(+) and REFIN2(−). REFIN2(+) can lie anywhere between AV

and AGND + 1 V.

4 AIN4/P0/REFIN2(−)

Analog Input/Digital Output Pin/Positive Reference Input. This pin functions as an analog input pin. When the GP10EN bit is set to 1, the pin functions as a general-purpose output bit referenced between AVDD and AGND. When the REFSEL bit in the configuration register is set to 1, this pin functions as REFIN2(−). An external reference can be applied between REFIN2(+) and REFIN2(−). This reference input can lie anywhere between AGND and AV

− 1 V. 5 AINCOM Analog Input AIN1 to Analog Input AIN16 are referenced to this input when the bit pseudo is set to 1. 6 AGND Analog Ground Reference Point. 7 AIN5 Analog Input Pin. 8 AIN6 Analog Input Pin. 9 AIN7 Analog Input Pin. 10 AIN8 Analog Input Pin. 11 AIN9 Analog Input Pin. 12 AIN10 Analog Input Pin. 13 AIN11 Analog Input Pin. 14 AIN12 Analog Input Pin. 15 AIN13 Analog Input Pin. 16 AIN14 Analog Input Pin. 17 REFIN1(+)

Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−). REFIN1(+) can lie anywhere between AV REFIN1(−)), is AV

, but the part functions with a reference from 1 V to AVDD.

18 REFIN1(−) Negative Reference Input. This reference input can lie anywhere between AGND and AVDD − 1 V. 19 AIN15 Analog Input Pin. 20 AIN16 Analog Input Pin. 21 AGND Analog Ground Reference Point. 22 DGND Digital Ground Reference Point.

SYNC

DIN

DOUT/RD

24 DV

DGND

AGND

21 20

AIN16

AIN15

REFIN1(–)

17 REFIN1(+)

AIN11

AIN12

AIN13

AIN14

08566-005

and AGND.

and AGND + 1 V. The nominal reference voltage, (REFIN1(+) −

and

Rev. 0 | Page 10 of 56

AD7194

Pin No. Mnemonic Description

23 AVDD

24 DVDD

SYNC

Logic input that allows for synchronization of the digital filters and analog modulators when using a

Analog Supply Voltage, 3 V to 5.25 V. AV with AV

at 5 V or vice versa.

Digital Supply Voltage, 2.7 V to 5.25 V. DV with DV

at 5 V or vice versa.

number of AD7194 devices. While SYNC calibration control logic are reset, and the analog modulator is also held in its reset state. SYNC affect the digital interface but does reset RDY internally to DV

26 NC This pin should be connected to GND for correct operation. 27

DOUT/RDY

Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data

output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY

pin. With CS low, the data-/control-word information is placed on the DOUT/RDY pin on the

SCLK falling edge and is valid on the SCLK rising edge.

28 DIN

Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers in the ADC, with the register selection bits of the communications register identifying the appropriate register.

29 MCLK1

When the master clock for the device is provided externally by a crystal, the crystal is connected between MCLK1 and MCLK2.

30 MCLK2

Master Clock Signal for the Device. The AD7194 has an internal 4.92 MHz clock. This internal clock can be made available on the MCLK2 pin. The clock for the AD7194 can also be provided externally in the form of a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin can be driven with a CMOS-compatible clock and with the MCLK1 pin remaining unconnected.

31 SCLK

Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitttriggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information transmitted to or from the ADC in smaller batches of data.

Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the

ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS with SCLK, DIN, and DOUT used to interface with the device.

is independent of DVDD. Therefore, DVDD can be operated at 3 V

is independent of AVDD. Therefore, AVDD can be operated at 3 V

is low, the nodes of the digital filter, the filter control logic, and the

does not

to a high state if it is low. SYNC has a pull-up resistor

operates as a data ready pin, going low

falling edge can be used as an interrupt to a processor,

can be hardwired low, allowing the ADC to operate in 3-wire mode

Rev. 0 | Page 11 of 56

AD7194

TYPICAL PERFORMANCE CHARACTERISTICS

8,387,952

8,387,950

8,387,948

8,387,946

8,387,944

CODE

8,387,942

8,387,940

8,387,938

8,387,936

8,387,934

0 200 400 600 800 1000

Figure 6. Noise (V

Gain = 128, Chop Disabled, Sinc

200

SAMPLE

= AVDD = 5 V, Output Data Rate = 4.7 Hz,

REF

Filter)

08566-006

OCCURRENCE

8,388,830 8,388,860 8,388,890 8,388,920

CODE

Figure 9. Noise Distribution Histogram (V

= AVDD = 5 V,

REF

Output Data Rate = 2400 Hz, Gain = 1, Chop Disabled, Sinc

8,388,880

8,388,878

Filter)

08566-009

150

100

OCCURRENCE

8,387,936

Figure 7. Noise Distribution Histogram (V

8,387,938

8,387,940

8,387,942

8,387,944

CODE

8,387,946

8,387,948

= AVDD = 5 V,

REF

Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc

8,388,920

8,388,910

8,388,900

8,388,890

8,388,880

CODE

8,388,870

8,388,860

8,388,850

8,388,840

8,388,830

0 200 400 600 800 1000

SAMPLE

Figure 8. Noise (V

= AVDD = 5 V, Output Data Rate = 2400 Hz,

REF

Gain = 1, Chop Disabled, Sinc

Filter)

8,387,950

Filter)

8,388,876

8,388,874

8,388,872

CODE

8,388,870

8,388,868

8,388,866

8,388,864

0 200 400 600 800 1000

8566-007

Figure 10. Noise (V

= AVDD = 5 V, Output Data Rate = 42.1 Hz (FS[9:0] = 6,

REF

Average by 16), Gain = 1, Chop Disabled, Sinc

200

150

100

OCCURRENCE

8,388,864 8,388,868 8,388,872 8,388,876 8,388,880

08566-008

Figu re 11. Noise Distribution Histogram (V

SAMPLE

Filter)

CODE

= AVDD = 5 V, Output Data Rate =

REF

42.1 Hz (FS[9:0] = 6, Average by 16), Gain = 1, Chop Disabled, Sinc

Filter)

08566-010

08566-011

Rev. 0 | Page 12 of 56

AD7194

0.6

INL (ppm of FSR)

–1

–2

–4–3–2–101234

VIN (V)

Figure 12. INL (Gain = 1)

–5

INL (ppm of FSR)

–10

–15

–20

–0.03 –0.02 –0.01 0 0.01 0.02 0.03

VIN (V)

Figure 13. INL (Gain = 128)

0.5

0.4

0.3

0.2

OFFSET ERROR (μV)

0.1

–60 –40 –20 0 20 40 60 80 100 120

08566-012

TEMPERAUTRE (°C)

08566-067

Figure 15. Offset vs. Temperature (Gain = 128, Chop Disabled)

1.000008

1.000006

1.000004

1.000002

1.000000

0.999998

GAIN

0.999996

0.999994

0.999992

0.999990

0.999988 –60 –40 –20 0 20 40 60 80 100 120

08566-013

TEMPERATURE (°C)

08566-016

Figure 16. Gain vs. Temperature (Gain = 1)

170

168

166

164

162

OFFSET (µV)

160

158

156

154

–60 –40 –20 0 20 40 60 80 100 120

TEMPERATURE ( °C)

Figure 14. Offset vs. Temperature (Gain = 1, Chop Disabled)

08566-014

Rev. 0 | Page 13 of 56

128.004

128.002

128.000

127.998

127.996

GAIN

127.994

127.992

127.990

127.988 –60 –40 –20 0 20 40 60 80 100 120

TEMPERATURE (°C)

Figure 17. Gain vs. Temperature (Gain = 128)

08566-017

AD7194

GAIN = 1 GAIN = 8 GAIN = 16 GAIN = 32 GAIN = 64 GAIN = 128

GAIN = 1 GAIN = 8

NOISE FREE RESOL UTION (Bits)

Figure 18. Noise-Free Resolution (Sinc

GAIN = 16 GAIN = 32 GAIN = 64 GAIN = 128

1 10 100 1k 10k

OUTPUT DATA RAT E (Hz)

Filter, Chop Disabled, V

GAIN = 1

NOISE FREE RESOLUTION (Bits)

GAIN = 8 GAIN = 16

GAIN = 32 GAIN = 64 GAIN = 128

1 10 100 1k 10k

OUTPUT DATA RATE (Hz)

Figure 19. Noise-Free Resolution (Sinc3 Filter, Chop Disabled, V

REF

= 5 V)

NOISE FREE RESOLUTION (Bits)

1 10 100 1k

08566-069

Figure 20. Noise-Free Resolution in Fast Settling Mode (V

Averaging by 16, Sinc

OUTPUT DATA RATE (Hz)

Filter, Chop Disabled)

REF

08566-068

= 5 V,

08566-070

Rev. 0 | Page 14 of 56

AD7194

RMS NOISE AND RESOLUTION

The following tables show the rms noise, peak-to-peak noise, effective resolution, and noise-free (peak-to-peak) resolution of the AD7194 for various output data rates and gain settings with chop disabled for the sinc

and sinc3 filters and for fast settling mode. The numbers given are for the bipolar input range with an external 5 V reference. These numbers are typical and are generated with a differential input voltage of 0 V when the ADC

SINC4 CHOP DISABLED

Table 6. RMS Noise (nV) vs. Gain and Output Data Rate

Filter Word (Decimal)

1023 4.7 852.5 370 57 35 18 13 11 640 7.5 533 440 73 41 24 17 13 480 10 400 470 83 45 28 18 16 96 50 80 1100 150 85 52 38 34 80 60 66.7 1200 170 94 56 42 38 32 150 26.7 1800 260 150 86 65 59 16 300 13.3 2500 360 210 130 95 83 5 960 4.17 4500 640 370 230 170 150 2 2400 1.67 7500 1100 600 380 280 240 1 4800 0.83 26,000 3400 1800 940 550 390

Output Data Rate (Hz)

Settling Time (ms)

is continuously converting on a single channel. It is important to note that the effective resolution is calculated using the rms noise, whereas the peak-to-peak resolution is calculated based on peak-to-peak noise. The peak-to-peak resolution represents the resolution for which there is no code flicker. With chop enabled, the resolution improves by 0.5 bits.

Gain of

1 8 16 32 64 128

Table 7. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate

Filter Word (Decimal)

1023 4.7 852.5 2200 340 200 120 84 70 640 7.5 533 2700 430 260 150 100 85 480 10 400 3000 480 300 170 120 100 96 50 80 6600 950 540 350 250 210 80 60 66.7 7200 1000 610 370 270 220 32 150 26.7 11,000 1600 970 580 430 370 16 300 13.3 17,000 2400 1400 840 620 530 5 960 4.17 35,000 4800 2500 1500 1100 1000 2 2400 1.67 56,000 7500 4200 2900 1800 1700 1 4800 0.83 175,000 23,000 12,000 7100 3600 2600

Output Data Rate (Hz)

Settling Time (ms)

1 8 16 32 64 128

Gain of

Table 8. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate

Filter Word (Decimal)

1023 4.7 852.5 24 (22.1) 24 (21.8) 24 (21.6) 24 (21.3) 23.5 (20.8) 22.8 (20.1) 640 7.5 533 24 (21.8) 24 (21.5) 23.9 (21.2) 23.6 (21) 23.1 (20.6) 22.5 (19.8) 480 10 400 24 (21.7) 24 (21.3) 23.7 (21) 23.4 (20.8) 23 (20.3) 22.2 (19.6) 96 50 80 23.1 (20.5) 23 (20.3) 22.8 (20.1) 22.5 (19.8) 22 (19.3) 21.1 (18.5) 80 60 66.7 23 (20.4) 22.9 (20.3) 22.7 (20) 22.4 (19.7) 21.8 (19.1) 21 (18.4) 32 150 26.7 22.4 (19.8) 22.3 (19.6) 22 (19.3) 21.8 (19) 21.2 (18.5) 20.3 (17.7) 16 300 13.3 21.9 (19.2) 21.8 (19) 21.5 (18.8) 21.2 (18.5) 20.7 (17.9) 19.8 (17.2) 5 960 4.17 21.1 (18.4) 21 (18) 20.7 (17.9) 20.4 (17.7) 19.8 (17.1) 19 (16.3) 2 2400 1.67 20.4 (17.6) 20.3 (17.3) 20 (17.2) 19.6 (16.7) 19.1 (16.4) 18.3 (15.5) 1 4800 0.83 18.6 (15.8) 18.5 (15.7) 18.4 (15.7) 18.3 (15.4) 18.1 (15.4) 17.6 (14.9)

The output peak-to-peak (p-p) resolution is listed in parentheses.

Output Data Rate (Hz)

Settling Time (ms)

1 8 16 32 64 128

Gain of

Rev. 0 | Page 15 of 56

AD7194

SINC3 CHOP DISABLED

Table 9. RMS Noise (nV) vs. Gain and Output Data Rate

Output Data

Filter Word (Decimal)

1023 4.7 639.4 380 58 35 20 13 11 640 7.5 400 450 73 41 25 17 14 480 10 300 490 90 47 28 19 16 96 50 60 1100 160 92 54 40 36 80 60 50 1200 170 99 59 43 39 32 150 20 1900 280 160 91 72 63 16 300 10 2700 380 210 130 97 87 5 960 3.13 6400 870 490 280 200 170 2 2400 1.25 115,000 14,000 7000 3600 1800 950 1 4800 0.625 860,000 110,000 54,000 28,000 14,000 7000

Rate (Hz)

Settling Time (ms)

1 8 16 32 64 128

Table 10. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate

Output Data

Filter Word (Decimal)

1023 4.7 639.4 2300 350 220 130 84 70 640 7.5 400 2700 450 270 160 110 88 480 10 300 3100 520 310 180 120 100 96 50 60 7200 990 560 370 260 230 80 60 50 7800 1100 630 390 270 250 32 150 20 13,000 1800 1000 580 480 400 16 300 10 19,000 2500 1400 860 640 560 5 960 3.13 410,000 5700 3200 1800 1300 1100 2 2400 1.25 730,000 93,000 47,000 24,000 12,000 6100 1 4800 0.625 5,700,000 730,000 360,000 180,000 93,000 45,000

Rate (Hz)

Settling Time (ms)

1 8 16 32 64 128

Gain of

Table 11. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate

Output Data

Filter Word (Decimal)

1023 4.7 639.4 24 (22.1) 24 (21.8) 24 (21.4) 23.9 (21.2) 23.5 (20.8) 22.8 (20.1) 640 7.5 400 24 (21.8) 24 (21.4) 23.9 (21.1) 23.6 (20.9) 23.1 (20.4) 22.4 (19.8) 480 10 300 24 (21.6) 23.8 (21.2) 23.7 (20.9) 23.4 (20.7) 23 (20.3) 22.2 (19.6) 96 50 60 23.1 (20.4) 22.9 (20.3) 22.7 (20.1) 22.5 (19.7) 21.9 (19.2) 21 (18.4) 80 60 50 23 (20.3) 22.8 (20.1) 22.6 (19.9) 22.3 (19.6) 21.8 (19.1) 20.9 (18.3) 32 150 20 22.3 (19.6) 22.1 (19.4) 21.9 (19.3) 21.7 (19) 21 (18.3) 20.2 (17.6) 16 300 10 21.8 (19) 21.6 (18.9) 21.56 (18.8) 21.2 (18.5) 20.6 (17.9) 19.8 (17.1) 5 960 3.13 20.6 (17.9) 20.5 (17.7) 20.3 (17.6) 20.1 (17.4) 19.6 (16.9) 18.8 (16.1) 2 2400 1.25 16.5 (13.7) 16.4 (13.7) 16.4 (13.7) 16.4 (13.7) 16.4 (13.7) 16.4 (13.6) 1 4800 0.625 13.5 (10.8) 13.5 (10.7) 13.5 (10.7) 13.5 (10.7) 13.5 (10.7) 13.5 (10.7)

The output peak-to-peak (p-p) resolution is listed in parentheses.

Rate (Hz)

Settling Time (ms)

1 8 16 32 64 128

Gain of1

Rev. 0 | Page 16 of 56

AD7194

FAST SETTLING

Table 12. RMS Noise (nV) vs. Gain and Output Data Rate

Filter Wo rd (Decimal)

96 16 2.63 380 410 87 52 33 15 12 30 16 8.4 118.75 700 140 71 43 30 21 6 16 42.10 23.75 1500 270 150 82 56 47 5 16 50.53 19.79 1600 280 160 88 61 52 2 16 126.32 7.92 2700 380 210 130 94 85 1 16 252.63 3.96 3700 540 300 190 140 120

Average

Output Data Rate (Hz)

Settling Time (ms)

1 8 16 32 64 128

Table 13. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate

Filter Wo rd (Decimal) Average

96 16 2.63 380 2500 450 260 180 100 70 30 16 8.4 118.75 4200 900 470 280 190 130 6 16 42.10 23.75 10,000 1800 950 540 360 300 5 16 50.53 19.79 11,000 1900 1000 580 390 330 2 16 126.32 7.92 16,000 2800 1500 850 580 510 1 16 252.63 3.96 23,000 4500 2000 1200 850 740

Output Data Rate (Hz)

Settling Time (ms)

1 8 16 32 64 128

Gain of

Table 14. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate

Filter Wo rd (Decimal) Average

96 16 2.63 380 24 (21.9) 23.8 (21.4) 23.5 (21.2) 23.2 (20.7) 23.3 (20.6) 22.6 (20.1) 30 16 8.4 118.75 23.8 (21.2) 23.1 (20.4) 23.1 (20.3) 22.8 (20.1) 22.3 (19.6) 21.8 (19.2) 6 16 42.10 23.75 22.7 (19.9) 22.1 (19.4) 22 (19.3) 21.9 (19.1) 21.4 (18.7) 20.7 (18) 5 16 50.53 19.79 22.6 (19.8) 22.1 (19.3) 21.9 (19.3) 21.8 (19) 21.3 (18.6) 20.5 (17.9) 2 16 126.32 7.92 21.8 (19.3) 21.6 (18.8) 21.5 (18.7) 21.2 (18.5) 20.7 (18) 19.8 (17.2) 1 16 252.63 3.96 21.4 (18.7) 21.1 (18.1) 21 (18.3) 20.6 (18) 20.1 (17.5) 19.3 (16.7)

The output peak-to-peak (p-p) resolution is listed in parentheses.

Output Data Rate (Hz)

Settling Time (ms)

1 8 16 32 64 128

Gain of1

Rev. 0 | Page 17 of 56

+ 39 hidden pages

ANALOG DEVICES AD7194 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING CHARACTERISTICS

Circuit and Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

RMS NOISE AND RESOLUTION

SINC4 CHOP DISABLED

SINC3 CHOP DISABLED

FAST SETTLING