ANALOG DEVICES AD7192 Service Manual

4.8 kHz Ultra-Low Noise 24-Bit

)

www.BDTIC.com/ADI

Preliminary Technical Data

FEATURES

RMS Noise: 14 nV @ 7.5 Hz (gain = 128)

15.5 noise free bits @ 2.4 kHz (gain = 128)
Up to 22 noise free bits (gain = 1)
Offset drift: 5 nV/°C
Gain drift: 1 ppm/°C
Specified drift over time
Programmable gain (1 – 128)
Output data rate: 4.7 Hz to 4.8 kHz
Internal or external clock
Simultaneous 50 Hz/60 Hz rejection
Four general purpose digital outputs
Power supply: 3 V to 5.25 V
Current: 3.5 mA
Temperature range: –40°C to +105°C

INTERFACE

3-wire serial
SPI®, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK

APPLICATIONS

Weigh scales
Strain gauge transducers
Pressure measurement

Temperature measurement
Chromatography

FUNCTIONAL BLOCK DIAGRAM

DD

AGNDAV

DD

DGNDDV

Sigma-Delta ADC with PGA

AD7192

PLC/DCS Analog Input Modules
Data Acquisition
Medical and Scientific instrumentation

GENERAL DESCRIPTION

The AD7192 is a low noise, complete analog front end for high
precision measurement applications. It contains a low noise, 24­bit ∑-∆ ADC. The on-chip low noise gain stage means that
signals of small amplitude can be interfaced directly to the
ADC.

The device can be configured to have two differential inputs or
four pseudo-differential inputs. The device can be operated
with either the internal clock or an external clock. The output
data rate from the part can be varied from 4.7 Hz to 4.8 kHz.

The device can be operated with a sinc
At the lower output data rates, the sinc
settling time. The benefit of the sinc
the superior 50 Hz/60 Hz rejection. At the higher output data
rates, the sinc

4

filter gives best noise performance. For
applications that require all conversions to be settled, the
AD7192 includes a zero-latency feature.

The part operates with a power supply from 3 V to 5.25 V. It
consumes a current of 3.5 mA. It is housed in a 24-lead TSSOP
package.

REFIN1(+) REFIN1(-)

3

or a sinc4 digital filter.

3

is useful to optimize the

4

at low output data rates is

REFERENCE

SERIAL

INTERFACE

AND CONTROL

LOGIC

AD7192

PGA

MCLK1

CLOCK

CIRCUITRY

Figure 1.

SIGMA DELTA

ADC

MCLK2

P0/REFIN2(-)P1/REFIN2(+

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2008 Analog Devices, Inc. All rights reserved.

AV

MUX

DD

AGND

SENSOR

TEMP

AIN1
AIN2
AIN3
AIN4

AINCOM

BPDSW

AGND

Rev.PrE 8/08

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

DETECT

DOUT/RDY

DIN

SCLK
CS
SYNC

P3
P2

AD7192 Preliminary Technical Data

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SPECIFICATIONS

AVDD = 3 V to 5.25 V; DVDD = 2.7 V to 5.25 V; GND = 0 V; REFIN1(+) = AVDD ; REFIN1(-) = GND; MCLK = 4.9152 MHz; Sinc4 filter
selected; all specifications T

Table 1.

Parameter1 AD7192B Unit Test Conditions/Comments

Output Data Rate 4.7 to 4800 Hz nom Chop Disabled

1.17 to 1200 Hz nom Chop Enabled
No Missing Codes2 24 Bits min FS > 1
Resolution

RMS Noise and Update Rates

Integral Nonlinearity ±15 ppm of FSR max
Offset Error3 ±100/Gain µV typ Chop Disabled
±0.5 µV typ Chop Enabled
Offset Error Drift vs. Temperature4 ±150/Gain nV/°C typ Gain = 1 to 16. Chop Disabled
±10 nV/°C typ Gain = 32 to 128. Chop Disabled
±5 nV/°C typ Chop Enabled
Offset Error Drift vs. Time 25 nV/1000 Hours typ
Full-Scale Error
Gain Drift vs. Temperature4
Gain Drift vs. Time 10 ppm/1000 Hours typ
Power Supply Rejection 100 dB min VIN = 1 V/Gain. 120 dB typical.

ANALOG INPUTS

Differential Input Voltage Ranges ± V

± (AVDD – 1V)/gain V min/max gain > 1
Absolute AIN Voltage Limits2

Unbuffered Mode

AVDD + 50 mV V max

Buffered Mode GND + 200 mV V min

Analog Input Current

Buffered Mode

Input Current2
±3 nA typ Gain > 1
Input Current Drift ±2 pA/°C typ

Unbuffered Mode

Input Current ±5 µA/V typ Gain = 1. Input current varies with input voltage
±1 µA/V typ Gain > 1.
Input Current Drift ±50 pA/V/°C typ

Normal Mode Rejection2

@ 50 Hz, 60 Hz 98 dB min 10 Hz Output Date Rate, 50 ± 1 Hz, 60 ± 1 Hz
TBD dB min 50 Hz Output Date Rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1

@ 50 Hz TBD dB min 50 Hz Output Date Rate, 50 ± 1 Hz
@ 60 Hz TBD dB min 60 Hz Output Date Rate, 60 ± 1 Hz

Common-Mode Rejection

@ DC 100 dB min AIN = 1 V/gain
@ 50 Hz, 60 Hz2
@ 50 Hz, 60 Hz2

REFERENCE INPUT

3, 5

MIN

to T

, unless otherwise noted.

MAX

See

RMS Noise and
Resolution
Specifications

See

RMS Noise and
Resolution
Specifications

±10 µV typ
±1 ppm/°C typ

/gain V nom

REF

GND − 50 mV

AV

− 200 mV

DD

±1 nA max Gain = 1

100 dB min 10 Hz Output Date Rate, 50 ± 1 Hz, 60 ± 1 Hz
100 dB min 50 ± 1 Hz (50 Hz Output Date Rate), 60 ± 1 Hz (60 Hz

V

= REFIN(+) − REFIN(−) , gain = 1 to 128

REF

V min

V max

Hz

Output Date Rate)

Rev.PrE 8/08 | Page 2

Preliminary Technical Data AD7192

www.BDTIC.com/ADI

Parameter1 AD7192B Unit Test Conditions/Comments

REFIN Voltage AVDD V nom

Reference Voltage Range2

1 V min

AVDD V max The differential input must be limited to ± (AVDD –

Absolute REFIN Voltage Limits2

GND – 50 mV V min

AVDD + 50 mV V max

Average Reference Input Current 6 µA/V typ
Average Reference Input Current

±0.03 nA/V/°C typ

Drift
Normal Mode Rejection2

Same as for analog
inputs

Common-Mode Rejection 100

dB typ

Reference Detect Levels 0.3 V min

0.5 V max
TEMPERATURE SENSOR
Accuracy +2 °C typ Applies after user-calibration at one temperature
Sensitivity 2800 codes/°C typ
LOW SIDE POWER SWITCH
RON 7

9

Allowable Current2

30 mA max Continuous Current

Ω max

Ω max

BURNOUT CURRENTS
AIN Current 500 nA nom
DIGITAL OUTPUTS (P0 – P3)
VOH, Output High Voltage2

VOL, Output Low Voltage2

VOH, Output High Voltage2

VOL, Output Low Voltage2

− 0.6

AV

DD

0.4 V max

4 V min

0.4 V max

V min

Floating-State Leakage Current ±10 µA max

Floating-State Output Capacitance 10 pF typ
INTERNAL/EXTERNAL CLOCK
Internal Clock
Frequency 4.92 + 4% MHz min/max
Duty Cycle 50:50 % typ
External Clock/Crystal
Frequency 4.9152 MHz nom

2.4576/5.12 MHz min/max

V

, Input Low Voltage 0.8 V max DVDD = 5 V

INL

0.4 V max DVDD = 3 V

V

, Input High Voltage 2.5 V min DVDD = 3 V

INH

3.5 V min DVDD = 5 V

Input Current ±10 µA max MCLKIN = DVDD or GND
LOGIC INPUTS

VT(+) 1.4/2 V min/V max DVDD = 5 V
VT(−)

VT(+) − VT(−)

0.8/1.7 V min/V max DV

0.1/0.17 V min/V max DV

VT(+) 0.9/2 V min/V max DVDD = 3 V
VT(−)

VT(+)− VT(−)

0.4/1.35 V min/V max DV

0.06/0.13 V min/V max DV

Input Currents ±10 µA max VIN = DVDD or GND
LOGIC OUTPUT (DOUT/

VOH, Output High Voltage2

VOL, Output Low Voltage2

RDY

)

DV

− 0.6

DD

V min DV

0.4 V max DV

REFIN = REFIN(+) − REFIN(−)

1V)/gain when gain > 1

AVDD = 5 V

AVDD = 3 V

AV

AV

AV

AV

= 3V, I

DD

= 3V, I

DD

= 5V, I

DD

= 5V, I

DD

= 5 V

DD

= 5 V

DD

= 3 V

DD

= 3 V

DD

= 3 V, I

DD

= 3 V, I

DD

= 100 µA

SOURCE

= 100 µA

SINK

= 200 µA

SOURCE

= 800 µA

SINK

SOURCE

= 100 µA

SINK

= 100 µA

Rev.PrE 8/08 | Page 3

AD7192 Preliminary Technical Data

www.BDTIC.com/ADI

Parameter1 AD7192B Unit Test Conditions/Comments

VOH, Output High Voltage2
VOL, Output Low Voltage2

4 V min DV

0.4 V max DV

= 5 V, I

DD

= 5 V, I

DD

Floating-State Leakage Current ±10 µA max
Floating-State Output Capacitance 10 pF typ
Data Output Coding Offset binary

SYSTEM CALIBRATION2

Full-Scale Calibration Limit 1.05 × FS V max
Zero-Scale Calibration Limit

−1.05 × FS

V min

Input Span 0.8 × FS V min

2.1 × FS V max
POWER REQUIREMENTS7

Power Supply Voltage
AVDD − AGND
DVDD − DGND

3/5.25 V min/max

2.7/5.25 V min/max

Power Supply Currents
AIDD Current TBD mA max Gain = 1, Buffer off
TBD mA max Gain = 8, Buffer off
TBD mA max Gain = 8, Buffer on
TBD mA max Gain = 16 – 128, Buffer off
TBD mA max Gain = 16 – 128, Buffer on
DIDD Current TBD mA max DVDD = 3 V
1 mA max DVDD = 5 V
IDD (Power-Down Mode) 1 µA max

1

Temperature range: −40°C to +105°C.

2

Specification is not production tested but is supported by characterization data at initial product release.

3

Following a calibration, this error will be in the order of the noise for the programmed gain and output data rate selected.

4

Recalibration at any temperature will remove these errors.

5

Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AVDD = 5 V, gain = 1, TA = 25°C).

6

REJ60 is a bit in the Mode Register. When the output data rate is set to 50 Hz, setting REJ60 to ‘1’ places a notch at 60 Hz, allowing simultaneous 50 Hz/60 Hz rejection.

7

Digital inputs equal to DV

or GND.

DD

SOURCE

= 1.6 mA

SINK

= 200 µA

Rev.PrE 8/08 | Page 4

Preliminary Technical Data AD7192

www.BDTIC.com/ADI

TIMING CHARACTERISTICS

AVDD = 3 V to 5.25 V; DVDD = 2.7 V to 5.25 V; GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.

Table 2.

Parameter

t

3

t4 100 ns min SCLK low pulse width
Read Operation

t1 0 ns min

60 ns max DVDD = 4.75 V to 5.25 V

80 ns max DVDD = 2.7 V to 3.6 V

t

60 ns max DVDD = 4.75 V to 5.25 V

80 ns max DVDD = 2.7 V to 3.6 V

t

80 ns max

t6 0 ns min

t7 10 ns min
Write Operation

t8 0 ns min

t9 30 ns min Data valid to SCLK edge setup time

t10 25 ns min Data valid to SCLK edge hold time

t11 0 ns min

1

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.

2

See Figure 3 and Figure 4.

3

These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.

4

SCLK active edge is falling edge of SCLK.

5

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number

is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.

6

RDY
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.

1, 2

Limit at T

MIN

, T

(B Version) Unit Conditions/Comments

MAX

100 ns min SCLK high pulse width

falling edge to DOUT/RDY active time

CS

3

0 ns min SCLK active edge to data valid delay4

2

5, 6

10 ns min

5

Bus relinquish time after CS

SCLK inactive edge to CS
SCLK inactive edge to DOUT/RDY

falling edge to SCLK active edge setup time4

CS

rising edge to SCLK edge hold time

CS

returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while

inactive edge

inactive edge

high

RDY

is high,

I

(1.6mA WITH DVDD = 5V,

SINK

100µA WITH DV

TO

OUTPUT

PIN

50pF

I

SOURCE

100µA WITH DV

Figure 2. Load Circuit for Timing Characterization

= 3V)

DD

1.6V

(200µA WITH DVDD = 5V,

= 3V)

DD

04854-002

Rev.PrE 8/08 | Page 5

AD7192 Preliminary Technical Data

S

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TIMING DIAGRAMS

CS (I)

t

t

1

DOUT/RDY (O)

SCLK (I)

t

2

I = INPUT, O = OUTPUT

MSB LSB

t

3

t

4

Figure 3. Read Cycle Timing Diagram

6

t

5

t

7

04854-003

CS (I)

t

11

04854-004

CLK (I)

DIN (I)

I = INPUT, O = OUTPUT

t

8

t

9

t

10

MSB LSB

Figure 4. Write Cycle Timing Diagram

Rev.PrE 8/08 | Page 6

Preliminary Technical Data AD7192

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND

DVDD to GND

Analog Input Voltage to GND

Reference Input Voltage to GND

Digital Input Voltage to GND

Digital Output Voltage to GND

AIN/Digital Input Current 10 mA
Operating Temperature Range

Storage Temperature Range

Maximum Junction Temperature 150°C
TSSOP

θJA Thermal Impedance 97.9°C/W

θJC Thermal Impedance 14°C/W
Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

−0.3 V to +6.5 V

−0.3 V to +6.5 V

−0.3 V to AVDD + 0.3 V

−0.3 V to AVDD + 0.3 V

−0.3 V to DVDD + 0.3 V

−0.3 V to DVDD + 0.3 V

−40°C to +105°C

−65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev.PrE 8/08 | Page 7