ANALOG DEVICES AD7190 Service Manual

4.8 kHz Ultralow Noise 24-Bit

A

www.BDTIC.com/ADI

FEATURES

RMS noise: 8.5 nV @ 4.7 Hz (gain = 128)
16 noise free bits @ 2.4 kHz (gain = 128)
Up to 22.5 noise free bits (gain = 1)
Offset drift: 5 nV/°C
Gain drift: 1 ppm/°C
Specified drift over time
2 differential/4 pseudo differential input channels
Automatic channel sequencer
Programmable gain (1 to 128)
Output data rate: 4.7 Hz to 4.8 kHz
Internal or external clock
Simultaneous 50 Hz/60 Hz rejection
4 general-purpose digital outputs
Power supply

AV

: 4.75 V to 5.25 V

DD

DV

: 2.7 V to 5.25 V

DD

Current: 6 mA
Temperature range: –40°C to +105°C
Interface

3-wire serial
SPI, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK

APPLICATIONS

Weigh scales
Strain gauge transducers
Pressure measurement
Temperature measurement

Sigma-Delta ADC with PGA

AD7190

Chromatography
PLC/DCS analog input modules
Data acquisition
Medical and scientific instrumentation

GENERAL DESCRIPTION

The AD7190 is a low noise, complete analog front end for high
precision measurement applications. It contains a low noise,
24-bit sigma-delta (∑-∆) analog to digital converter (ADC).
The on-chip low noise gain stage means that signals of small
amplitude can be interfaced directly to the ADC.

The device can be configured to have two differential inputs or
four pseudo differential inputs. The on-chip channel sequencer
allows several channels to be enabled, and the AD7190
sequentially converts on each enabled channel. This simplifies
communication with the part. The on-chip 4.92 MHz clock can
be used as the clock source to the ADC or, alternatively, an
external clock or crystal can be used. The output data rate from
the part can be varied from 4.7 Hz to 4.8 kHz.

The device has two digital filter options. The choice of filter
affects the rms noise/noise-free resolution at the programmed
output data rate, the settling time, and the 50 Hz/60 Hz
rejection. For applications that require all conversions to be
settled, the AD7190 includes a zero latency feature.

The part operates with 5 V analog power supply and a digital
power supply from 2.7 V to 5.25 V. It consumes a current of
6 mA. It is housed in a 24-lead TSSOP package.

FUNCTIONAL BLOCK DIAGRAM

AV

AIN1
AIN2
AIN3
AIN4

INCOM

BPDSW

AGND

DD

MUX

AGND

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of p atents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

DGND REFIN1 (+) REF IN1(–)

DV

DD

AD7190

CLOCK

Figure 1.

Σ-Δ

ADC

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

PGA

TEMP

SENSOR

CIRCUITRY

MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+)

REFERENCE

DETECT

SERIAL

INTERFACE

AND

CONTROL

LOGIC

DOUT/RDY

DIN

SCLK

CS

SYNC

P3

P2

07640-001

AD7190

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ................................................................ 7

Circuit and Timing Diagrams ..................................................... 7

Absolute Maximum Ratings ............................................................ 9

Thermal Resistance ...................................................................... 9

ESD Caution .................................................................................. 9

Pin Configuration and Function Descriptions ........................... 10

Typical Performance Characteristics ........................................... 12

RMS Noise and Resolution ............................................................ 15

Sinc4 Chop Disabled ................................................................... 15

Sinc3 Chop Disabled ................................................................... 16

Sinc4 Chop Enabled .................................................................... 17

Sinc3 Chop Enabled .................................................................... 18

On-Chip Registers .......................................................................... 19

Communications Register ......................................................... 19

Status Register ............................................................................. 20

Mode Register ............................................................................. 20

Configuration Register .............................................................. 22

Data Register ............................................................................... 24

GPOCON Register ..................................................................... 24

Offset Register ............................................................................. 25

Full-Scale Register ...................................................................... 25

ADC Circuit Information .............................................................. 26

Overview ..................................................................................... 26

Filter, Output Data Rate, Settling Time ................................... 26

Digital Interface .......................................................................... 29

Circuit Description......................................................................... 33

Analog Input Channel ............................................................... 33

PGA .............................................................................................. 33

Bipolar/Unipolar Configuration .............................................. 33

Data Output Coding .................................................................. 33

Clock ............................................................................................ 33

Burnout Currents ....................................................................... 34

Reference ..................................................................................... 34

Reference Detect ......................................................................... 34

Reset ............................................................................................. 34

System Synchronization ............................................................ 35

Temperature Sensor ................................................................... 35

Bridge Power-Down Switch ...................................................... 35

Logic Outputs ............................................................................. 35

Enable Parity ............................................................................... 35

Calibration ................................................................................... 36

Grounding and Layout .............................................................. 36

Applications Information .............................................................. 38

Weigh Scales ................................................................................ 38

Outline Dimensions ....................................................................... 39

Ordering Guide .......................................................................... 39

REVISION HISTORY

10/08—Revision 0—Initial Version

Rev. 0 | Page 2 of 40

AD7190

www.BDTIC.com/ADI

SPECIFICATIONS

AVDD = 4.75 V to 5.25 V; DVDD = 2.7 V to 5.25 V; GND = 0 V; REFIN1(+) = AVDD ; REFIN1(−) = GND; MCLK = 4.92 MHz; all
specifications T

Table 1.

Parameter AD7190B Unit Test Conditions/Comments1

ADC

Output Data Rate 4.7 to 4800 Hz nom Chop disabled.

1.17 to 1200 Hz nom Chop enabled.
No Missing Codes
24 Bits min FS > 4, sinc3 filter.
Resolution

RMS Noise and Output Data Rates

Integral Nonlinearity ±5 ppm of FSR max ±1 ppm typical, gain = 1.
±15 ppm of FSR max ±5 ppm typical, gain > 1.
Offset Error
±0.5 μV typ Chop enabled.
Offset Error Drift vs. Temperature ±100/gain nV/°C typ Gain = 1 to 16. chop disabled.
±5 nV/°C typ Gain = 32 to 128. chop disabled.
±5 nV/°C typ Chop enabled.
Offset Error Drift vs. Time 25 nV/1000 hours typ Gain ≥ 32
Gain Error
±0.0075 % typ Gain > 1, post internal-calibration.
Gain Drift vs. Temperature ±1 ppm/°C typ
Gain Drift vs. Time 10 ppm/1000 hours typ Gain = 1.
Power Supply Rejection 95 dB typ Gain = 1, VIN = 1 V.
95 dB min Gain > 1, VIN = 1 V/gain. 110 dB typical.
Common-Mode Rejection

@ DC 100 dB min Gain = 1, VIN = 1 V2
110 dB min Gain > 1, VIN = 1 V/gain.
@ 50 Hz, 60 Hz2 120 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz.
@ 50 Hz, 60 Hz2 120 dB min

Normal Mode Rejection

Sinc4 Filter
Internal Clock

@ 50 Hz, 60 Hz 100 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz.
74 dB min

@ 50 Hz 96 dB min 50 Hz output data rate, 50 ± 1 Hz.
@ 60 Hz 97 dB min 60 Hz output data rate, 60 ± 1 Hz.

to T

MIN

3

3, 4

±0.005 % max ±0.001 % typical, gain = 1, AV

, unless otherwise noted.

MAX

2

2

24 Bits min FS > 1, sinc4 filter.

See the RMS Noise and
Resolution section

See the RMS Noise and
Resolution section

±75/gain μV typ Chop disabled.

50 ± 1 Hz (50 Hz output data rate), 60 ± 1 Hz
(60 Hz output data rate).

50 Hz output data rate, REJ60
50 ± 1 Hz, 60 ± 1 Hz.

= 5 V.

DD

5

= 1,

Rev. 0 | Page 3 of 40

AD7190

www.BDTIC.com/ADI

Parameter AD7190B Unit Test Conditions/Comments1

External Clock

@ 50 Hz, 60 Hz 120 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz.
82 dB min

@ 50 Hz 120 dB min 50 Hz output data rate, 50 ± 1 Hz.
@ 60 Hz 120 dB min 60 Hz output data rate, 60 ± 1 Hz.

Sinc

3

Filter

Internal Clock

@ 50 Hz, 60 Hz 75 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz.
60 dB min

@ 50 Hz 72 dB min 50 Hz output data rate, 50 ± 1 Hz.
@ 60 Hz 72 dB min 60 Hz output data rate, 60 ± 1 Hz.

External Clock

@ 50 Hz, 60 Hz 100 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz.
67 dB min

@ 50 Hz 100 dB min 50 Hz output data rate, 50 ± 1 Hz.
@ 60 Hz 100 dB min 60 Hz output data rate, 60 ± 1 Hz.

ANALOG INPUTS

Differential Input Voltage Ranges ±V

/gain V nom

REF

±(AVDD – 1.25 V)/gain V min/max gain > 1.
Absolute AIN Voltage Limits

2

Unbuffered Mode GND − 50 mV V min
AVDD + 50 mV V max

Buffered Mode GND + 250 mV V min
AVDD − 250 mV V max
Analog Input Current

Buffered Mode

Input Current

2

±2 nA max Gain = 1.

±3 nA max Gain > 1.
Input Current Drift ±5 pA/°C typ

Unbuffered Mode

Input Current ±5 μA/V typ

±1 μA/V typ Gain > 1.

Input Current Drift ±0.05 nA/V/°C typ External clock.

±1.6 nA/V/°C typ Internal clock.

REFERENCE INPUT

REFIN Voltage AVDD V nom REFIN = REFINx(+) − REFINx(−).

2

Reference Voltage Range

1 V min

AVDD V max

Absolute REFIN Voltage Limits

2

GND – 50 mV V min

AVDD + 50 mV V max
Average Reference Input Current 7 μA/V typ
Average Reference Input Current

±0.03 nA/V/°C typ External clock.

Drift

1.3 nA/V/°C typ Internal clock.

50 Hz output data rate, REJ60
50 ± 1 Hz, 60 ± 1 Hz.

50 Hz output data rate, REJ60
50 ± 1 Hz, 60 ± 1 Hz.

50 Hz output data rate, REJ60
50 ± 1 Hz, 60 ± 1 Hz.

= REFINx(+) − REFINx(−),

V

REF

gain = 1 to 128.

Gain = 1, input current varies with input
voltage.

The differential input must be limited to
± (AVDD – 1.25 V)/gain when gain > 1.

5

= 1,

5

= 1,

5

= 1,

Rev. 0 | Page 4 of 40

AD7190

www.BDTIC.com/ADI

Parameter AD7190B Unit Test Conditions/Comments1

Normal Mode Rejection
Common-Mode Rejection 100 dB typ
Reference Detect Levels 0.3 V min

0.6 V max

TEMPERATURE SENSOR

Accuracy ±2 °C typ

Sensitivity 2815 Codes/°C typ Bipolar mode.

BRIDGE POWER-DOWN SWITCH

RON 10 Ω max
Allowable Current

BURNOUT CURRENTS

AIN Current 500 nA nom

DIGITAL OUTPUTS (P0 to P3)

Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current ±100 nA max
Floating-State Output

Capacitance

INTERNAL/EXTERNAL CLOCK

Internal Clock

Frequency 4.92 ± 4% MHz min/max
Duty Cycle 50:50 % typ

External Clock/Crystal2

Frequency 4.9152 MHz nom

2.4576/5.12 MHz min/max
Input Low Voltage, VINL 0.8 V max DVDD = 5 V.

0.4 V max DVDD = 3 V.
Input High Voltage, VINH 2.5 V min DVDD = 3 V.

3.5 V min DVDD = 5 V.
Input Current ±10 μA max

LOGIC INPUTS

Input High Voltage, VINH2 2 V min
Input Low Voltage, VINL2 0.8 V max
Hysteresis2 0.1/0.25 V min/V max
Input Currents ±10 μA max

LOGIC OUTPUT (DOUT/RDY)

Output High Voltage, VOH
Output Low Voltage, VOL
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current ±10 μA max
Floating-State Output

Capacitance

Data Output Coding Offset binary

SYSTEM CALIBRATION

Full-Scale Calibration Limit 1.05 × FS V max
Zero-Scale Calibration Limit −1.05 × FS V min
Input Span 0.8 × FS V min

2.1 × FS V max

2

Same as for analog inputs

Applies after user calibration at one
temperature.

2

30 mA max Continuous current.

Analog inputs must be buffered and chop
disabled.

2

2

0.4 V max AV

4 V min AVDD = 5V, I

= 5V, I

DD

SOURCE

= 800 μA.

SINK

= 200 μA.

10 pF typ

2

DV

2

0.4 V max DV

2

4 V min DV

2

0.4 V max DV

− 0.6 V min DVDD = 3 V, I

DD

= 3 V, I

DD

= 5 V, I

DD

= 5 V, I

DD

SOURCE

= 100 μA.

SINK

SOURCE

= 1.6 mA.

SINK

10 pF typ

2

= 100 μA.

= 200 μA.

Rev. 0 | Page 5 of 40

AD7190

www.BDTIC.com/ADI

Parameter AD7190B Unit Test Conditions/Comments1

POWER REQUIREMENTS

Power Supply Voltage

AVDD − AGND 4.75/5.25 V min/max
DVDD − DGND 2.7/5.25 V min/max

Power Supply Currents

AIDD Current 1 mA max 0.85 mA typical, gain = 1, buffer off.

1.3 mA max 1.1 mA typical, gain = 1, buffer on.

4.5 mA max 3.5 mA typical, gain = 8, buffer off.

4.75 mA max 4 mA typical, gain = 8, buffer on.

6.2 mA max 5 mA typical, gain = 16 to 128, buffer off.

6.75 mA max 5.5 mA typical, gain = 16 to 128, buffer on.
DIDD Current 0.4 mA max 0.35 mA typical, DVDD = 3 V.

0.6 mA max 0.5 mA typical, DVDD = 5 V.

1.5 mA typ External crystal used.
IDD (Power-Down Mode) 2 μA max

1

Temperature range: −40°C to +105°C.

2

Specification is not production tested but is supported by characterization data at initial product release.

3

Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full-

scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.

4

Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (AVDD = 5 V, gain = 1, TA = 25°C).

5

REJ60 is a bit in the mode register. When the output data rate is set to 50 Hz, setting REJ60 to 1 places a notch at 60 Hz, allowing simultaneous 50 Hz/60 Hz rejection.

6

Digital inputs equal to DV

6

or GND.

DD

Rev. 0 | Page 6 of 40

AD7190

www.BDTIC.com/ADI

TIMING CHARACTERISTICS

AVDD = 4.75 V to 5.25 V; DVDD = 2.7 V to 5.25 V; GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.

Table 2.

Parameter Limit at T

t

3

100 ns min SCLK high pulse width

MIN

, T

(B Version) Unit Conditions/Comments

MAX

1, 2

t4 100 ns min SCLK low pulse width
READ OPERATION

t1 0 ns min

falling edge to DOUT/RDY active time

CS
60 ns max DVDD = 4.75 V to 5.25 V
80 ns max DVDD = 2.7 V to 3.6 V

3

t

2

0 ns min SCLK active edge to data valid delay

4

60 ns max DVDD = 4.75 V to 5.25 V
80 ns max DVDD = 2.7 V to 3.6 V

5, 6

t

5

10 ns min

Bus relinquish time after CS

inactive edge
80 ns max
t6 0 ns min
t7 10 ns min

SCLK inactive edge to CS
SCLK inactive edge to DOUT/RDY

inactive edge

high

WRITE OPERATION

t8 0 ns min

falling edge to SCLK active edge setup time

CS

4

t9 30 ns min Data valid to SCLK edge setup time
t10 25 ns min Data valid to SCLK edge hold time
t11 0 ns min

1

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.

2

See Figure 3 and Figure 4.

3

These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.

4

The SCLK active edge is the falling edge of SCLK.

5

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number

is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.

6

RDY

returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while
is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the
digital word can be read only once.

rising edge to SCLK edge hold time

CS

RDY

CIRCUIT AND TIMING DIAGRAMS

I

(1.6mA WITH DVDD = 5V,

SINK

TO

OUTPUT

PIN

50pF

100µA WIT H DV

I

SOURCE

100µA WIT H DV

= 3V)

DD

1.6V

(200µA WIT H DVDD = 5V,

= 3V)

DD

Figure 2. Load Circuit for Timing Characterization

Rev. 0 | Page 7 of 40

7640-002

AD7190

S

www.BDTIC.com/ADI

CS (I)

DOUT/RDY (O )

SCLK (I)

CS (I)

t

1

MSB LSB

t

2

t

3

t

I = INPUT, O = OUTPUT

4

Figure 3. Read Cycle Timing Diagram

t

6

t

5

t

7

7640-003

t

11

7640-004

CLK (I)

DIN (I)

I = INPUT, O = OUTPUT

t

8

t

9

t

10

MSB LSB

Figure 4. Write Cycle Timing Diagram

Rev. 0 | Page 8 of 40

AD7190

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND

DVDD to GND

Analog Input Voltage to GND

Reference Input Voltage to GND

Digital Input Voltage to GND

Digital Output Voltage to GND

AIN/Digital Input Current 10 mA
Operating Temperature Range

Storage Temperature Range

Maximum Junction Temperature 150°C
Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

−0.3 V to +6.5 V

−0.3 V to +6.5 V

−0.3 V to AVDD + 0.3 V

−0.3 V to AVDD + 0.3 V

−0.3 V to DVDD + 0.3 V

−0.3 V to DVDD + 0.3 V

−40°C to +105°C

−65°C to +150°C

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θJA θ

24-Lead TSSOP 97.9 14 °C/W

Unit

JC

ESD CAUTION

Rev. 0 | Page 9 of 40

AD7190

www.BDTIC.com/ADI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

MCLK1

MCLK2

SCLK

CS

P1/REFIN2(+)

P0/REFIN2(–)

NC

AINCOM

AIN1

AIN2

1

2

3

4

AD7190

TOP VIEW

5

P3

(Not to Scale)

6

P2

7

8

9

10

11

12

NC = NO CONNECT

24

DIN

23

DOUT/RDY

22

SYNC

21

DV

20

AV

19

DGND

18

AGND

17

BPDSW

16

REFIN1(–)

15

REFIN1(+)

14

AIN4

13

AIN3

DD

DD

07640-005

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 MCLK1

When the master clock for the device is provided externally by a crystal, the crystal is connected between
MCLK1 and MCLK2.

2 MCLK2

Master Clock Signal for the Device. The AD7190 has an internal 4.92 MHz clock. This internal clock can be
made available on the MCLK2 pin. The clock for the AD7190 can be provided externally also in the form of
a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the
MCLK2 pin can be driven with a CMOS-compatible clock and the MCLK1 pin left unconnected.

3 SCLK

Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt­triggered input, making the interface suitable for opto-isolated applications. The serial clock can be
continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncon­tinuous clock with the information transmitted to or from the ADC in smaller batches of data.

4

Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC

CS

in systems with more than one device on the serial bus or as a frame synchronization signal in
communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode

with SCLK, DIN, and DOUT used to interface with the device.
5 P3 Digital Output Pin. This pin can function as a general-purpose output bit referenced between AVDD and AGND.
6 P2 Digital Output Pin. This pin can function as a general-purpose output bit referenced between AVDD and AGND.
7 P1/REFIN2(+)

Digital Output Pin/Positive Reference Input. This pin functions as a general-purpose output bit referenced

between AVDD and AGND. When REFSEL = 1, this pin functions as REFIN2(+). An external reference can be

applied between REFIN2(+) and REFIN2(−). REFIN2(+) can lie anywhere between AV

nominal reference voltage, (REFIN2(+) − REFIN2(−)), is AV

1 V to AV
8 P0/REFIN2(−)

Digital Output Pin/Negative Reference Input. This pin functions as a general-purpose output bit referenced

between AV

anywhere between GND and AV

, but the part functions with a reference from

.

DD

and AGND. When REFSEL = 1, this pin functions as REFIN2(−). This reference input can lie

DD

− 1 V.

DD

DD

and GND + 1 V. The

DD

9 NC No Connect. This pin should be tied to AGND.
10 AINCOM

Analog Input AIN1 to Analog Input AIN4 are referenced to this input when configured for pseudo

differential operation.
11 AIN1

Analog Input. It can be configured as the positive input of a fully differential input pair when used with

AIN2 or as a pseudo differential input when used with AINCOM.
12 AIN2

Analog Input. It can be configured as the negative input of a fully differential input pair when used with

AIN1 or as a pseudo differential input when used with AINCOM.

Rev. 0 | Page 10 of 40

AD7190

www.BDTIC.com/ADI

Pin No. Mnemonic Description

13 AIN3

14 AIN4

15 REFIN1(+)

16 REFIN1(−) Negative Reference Input. This reference input can lie anywhere between GND and AVDD − 1 V.
17 BPDSW Bridge Power-Down Switch to AGND.
18 AGND Analog Ground Reference Point.
19 DGND Digital Ground Reference Point.
20 AVDD Analog Supply Voltage, 4.75 V to 5.25 V. AVDD is independent of DVDD.
21 DVDD Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD.
22

23

24 DIN

SYNC

DOUT/RDY

Serial Data Output/Data Ready Output. DOUT/RDYserves a dual purpose. It functions as a serial data

Analog Input. It can be configured as the positive input of a fully differential input pair when used with
AIN4 or as a pseudo differential input when used with AINCOM.

Analog Input. It can be configured as the negative input of a fully differential input pair when used with
AIN3 or as a pseudo differential input when used with AINCOM.

Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−).
REFIN1(+) can lie anywhere between AV
REFIN1(−)), is AV

Logic input that allows for synchronization of the digital filters and analog modulators when using
multiple AD7190 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the
calibration control logic are reset, and the analog modulator is held in its reset state. SYNC
the digital interface but does reset RDY
DVDD.

output pin to access the output shift register of the ADC. The output shift register can contain data from
any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low
to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high
before the next update occurs. The DOUT/RDY
indicating that valid data is available. With an external serial clock, the data can be read using the
DOUT/RDY
SCLK falling edge and is valid on the SCLK rising edge.

Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the
control registers in the ADC, with the register selection bits of the communications register identifying the
appropriate register.

, but the part functions with a reference from 1 V to AVDD.

DD

pin. With CS low, the data/control word information is placed on the DOUT/RDY pin on the

and GND + 1 V. The nominal reference voltage, (REFIN1(+) −

DD

does not affect

to a high state if it is low. SYNC has a pull-up resistor internally to

falling edge can be used as an interrupt to a processor,

Rev. 0 | Page 11 of 40

AD7190

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

8,388,760

8,388,758

8,388,756

8,388,754

CODE

8,388,752

8,388,750

8,388,748

8,388,746

0 200 400 600 800 1000

Figure 6. Noise (V

= 5 V, Output Data Rate = 4.7 Hz, Gain = 128, Chop

REF

Disabled, Sinc

SAMPLE

4

Filter)

07640-106

8,388,950

8,388,900

8,388,850

8,388,800

8,388,750

8,388,700

CODE

8,388,650

8,388,600

8,388,550

8,388,500

8,388,450

0 200 400 600 800 1000100 300 500 700 900

Figure 8. Noise (V

SAMPLES

= 5 V, Output Data Rate = 4800 Hz, Gain = 128, Chop

REF

Disabled, Sinc

4

Filter)

07640-108

250

200

150

100

FREQUENCY

50

0

388,746

388,748

388,750

388,752

388,754

388,756

388,758

8,

8,

8,

8,

8,

CODE

Figure 7. Noise Distribution Histogram (V

8,

= 5 V,

REF

388,760

8,

8,

Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc4 Filter)

30

25

20

15

FREQUENCY

10

5

0

7

07640-10

8,388,490

8,388,576

8,388,662

8,388,748

CODE

Figure 9. Noise Distribution Histogram (V

REF

8,388,834

= 5 V,

8,388,920

07640-109

Output Data Rate = 4800 Hz, Gain = 128, Chop Disabled, Sinc4 Filter)

Rev. 0 | Page 12 of

40