ANALOG DEVICES AD7190 Service Manual

4.8 kHz Ultralow Noise 24-Bit

www.BDTIC.com/ADI

FEATURES

RMS noise: 8.5 nV @ 4.7 Hz (gain = 128) 16 noise free bits @ 2.4 kHz (gain = 128) Up to 22.5 noise free bits (gain = 1) Offset drift: 5 nV/°C Gain drift: 1 ppm/°C Specified drift over time 2 differential/4 pseudo differential input channels Automatic channel sequencer Programmable gain (1 to 128) Output data rate: 4.7 Hz to 4.8 kHz Internal or external clock Simultaneous 50 Hz/60 Hz rejection 4 general-purpose digital outputs Power supply

: 4.75 V to 5.25 V

: 2.7 V to 5.25 V

Current: 6 mA Temperature range: –40°C to +105°C Interface

3-wire serial SPI, QSPI™, MICROWIRE™, and DSP compatible Schmitt trigger on SCLK

APPLICATIONS

Weigh scales Strain gauge transducers Pressure measurement Temperature measurement

Sigma-Delta ADC with PGA

AD7190

Chromatography PLC/DCS analog input modules Data acquisition Medical and scientific instrumentation

GENERAL DESCRIPTION

The AD7190 is a low noise, complete analog front end for high precision measurement applications. It contains a low noise, 24-bit sigma-delta (∑-∆) analog to digital converter (ADC). The on-chip low noise gain stage means that signals of small amplitude can be interfaced directly to the ADC.

The device can be configured to have two differential inputs or four pseudo differential inputs. The on-chip channel sequencer allows several channels to be enabled, and the AD7190 sequentially converts on each enabled channel. This simplifies communication with the part. The on-chip 4.92 MHz clock can be used as the clock source to the ADC or, alternatively, an external clock or crystal can be used. The output data rate from the part can be varied from 4.7 Hz to 4.8 kHz.

The device has two digital filter options. The choice of filter affects the rms noise/noise-free resolution at the programmed output data rate, the settling time, and the 50 Hz/60 Hz rejection. For applications that require all conversions to be settled, the AD7190 includes a zero latency feature.

The part operates with 5 V analog power supply and a digital power supply from 2.7 V to 5.25 V. It consumes a current of 6 mA. It is housed in a 24-lead TSSOP package.

FUNCTIONAL BLOCK DIAGRAM

AIN1 AIN2 AIN3 AIN4

INCOM

BPDSW

AGND

MUX

AGND

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of p atents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

DGND REFIN1 (+) REF IN1(–)

AD7190

CLOCK

Figure 1.

Σ-Δ

ADC

PGA

TEMP

SENSOR

CIRCUITRY

MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+)

REFERENCE

DETECT

SERIAL

INTERFACE

AND

CONTROL

LOGIC

DOUT/RDY

DIN

SCLK

SYNC

07640-001

AD7190

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Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ................................................................ 7

Circuit and Timing Diagrams ..................................................... 7

Absolute Maximum Ratings ............................................................ 9

Thermal Resistance ...................................................................... 9

ESD Caution .................................................................................. 9

Pin Configuration and Function Descriptions ........................... 10

Typical Performance Characteristics ........................................... 12

RMS Noise and Resolution ............................................................ 15

Sinc4 Chop Disabled ................................................................... 15

Sinc3 Chop Disabled ................................................................... 16

Sinc4 Chop Enabled .................................................................... 17

Sinc3 Chop Enabled .................................................................... 18

On-Chip Registers .......................................................................... 19

Communications Register ......................................................... 19

Status Register ............................................................................. 20

Mode Register ............................................................................. 20

Configuration Register .............................................................. 22

Data Register ............................................................................... 24

GPOCON Register ..................................................................... 24

Offset Register ............................................................................. 25

Full-Scale Register ...................................................................... 25

ADC Circuit Information .............................................................. 26

Overview ..................................................................................... 26

Filter, Output Data Rate, Settling Time ................................... 26

Digital Interface .......................................................................... 29

Circuit Description......................................................................... 33

Analog Input Channel ............................................................... 33

PGA .............................................................................................. 33

Bipolar/Unipolar Configuration .............................................. 33

Data Output Coding .................................................................. 33

Clock ............................................................................................ 33

Burnout Currents ....................................................................... 34

Reference ..................................................................................... 34

Reference Detect ......................................................................... 34

Reset ............................................................................................. 34

System Synchronization ............................................................ 35

Temperature Sensor ................................................................... 35

Bridge Power-Down Switch ...................................................... 35

Logic Outputs ............................................................................. 35

Enable Parity ............................................................................... 35

Calibration ................................................................................... 36

Grounding and Layout .............................................................. 36

Applications Information .............................................................. 38

Weigh Scales ................................................................................ 38

Outline Dimensions ....................................................................... 39

Ordering Guide .......................................................................... 39

REVISION HISTORY

10/08—Revision 0—Initial Version

Rev. 0 | Page 2 of 40

AD7190

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SPECIFICATIONS

AVDD = 4.75 V to 5.25 V; DVDD = 2.7 V to 5.25 V; GND = 0 V; REFIN1(+) = AVDD ; REFIN1(−) = GND; MCLK = 4.92 MHz; all specifications T

Table 1.

Parameter AD7190B Unit Test Conditions/Comments1

ADC

Output Data Rate 4.7 to 4800 Hz nom Chop disabled.

1.17 to 1200 Hz nom Chop enabled. No Missing Codes 24 Bits min FS > 4, sinc3 filter. Resolution

RMS Noise and Output Data Rates

Integral Nonlinearity ±5 ppm of FSR max ±1 ppm typical, gain = 1. ±15 ppm of FSR max ±5 ppm typical, gain > 1. Offset Error ±0.5 μV typ Chop enabled. Offset Error Drift vs. Temperature ±100/gain nV/°C typ Gain = 1 to 16. chop disabled. ±5 nV/°C typ Gain = 32 to 128. chop disabled. ±5 nV/°C typ Chop enabled. Offset Error Drift vs. Time 25 nV/1000 hours typ Gain ≥ 32 Gain Error ±0.0075 % typ Gain > 1, post internal-calibration. Gain Drift vs. Temperature ±1 ppm/°C typ Gain Drift vs. Time 10 ppm/1000 hours typ Gain = 1. Power Supply Rejection 95 dB typ Gain = 1, VIN = 1 V. 95 dB min Gain > 1, VIN = 1 V/gain. 110 dB typical. Common-Mode Rejection

@ DC 100 dB min Gain = 1, VIN = 1 V2 110 dB min Gain > 1, VIN = 1 V/gain. @ 50 Hz, 60 Hz2 120 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. @ 50 Hz, 60 Hz2 120 dB min

Normal Mode Rejection

Sinc4 Filter Internal Clock

@ 50 Hz, 60 Hz 100 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 74 dB min

@ 50 Hz 96 dB min 50 Hz output data rate, 50 ± 1 Hz. @ 60 Hz 97 dB min 60 Hz output data rate, 60 ± 1 Hz.

to T

MIN

3, 4

±0.005 % max ±0.001 % typical, gain = 1, AV

, unless otherwise noted.

MAX

24 Bits min FS > 1, sinc4 filter.

See the RMS Noise and Resolution section

±75/gain μV typ Chop disabled.

50 ± 1 Hz (50 Hz output data rate), 60 ± 1 Hz (60 Hz output data rate).

50 Hz output data rate, REJ60 50 ± 1 Hz, 60 ± 1 Hz.

= 5 V.

= 1,

Rev. 0 | Page 3 of 40

AD7190

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Parameter AD7190B Unit Test Conditions/Comments1

External Clock

@ 50 Hz, 60 Hz 120 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 82 dB min

@ 50 Hz 120 dB min 50 Hz output data rate, 50 ± 1 Hz. @ 60 Hz 120 dB min 60 Hz output data rate, 60 ± 1 Hz.

Sinc

Filter

Internal Clock

@ 50 Hz, 60 Hz 75 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 60 dB min

@ 50 Hz 72 dB min 50 Hz output data rate, 50 ± 1 Hz. @ 60 Hz 72 dB min 60 Hz output data rate, 60 ± 1 Hz.

External Clock

@ 50 Hz, 60 Hz 100 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 67 dB min

@ 50 Hz 100 dB min 50 Hz output data rate, 50 ± 1 Hz. @ 60 Hz 100 dB min 60 Hz output data rate, 60 ± 1 Hz.

ANALOG INPUTS

Differential Input Voltage Ranges ±V

/gain V nom

REF

±(AVDD – 1.25 V)/gain V min/max gain > 1. Absolute AIN Voltage Limits

Unbuffered Mode GND − 50 mV V min AVDD + 50 mV V max

Buffered Mode GND + 250 mV V min AVDD − 250 mV V max Analog Input Current

Buffered Mode

Input Current

±2 nA max Gain = 1.

±3 nA max Gain > 1. Input Current Drift ±5 pA/°C typ

Unbuffered Mode

Input Current ±5 μA/V typ

±1 μA/V typ Gain > 1.

Input Current Drift ±0.05 nA/V/°C typ External clock.

±1.6 nA/V/°C typ Internal clock.

REFERENCE INPUT

REFIN Voltage AVDD V nom REFIN = REFINx(+) − REFINx(−).

Reference Voltage Range

1 V min

AVDD V max

Absolute REFIN Voltage Limits

GND – 50 mV V min

AVDD + 50 mV V max Average Reference Input Current 7 μA/V typ Average Reference Input Current

±0.03 nA/V/°C typ External clock.

Drift

1.3 nA/V/°C typ Internal clock.

50 Hz output data rate, REJ60 50 ± 1 Hz, 60 ± 1 Hz.

= REFINx(+) − REFINx(−),

REF

gain = 1 to 128.

Gain = 1, input current varies with input voltage.

The differential input must be limited to ± (AVDD – 1.25 V)/gain when gain > 1.

= 1,

Rev. 0 | Page 4 of 40

AD7190

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Parameter AD7190B Unit Test Conditions/Comments1

Normal Mode Rejection Common-Mode Rejection 100 dB typ Reference Detect Levels 0.3 V min

0.6 V max

TEMPERATURE SENSOR

Accuracy ±2 °C typ

Sensitivity 2815 Codes/°C typ Bipolar mode.

BRIDGE POWER-DOWN SWITCH

RON 10 Ω max Allowable Current

BURNOUT CURRENTS

AIN Current 500 nA nom

DIGITAL OUTPUTS (P0 to P3)

Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current ±100 nA max Floating-State Output

Capacitance

INTERNAL/EXTERNAL CLOCK

Internal Clock

Frequency 4.92 ± 4% MHz min/max Duty Cycle 50:50 % typ

External Clock/Crystal2

Frequency 4.9152 MHz nom

2.4576/5.12 MHz min/max Input Low Voltage, VINL 0.8 V max DVDD = 5 V.

0.4 V max DVDD = 3 V. Input High Voltage, VINH 2.5 V min DVDD = 3 V.

3.5 V min DVDD = 5 V. Input Current ±10 μA max

LOGIC INPUTS

Input High Voltage, VINH2 2 V min Input Low Voltage, VINL2 0.8 V max Hysteresis2 0.1/0.25 V min/V max Input Currents ±10 μA max

LOGIC OUTPUT (DOUT/RDY)

Output High Voltage, VOH Output Low Voltage, VOL Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current ±10 μA max Floating-State Output

Capacitance

Data Output Coding Offset binary

SYSTEM CALIBRATION

Full-Scale Calibration Limit 1.05 × FS V max Zero-Scale Calibration Limit −1.05 × FS V min Input Span 0.8 × FS V min

2.1 × FS V max

Same as for analog inputs

Applies after user calibration at one temperature.

30 mA max Continuous current.

Analog inputs must be buffered and chop disabled.

0.4 V max AV

4 V min AVDD = 5V, I

= 5V, I

SOURCE

= 800 μA.

SINK

= 200 μA.

10 pF typ

0.4 V max DV

4 V min DV

0.4 V max DV

− 0.6 V min DVDD = 3 V, I

= 3 V, I

= 5 V, I

SOURCE

= 100 μA.

SINK

SOURCE

= 1.6 mA.

SINK

10 pF typ

= 100 μA.

= 200 μA.

Rev. 0 | Page 5 of 40

AD7190

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Parameter AD7190B Unit Test Conditions/Comments1

POWER REQUIREMENTS

Power Supply Voltage

AVDD − AGND 4.75/5.25 V min/max DVDD − DGND 2.7/5.25 V min/max

Power Supply Currents

AIDD Current 1 mA max 0.85 mA typical, gain = 1, buffer off.

1.3 mA max 1.1 mA typical, gain = 1, buffer on.

4.5 mA max 3.5 mA typical, gain = 8, buffer off.

4.75 mA max 4 mA typical, gain = 8, buffer on.

6.2 mA max 5 mA typical, gain = 16 to 128, buffer off.

6.75 mA max 5.5 mA typical, gain = 16 to 128, buffer on. DIDD Current 0.4 mA max 0.35 mA typical, DVDD = 3 V.

0.6 mA max 0.5 mA typical, DVDD = 5 V.

1.5 mA typ External crystal used. IDD (Power-Down Mode) 2 μA max

Temperature range: −40°C to +105°C.

Specification is not production tested but is supported by characterization data at initial product release.

Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full-

scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.

Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (AVDD = 5 V, gain = 1, TA = 25°C).

REJ60 is a bit in the mode register. When the output data rate is set to 50 Hz, setting REJ60 to 1 places a notch at 60 Hz, allowing simultaneous 50 Hz/60 Hz rejection.

Digital inputs equal to DV

or GND.

Rev. 0 | Page 6 of 40

AD7190

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TIMING CHARACTERISTICS

AVDD = 4.75 V to 5.25 V; DVDD = 2.7 V to 5.25 V; GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.

Table 2.

Parameter Limit at T

100 ns min SCLK high pulse width

MIN

, T

(B Version) Unit Conditions/Comments

MAX

1, 2

t4 100 ns min SCLK low pulse width READ OPERATION

t1 0 ns min

falling edge to DOUT/RDY active time

CS 60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V

0 ns min SCLK active edge to data valid delay

60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V

5, 6

10 ns min

Bus relinquish time after CS

inactive edge 80 ns max t6 0 ns min t7 10 ns min

SCLK inactive edge to CS SCLK inactive edge to DOUT/RDY

inactive edge

high

WRITE OPERATION

t8 0 ns min

falling edge to SCLK active edge setup time

t9 30 ns min Data valid to SCLK edge setup time t10 25 ns min Data valid to SCLK edge hold time t11 0 ns min

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.

See Figure 3 and Figure 4.

These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.

The SCLK active edge is the falling edge of SCLK.

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number

is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.

RDY

returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once.

rising edge to SCLK edge hold time

RDY

CIRCUIT AND TIMING DIAGRAMS

(1.6mA WITH DVDD = 5V,

SINK

OUTPUT

50pF

100µA WIT H DV

SOURCE

100µA WIT H DV

= 3V)

1.6V

(200µA WIT H DVDD = 5V,

= 3V)

Figure 2. Load Circuit for Timing Characterization

Rev. 0 | Page 7 of 40

7640-002

AD7190

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CS (I)

DOUT/RDY (O )

SCLK (I)

CS (I)

MSB LSB

I = INPUT, O = OUTPUT

Figure 3. Read Cycle Timing Diagram

7640-003

7640-004

CLK (I)

DIN (I)

I = INPUT, O = OUTPUT

MSB LSB

Figure 4. Write Cycle Timing Diagram

Rev. 0 | Page 8 of 40

AD7190

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND

DVDD to GND

Analog Input Voltage to GND

Reference Input Voltage to GND

Digital Input Voltage to GND

Digital Output Voltage to GND

AIN/Digital Input Current 10 mA Operating Temperature Range

Storage Temperature Range

Maximum Junction Temperature 150°C Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

−0.3 V to +6.5 V

−0.3 V to AVDD + 0.3 V

−0.3 V to DVDD + 0.3 V

−40°C to +105°C

−65°C to +150°C

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θJA θ

24-Lead TSSOP 97.9 14 °C/W

Unit

ESD CAUTION

Rev. 0 | Page 9 of 40

AD7190

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

MCLK1

MCLK2

SCLK

P1/REFIN2(+)

P0/REFIN2(–)

AINCOM

AIN1

AIN2

AD7190

TOP VIEW

(Not to Scale)

NC = NO CONNECT

DIN

DOUT/RDY

SYNC

DGND

AGND

BPDSW

REFIN1(–)

REFIN1(+)

AIN4

AIN3

07640-005

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 MCLK1

When the master clock for the device is provided externally by a crystal, the crystal is connected between MCLK1 and MCLK2.

2 MCLK2

Master Clock Signal for the Device. The AD7190 has an internal 4.92 MHz clock. This internal clock can be made available on the MCLK2 pin. The clock for the AD7190 can be provided externally also in the form of a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin can be driven with a CMOS-compatible clock and the MCLK1 pin left unconnected.

3 SCLK

Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitttriggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information transmitted to or from the ADC in smaller batches of data.

Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC

in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode

with SCLK, DIN, and DOUT used to interface with the device. 5 P3 Digital Output Pin. This pin can function as a general-purpose output bit referenced between AVDD and AGND. 6 P2 Digital Output Pin. This pin can function as a general-purpose output bit referenced between AVDD and AGND. 7 P1/REFIN2(+)

Digital Output Pin/Positive Reference Input. This pin functions as a general-purpose output bit referenced

between AVDD and AGND. When REFSEL = 1, this pin functions as REFIN2(+). An external reference can be

applied between REFIN2(+) and REFIN2(−). REFIN2(+) can lie anywhere between AV

nominal reference voltage, (REFIN2(+) − REFIN2(−)), is AV

1 V to AV 8 P0/REFIN2(−)

Digital Output Pin/Negative Reference Input. This pin functions as a general-purpose output bit referenced

between AV

anywhere between GND and AV

, but the part functions with a reference from

and AGND. When REFSEL = 1, this pin functions as REFIN2(−). This reference input can lie

− 1 V.

and GND + 1 V. The

9 NC No Connect. This pin should be tied to AGND. 10 AINCOM

Analog Input AIN1 to Analog Input AIN4 are referenced to this input when configured for pseudo

differential operation. 11 AIN1

Analog Input. It can be configured as the positive input of a fully differential input pair when used with

AIN2 or as a pseudo differential input when used with AINCOM. 12 AIN2

Analog Input. It can be configured as the negative input of a fully differential input pair when used with

AIN1 or as a pseudo differential input when used with AINCOM.

Rev. 0 | Page 10 of 40

AD7190

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Pin No. Mnemonic Description

13 AIN3

14 AIN4

15 REFIN1(+)

16 REFIN1(−) Negative Reference Input. This reference input can lie anywhere between GND and AVDD − 1 V. 17 BPDSW Bridge Power-Down Switch to AGND. 18 AGND Analog Ground Reference Point. 19 DGND Digital Ground Reference Point. 20 AVDD Analog Supply Voltage, 4.75 V to 5.25 V. AVDD is independent of DVDD. 21 DVDD Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. 22

24 DIN

SYNC

DOUT/RDY

Serial Data Output/Data Ready Output. DOUT/RDYserves a dual purpose. It functions as a serial data

Analog Input. It can be configured as the positive input of a fully differential input pair when used with AIN4 or as a pseudo differential input when used with AINCOM.

Analog Input. It can be configured as the negative input of a fully differential input pair when used with AIN3 or as a pseudo differential input when used with AINCOM.

Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−). REFIN1(+) can lie anywhere between AV REFIN1(−)), is AV

Logic input that allows for synchronization of the digital filters and analog modulators when using multiple AD7190 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the calibration control logic are reset, and the analog modulator is held in its reset state. SYNC the digital interface but does reset RDY DVDD.

output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY SCLK falling edge and is valid on the SCLK rising edge.

Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers in the ADC, with the register selection bits of the communications register identifying the appropriate register.

, but the part functions with a reference from 1 V to AVDD.

pin. With CS low, the data/control word information is placed on the DOUT/RDY pin on the

and GND + 1 V. The nominal reference voltage, (REFIN1(+) −

does not affect

to a high state if it is low. SYNC has a pull-up resistor internally to

falling edge can be used as an interrupt to a processor,

Rev. 0 | Page 11 of 40

AD7190

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TYPICAL PERFORMANCE CHARACTERISTICS

8,388,760

8,388,758

8,388,756

8,388,754

CODE

8,388,752

8,388,750

8,388,748

8,388,746

0 200 400 600 800 1000

Figure 6. Noise (V

= 5 V, Output Data Rate = 4.7 Hz, Gain = 128, Chop

REF

Disabled, Sinc

SAMPLE

Filter)

07640-106

8,388,950

8,388,900

8,388,850

8,388,800

8,388,750

8,388,700

CODE

8,388,650

8,388,600

8,388,550

8,388,500

8,388,450

0 200 400 600 800 1000100 300 500 700 900

Figure 8. Noise (V

SAMPLES

= 5 V, Output Data Rate = 4800 Hz, Gain = 128, Chop

REF

Disabled, Sinc

Filter)

07640-108

250

200

150

100

FREQUENCY

388,746

388,748

388,750

388,752

388,754

388,756

388,758

CODE

Figure 7. Noise Distribution Histogram (V

= 5 V,

REF

388,760

Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc4 Filter)

FREQUENCY

07640-10

8,388,490

8,388,576

8,388,662

8,388,748

CODE

Figure 9. Noise Distribution Histogram (V

REF

8,388,834

= 5 V,

8,388,920

07640-109

Output Data Rate = 4800 Hz, Gain = 128, Chop Disabled, Sinc4 Filter)

Rev. 0 | Page 12 of

AD7190

www.BDTIC.com/ADI

8,388,820

8,388,800

8,388,780

8,388,760

8,388,740

8,388,720

CODE

8,388,700

8,388,680

8,388,660

8,388,640

8,388,620

0 200 400 600 800 1000100 300 500 700 900

SAMPLES

07640-110

3.0

2.0

1.0

INL (ppm of FSR)

–1.0

–2.0

–3.0

–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5

VIN (V)

07640-112

Figure 10. Noise (V

FREQUENCY

8,388,620

Figure 11. Noise Distribution Histogram (V

= 5 V, Output Data Rate = 4800 Hz, Gain = 1, Chop

REF

Disabled, Sinc

8,388,660

8,388,700

CODE

Filter)

8,388,740

REF

Output Data Rate = 4800 Hz, Gain = 1, Chop Disabled, Sinc

8,388,780

= 5 V,

Filter)

Figure 12. INL (Gain = 1)

INL (ppm of FSR)

–2

–4

–6

–0.020 –0.015 –0.010 –0.005 0 0.005 0.010 0.015 0.020

8,388,820

7640-111

VIN (V)

07640-113

Figure 13. INL (Gain = 128)

Rev. 0 | Page 13 of

AD7190

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1.000008

OUTPUT VOLTAGE (µV)

–60 –40 –20 0 20 40 60 80 100 120 140

TEMPERATURE ( °C)

Figure 14. Offset Error (Gain = 1, Chop Disabled) Figure 16. Gain Error (Gain = 1, Chop Disabled)

–0.1

–0.2

–0.3

–0.4

OFFSET (µV)

–0.5

1.000007

1.000006

1.000005

1.000004

GAIN

1.000003

1.000002

1.000001

1.000000 –60 –40 –20 0 20 40 60 80 100 120

07640-114

128.003

128.002

128.001

128.000

GAIN

127.999

127.998

TEMPERATURE ( °C)

07640-116

–0.6

–0.7

–60 –40 –20 0 20 40 60 80 100 120

TEMERAT URE (° C)

07640-115

127.997

127.996 –60 –40 –20 0 20 40 60 80 100 120

TEMPERATURE ( °C)

07640-117

Figure 15. Offset Error (Gain = 128, Chop Disabled) Figure 17. Gain Error (Gain = 128, Chop Disabled)

Rev. 0 | Page 14

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RMS NOISE AND RESOLUTION

The AD7190 has a choice of two filter types: sinc4 and sinc3. In addition, the AD7190 can be operated with chop enabled or chop disabled.

The following tables show the rms noise of the AD7190 for some of the output data rates and gain settings with chop disabled and enabled for the sinc are for the bipolar input range with the external 5 V reference. These numbers are typical and are generated with a differential input voltage of 0 V when the ADC is continuously converting

and sinc3 filters. The numbers given

SINC4 CHOP DISABLED

Table 6. RMS Noise (nV) vs. Gain and Output Data Rate

Filter Word (Decimal)

1023 4.7 852.5 250 38 21 12 10 8.5 640 7.5 533 310 45 25 16 12 10.5 480 10 400 330 50 30 18 14 11.5 96 50 800 900 125 78 45 33 28 80 60 66.7 970 140 88 52 36 31 32 150 26.7 1460 215 125 75 55 48 16 300 13.3 1900 285 170 100 75 67 5 960 4.17 3000 480 280 175 140 121 2 2400 1.67 5000 780 440 280 220 198 1 4800 0.83 14,300 1920 1000 550 380 295

Output Data Rate (Hz)

Settling Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

on a single channel. The effective resolution is also shown, and the output peak-to-peak (p-p) resolution, or noise-free resolution, is listed in parentheses. It is important to note that the effective resolution is calculated using the rms noise, wheras the p-p resolution is calculated based on peak-to-peak noise. The pp resolution represents the resolution for which there is no code flicker. These numbers are typical and are rounded to the nearest ½ LSB.

Table 7. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate

Filter Word (Decimal)

1023 4.7 852.5 24 (22.5) 24 (22) 24 (22) 24 (22) 24 (21) 23 (20.5) 640 7.5 533 24 (22) 24 (22) 24 (22) 24 (21.5) 23.5 (21) 23 (20) 480 10 400 24 (22) 24 (22) 24 (21.5) 24 (21.5) 23.5 (20.5) 22.5 (20) 96 50 800 23.5 (20.5) 23.5 (20.5) 23 (20) 22.5 (20) 22 (19.5) 21.5 (18.5) 80 60 66.7 23.5 (20.5) 23 (20.5) 22.5 (20) 22.5 (20) 22 (19.5) 21.5 (18.5) 32 150 26.7 22.5 (20) 22.5 (19.5) 22.5 (19.5) 22 (19.5) 21.5 (18.5) 20.5 (18) 16 300 13.3 22.5 (19.5) 22 (19.5) 22 (19) 21.5 (19) 21 (18.5) 20 (17.5) 5 960 4.17 21.5 (19) 21.5 (18.5) 21 (18.5) 21 (18) 20 (17.5) 19.5 (16.5) 2 2400 1.67 21 (18) 20.5 (18) 20.5 (17.5) 20 (17.5) 19.5 (16.5) 18.5 (16) 1 4800 0.83 19.5 (16.5) 19.5 (16.5) 19.5 (16.5) 19 (16.5) 18.5 (16) 18 (15.5)

The output peak-to-peak (p-p) resolution is listed in parentheses.

Output Data Rate (Hz)

Settling Time (ms)

Gain of 1

Gain of 81 Gain of 161 Gain of 321 Gain of 641 Gain of 1281

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SINC3 CHOP DISABLED

Table 8. RMS Noise (nV) vs. Gain and Output Data Rate

Filter Word (Decimal)

1023 4.7 639.4 270 42 23 13.5 10.5 9 640 7.5 400 320 50 27 17 13 11.5 480 10 300 350 60 35 19 15 12.5 96 50 60 1000 134 86 50 35 29 80 60 50 1050 145 95 55 40 32 32 150 20 1500 225 130 80 58 50 16 300 10 1950 308 175 110 83 73 5 960 3.125 4000 590 330 200 150 133 2 2400 1.25 56,600 7000 3500 1800 900 490 1 4800 0.625 442,000 55,000 28,000 14,000 7000 3450

Table 9. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate

Filter Word (Decimal)

1023 4.7 639.4 24 (22.5) 24 (22) 24 (22) 24 (21.5) 24 (21) 23 (20.5) 640 7.5 400 24 (22) 24 (22) 24 (21.5) 24 (21.5) 23.5 (21) 22.5 (20) 480 10 300 24 (22) 24 (21.5) 24 (21.5) 24 (21) 23.5 (20.5) 22.5 (20) 96 50 60 23.5 (20.5) 23 (20.5) 23 (20) 22.5 (20) 22 (19.5) 21.5 (18.5) 80 60 50 23 (20.5) 23 (20.5) 22.5 (20) 22.5 (19.5) 22 (19) 21 (18.5) 32 150 20 22.5 (20) 22.5 (19.5) 22 (19.5) 22 (19) 21.5 (18.5) 20.5 (18) 16 300 10 22.5 (19.5) 22 (19) 22 (19) 21.5 (18.5) 21 (18) 20 (17.5) 5 960 3.125 21.5 (18.5) 21 (18.5) 21 (18) 20.5 (18) 20 (17.5) 19 (16.5) 2 2400 1.25 17.5 (14.5) 17.5 (14.5) 17.5 (14.5) 17.5 (14.5) 17.5 (14.5) 17.5 (14.5) 1 4800 0.625 14.5 (11.5) 14.5 (11.5) 14.5 (11.5) 14.5 (11.5) 14.5 (11.5) 14.5 (11.5)

The output peak-to-peak (p-p) resolution is listed in parentheses.

Output Data Rate (Hz)

Settling Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

Settling Time (ms) Gain of 1

Gain of 81 Gain of 161 Gain of 321 Gain of 641 Gain of 1281

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SINC4 CHOP ENABLED

Table 10. RMS Noise (nV) vs. Gain and Output Data Rate

Filter Word (Decimal)

1023 1.175 1702 177 27 15 8.5 7 6 640 1.875 1067 219 32 18 11.5 8.5 7.5 480 2.5 800 234 36 21 13 10 8.5 96 12.5 160 637 89 55 32 24 20 80 15 133 686 99 63 37 26 22 32 37.5 53 1033 152 89 53 39 34 16 75 26.7 1343 202 120 71 53 48 5 240 8.33 2121 340 198 124 99 86 2 600 3.33 3536 552 311 198 156 140 1 1200 1.67 10,200 1360 707 389 26 209

Table 11. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate

Filter Word (Decimal)

1023 1.175 1702 24 (23) 24 (22.5) 24 (22.5) 24 (22.5) 24 (21.5) 23.5 (21) 640 1.875 1067 24 (22.5) 24 (22.5) 24 (22.5) 24 (22) 24 (21.5) 23.5 (20.5) 480 2.5 800 24 (22.5) 24 (22.5) 24 (22) 24 (22) 24 (21) 23 (20.5) 96 12.5 160 24 (21) 24 (21) 23.5 (20.5) 23 (20.5) 22.5 (20) 22 (19) 80 15 133 24 (21) 23.5 (21) 23.5 (20.5) 23 (20.5) 22.5 (20) 22 (19) 32 37.5 53 23 (20.5) 23 (20) 23 (20) 22.5 (20) 22 (19) 21 (18.5) 16 75 26.7 23 (20) 22.5 (20) 22.5 (19.5) 22 (19.5) 21.5 (19) 20.5 (18) 5 240 8.33 22 (19.5) 22 (19) 21.5 (19) 21.5 (18.5) 20.5 (18) 20 (17) 2 600 3.33 21.5 (18.5) 21 (18.5) 21 (18) 20.5 (18) 20 (17) 19 (16.5) 1 1200 1.67 20 (17) 20 (17) 20 (17) 19.5 (17) 19 (16.5) 18.5 (16)

The output peak-to-peak (p-p) resolution is listed in parentheses.

Output Data Rate (Hz)

Settling Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

Settling Time (ms)

Gain of 1

Gain of 81 Gain of 161 Gain of 321 Gain of 641 Gain of 1281

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SINC3 CHOP ENABLED

Table 12. RMS Noise (nV) vs. Gain and Output Data Rate

Filter Word (Decimal)

1023 1.56 1282 191 30 16.5 10 8 6.5 640 2.5 800 226 36 19 12 9 8.5 480 3.33 600 248 43 25 14 11 9 96 16.6 120 708 95 61 36 25 21 80 20 100 743 103 68 39 29 23 32 50 40 1061 159 92 57 41 36 16 100 20 1380 218 124 78 59 52 5 320 6.25 2829 418 234 142 106 94 2 800 2.5 40,100 4950 2475 1273 637 347 1 1600 1.25 312,550 38,540 19,800 9900 4950 2440

Table 13. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate

Filter Word (Decimal)

1023 1.56 1282 24 (23) 24 (22.5) 24 (22.5) 24 (22) 24 (21.5) 23.5 (21) 640 2.5 800 24 (22.5) 24 (22.5) 24 (22) 24 (22) 24 (21.5) 23 (20.5) 480 3.33 600 24 (22.5) 24 (22) 24 (22) 24 (21.5) 24 (21) 23 (20.5) 96 16.6 120 24 (21) 23.5 (21) 23.5 (20.5) 23 (20.5) 22.5 (20) 22 (19) 80 20 100 23.5 (21) 23.5 (21) 23 (20.5) 23 (20) 22.5 (19.5) 21.5 (19) 32 50 40 23 (20.5) 23 (20) 22.5 (20) 22.5 (19.5) 22 (19) 21 (18.5) 16 100 20 23 (20) 22.5 (19.5) 22.5 (19.5) 22 (19) 21.5 (18.5) 20.5 (18) 5 320 6.25 22 (19) 21.5 (19) 21.5 (18.5) 21 (18.5) 20.5 (18) 19.5 (17) 2 800 2.5 18 (15) 18 (15) 18 (15) 18 (15) 18 (15) 18 (15) 1 1600 1.25 15 (12) 15 (12.5) 15 (12) 15 (12) 15 (12) 15 (12)

The output peak-to-peak (p-p) resolution is listed in parentheses.

Output Data Rate (Hz)

Settling Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

Settling Time (ms)

Gain of 1

Gain of 8

Gain of 16

Gain of 321Gain of 641Gain of 128

Rev. 0 | Page 18 of 40

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ON-CHIP REGISTERS

The ADC is controlled and configured via a number of on-chip registers, which are described in the following sections. In the descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise noted.

COMMUNICATIONS REGISTER

(RS2, RS1, RS0 = 0, 0, 0)

The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register. The data written to the communications register determines whether the next operation is a read or write operation and in which register this operation takes place. For read or write operations, when the subsequent read or write operation to the selected register is complete, the

CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0

WEN(0) R/W(0)

Table 14. Communications Register Bit Designations

Bit Location Bit Name Description

CR7

CR6

CR5 to CR3 RS2 to RS0

CR2 CREAD

CR1 to CR0 These bits must be programmed to Logic 0 for correct operation.

Write enable bit. A 0 must be written to this bit for a write to the communications register to occur. If a 1 is

WEN

A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position

R/W

RS2(0) RS1(0) RS0(0) CREAD(0) 0(0) 0(0)

the first bit written, the part does not clock on to subsequent bits in the register. It stays at this bit location until a 0 is written to this bit. After a 0 is written to the WEN communications register.

indicates that the next operation is a read from the designated register. Register address bits. These address bits are used to select which registers of the ADC are selected during

the serial interface communication. See Table 15. Continuous read of the data register. When this bit is set to 1 (and the data register is selected), the serial

interface is configured so that the data register can be continuously read; that is, the contents of the data register are automatically placed on the DOUT pin when the SCLK pulses are applied after the RDY goes low to indicate that a conversion is complete. The communications register does not have to be written to for subsequent data reads. To enable continuous read, the instruction 01011100 must be written to the communications register. To disable continuous read, the instruction 01011000 must be written to the communications register while the RDY activity on the DIN line so that it can receive the instruction to disable continuous read. Additionally, a reset occurs if 40 consecutive 1s are seen on DIN. Therefore, DIN should be held low until an instruction is to be written to the device.

interface returns to where it expects a write operation to the communications register. This is the default state of the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications register. In situations where the interface sequence is lost, a write operation of at least 40 serial clock cycles with DIN high returns the ADC to this default state by resetting the entire part. Tab le 1 4 outlines the bit designations for the communications register. CR0 through CR7 indicate the bit locations, CR denoting that the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit.

bit, the next seven bits are loaded to the

pin is low. While continuous read is enabled, the ADC monitors

Table 15. Register Selection

RS2 RS1 RS0 Register Register Size

0 0 0 Communications register during a write operation 8 bits 0 0 0 Status register during a read operation 8 bits 0 0 1 Mode register 24 bits 0 1 0 Configuration register 24 bits 0 1 1 Data register/data register plus status information 24 bits/32 bits 1 0 0 ID register 8 bits 1 0 1 GPOCON register 8 bits 1 1 0 Offset register 24 bits 1 1 1 Full-scale register 24 bits

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STATUS REGISTER

(RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80)

The status register is an 8-bit, read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Ta b le 16 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, SR denoting that the bits are in the status register. SR7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit.

SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

RDY(1)

Table 16. Status Register Bit Designations

Bit Location Bit Name Description

SR7

SR6 ERR

SR5 NOREF

SR4 Parity

SR3 to SR0

ERR(0) NOREF(0) Parity(0) CHD3(0) CHD2(0) CHD1(0) CHD0(0)

Ready bit for the ADC. Cleared when data is written to the ADC data register. The RDY bit is set

RDY

automatically after the ADC data register is read, or after a period of time before the data register is updated, with a new conversion result to indicate to the user that the conversion data should not be read.

CHD3 to CHD0

It is also set when the part is placed in power-down mode or idle mode or when SYNC The end of a conversion is also indicated by the DOUT/RDY pin. This pin can be used as an alternative to

the status register for monitoring the ADC for conversion data. ADC error bit. This bit is written to at the same time as the RDY

result written to the ADC data register is clamped to all 0s or all 1s. Error sources include overrange or underrange or the absence of a reference voltage. The bit is cleared by a write operation to start a conversion.

No external reference bit. This bit is set to indicate that the selected reference (REFIN1 or REFIN2) is at a voltage that is below a specified threshold. When set, conversion results are clamped to all 1s. This bit is cleared to indicate that a valid reference is applied to the selected reference pins. The NOREF bit is enabled by setting the REFDET bit in the configuration register to 1. The ERR bit is also set if the voltage applied to the selected reference input is invalid.

Parity check of the data register. If the ENPAR bit in the mode register is set, the parity bit is set if there is an odd number of 1s in the data register. It is cleared if there is an even number of 1s in the data register. The DAT_STA bit in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the contents of the status register are transmitted along with the data for each data register read.

These bits indicate which channel corresponds to the data register contents. They do not indicate which channel is presently being converted but indicate which channel was selected when the conversion contained in the data register was generated.

bit. The ERR bit is set to indicate that the

is taken low.

MODE REGISTER

(RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x080060)

The mode register is a 24-bit register from which data can be read or to which data can be written. This register is used to select the operating mode, the output data rate, and the clock source. Tab le 1 7 outlines the bit designations for the mode register. MR0 through MR23 indicate the bit locations, MR denoting that the bits are in the mode register. MR23 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. Any write to the mode register resets the modulator and filter and sets the

MR23 MR22 MR21 MR20 MR19 MR18 MR17 MR16 MD2(0) MD1(0) MD0(0) DAT_STA(0) CLK1(1) CLK0(0) 0 0 MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8

Sinc3(0) 0 ENPAR(0) 0 Single(0) REJ60(0) FS9(0) FS8(0)

MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0

FS7(0) FS6(1) FS5(1) FS4(0) FS3(0) FS2(0) FS1(0) FS0(0)

RDY

bit.

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Table 17. Mode Register Bit Designations

Bit Location Bit Name Description MR23 to MR21 MD2 to MD0 Mode select bits. These bits select the operating mode of the AD7190 (see Table 18). MR20 DAT_STA

MR19 to MR18 CLK1 to CLK0

MR17 to MR16 These bits must be programmed with a Logic 0 for correct operation. MR15 SINC3

MR14 This bit must be programmed with a Logic 0 for correct operation. MR13 ENPAR

MR12 This bit must be programmed with a Logic 0 for correct operation. MR11 Single

MR10 REJ60

MR9 to MR0 FS9 to FS0

This bit enables the transmission of status register contents after each data register read. When DAT_STA is set, the contents of the status register are transmitted along with each data register read. This function is useful when several channels are selected because the status register identifies the channel to which the data register value corresponds.

These bits are used to select the clock source for the AD7190. Either the on-chip 4.92 MHz clock or an external clock can be used. The ability to use an external clock allows several AD7190 devices to be synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7190.

CLK1 CLK0 ADC Clock Source

0 0 External crystal used. The external crystal is connected from MCLK1 to MCLK2. 0 1 External clock used. The external clock is applied to the MCLK2 pin. 1 0 Internal 4.92 MHz clock. Pin MCLK2 is tristated. 1 1 Internal 4.92 MHz clock. The internal clock is available on MCLK2.

filter select bit. When this bit is cleared, the sinc4 filter is used (default value). When this bit is set,

Sinc

the sinc when chop is disabled. For a given output data rate, f while the sinc 50 Hz/60 Hz rejection. At low output data rates, both filters give similar rms noise and similar no missing codes for a given output data rate. At higher output data rates (FS values less than 5), the sinc4 filter gives better performance than the sinc

Enable parity bit. When ENPAR is set, parity checking on the data register is enabled. The DAT_STA bit in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the contents of the status register are transmitted along with the data for each data register read.

Single cycle conversion enable bit. When this bit is set, the AD7190 settles in one conversion cycle so that it functions as a zero latency ADC. This bit has no affect when multiple analog input channels are enabled or when the single conversion mode is selected.

This bit enables a notch at 60 Hz when the output data rate is equal to 50 Hz. The bit should only be set when chop is disabled and when the device is operating with the zero latency function disabled. This bit allows simultaneous 50 Hz/60 Hz rejection.

Filter output data rate select bits. The 10 bits of data programmed into these bits determine the filter cutoff frequency, the position of the first notch of the filter, and the output data rate for the part. In association with the gain selection, it also determines the output noise (and, therefore, the effective resolution) of the device. When chop is disabled and continuous conversion mode is selected, the first notch of the filter occurs at a frequency determined by the relationship:

where FS is the decimal equivalent of the code in the FS0 to FS9 bits and is in the range 1 to 1023, and fmod is the modulator frequency, which is equal to MCLK/16. With a nominal MCLK of 4.92 MHz, this results in a first notch frequency range from 4.69 Hz to 4.8 kHz.

Changing the filter notch frequency or changing the gain impacts resolution. Tabl e 6 through Ta ble

filter is used. The benefit of the sinc3 filter compared to the sinc4 filter is its lower settling time

, the sinc3 filter has a settling time of f

filter has a settling time of f

Filter First Notch Frequency = (f

MOD

/4. The sinc4 filter, due to its deeper notches, gives better

ADC

filter for rms noise and no missing codes.

/64)/FS

ADC

13 show the effect of the filter notch frequency and gain on the effective resolution of the AD7190.

The output data rate (or effective conversion time) for the device is equal to the frequency selected for the first notch of the filter. For example, if the first notch of the filter is selected at 50 Hz, a new word is available at a 50 Hz rate or every 20 ms. When chop is enabled, the output data rate equals

Output Data Rate = (f where FS is the decimal equivalent of the code in the FS0 to FS9 bits and is in the range 1 to 1023, and fmod is the modulator frequency, which is equal to MCLK/16. With a nominal MCLK of 4.92 MHz, this results in a conversion rate from 4.69/N Hz to 4.8/N kHz, where N is the order of the sinc filter.

/64)/(N x FS)

MOD

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Table 18. Operating Modes

MD2 MD1 MD0 Mode

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1 Internal full-scale calibration. A full-scale input voltage is automatically connected to the input for this calibration.

1 1 0

1 1 1

Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. The DOUT/ RDY conversion is complete. The user can read these conversions by setting the CREAD bit in the communications register to 1, which enables continuous read. When continuous read is enabled, the conversions are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output each conversion by writing to the communications register. After power-on, a reset, or a recon-figuration of the ADC, the complete settling time of the filter is required to generate the first valid conversion. Subsequent conversions are available at the selected output data rate, which is dependent on filter choice.

Single conversion mode. When single conversion mode is selected, the ADC powers up and performs a single conversion on the selected channel. The internal clock requires up to 1 ms to power up and settle. The ADC then performs the conversion, which requires the complete settling time of the filter. The conversion result is placed in the data register, RDY register and RDY

Idle mode. In idle mode, the ADC filter and modulator are held in a reset state even though the modulator clocks are still provided.

Power-down mode. In power-down mode, all AD7190 circuitry, except the bridge power-down switch, is powered down. The bridge power-down switch remains active because the user may need to power up the sensor prior to powering up the AD7190 for settling reasons. The external crystal, if selected, remains active.

Internal zero-scale calibration. An internal short is automatically connected to the input. RDY calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a

calibration. The measured offset coefficient is placed in the offset register of the selected channel.

RDY

goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is required each time the gain of a channel is changed to minimize the fullscale error.

System zero-scale calibration. The user should connect the system zero-scale input to the channel input pins as selected by the CH7 to CH0 bits in the configuration register. RDY returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. A system zero-scale calibration is required each time the gain of a channel is changed.

System full-scale calibration. The user should connect the system full-scale input to the channel input pins as selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is required each time the gain of a channel is changed.

goes low, and the ADC returns to power-down mode. The conversion remains in the data

remains active (low) until the data is read or another conversion is performed.

pin and the RDY bit in the status register go low when a

goes high when the

goes high when the calibration is initiated and

CONFIGURATION REGISTER

(RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x000117)

The configuration register is a 24-bit register from which data can be read or to which data can be written. This register is used to configure the ADC for unipolar or bipolar mode, to enable or disable the buffer, to enable or disable the burnout currents, to select the gain, and to select the analog input channel.

Tabl e 1 9 outlines the bit designations for the filter register. CON0 through CON23 indicate the bit locations. CON denotes that the bits are in the configuration register. CON23 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit.

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CON23 CON22 CON21 CON20 CON19 CON18 CON17 CON16 Chop(0) 0(0) 0(0) REFSEL(0) 0(0) 0(0) 0(0) (0) CON15 CON14 CON13 CON12 CON11 CON10 CON9 CON8

CH7(0) CH6(0) CH5(0) CH4(0) CH3(0) CH2(0) CH1(0) CH0(1)

CON7 CON6 CON5 CON4 CON3 CON2 CON1 CON0

Burn(0) REFDET(0) 0(0) BUF(1)

Table 19. Configuration Register Bit Designations

Bit Location Bit Name Description CON23 Chop

CON22, CON21 These bits must be programmed with a Logic 0 for correct operation. CON20 REFSEL Reference select bits. The reference source for the ADC is selected using these bits.

CON19 to CON16 These bits must be programmed with a Logic 0 for correct operation. CON15 to CON8 CH7 to CH0

CON7 Burn

CON6 REFDET

CON5 This bit must be programmed with a Logic 0 for correct operation. CON4 BUF

CON3

CON2 to CON0 G2 to G0 Gain select bits. Written by the user to select the ADC input range as follows:

U/B

Chop enable bit. When the chop bit is cleared, chop is disabled. When the chop bit is set, chop is enabled. When chop is enabled, the offset and offset drift of the ADC are continuously minimized. However, this increases the conversion time and settling time of the ADC. For example, when FS = 96 decimal and the sinc4 filter is selected, the conversion time with chop enabled equals 80 ms and the settling time equals 160 ms. With chop disabled, higher conversion rates are allowed. For an FS word of 96 decimal and the sinc4 filter selected, the conversion time is 20 ms and the settling time is 80 ms. However, at low gains, periodic calibrations may be required to remove the offset and offset drift.

REFSEL Reference Voltage 0

1 External reference applied between the P1 and P0 pins.

Channel select bits. These bits are used to select which channels are enabled on the AD7190. See Table 20. Several channels can be selected, and the AD7190 automatically sequences them. The conversion on each channel requires the complete settling time.

When this bit is set to 1 by the user, the 500 nA current sources in the signal path are enabled. When burn = 0, the burnout currents are disabled. The burnout currents can be enabled only when the buffer is active and when chop is disabled.

Enables the reference detect function. When set, the NOREF bit in the status register indicates when the external reference being used by the ADC is open circuit or less than 0.5 V typically. The reference detect circuitry only operates when the ADC is active.

Configures the ADC for a buffered or an unbuffered mode of operation. If cleared, the ADC operates in unbuffered mode, lowering the power consumption of the device. If set, the ADC operates in buffered mode, allowing the user to place source impedances on the front end without contributing gain errors to the system. With the buffer disabled, the voltage on the analog input pins can be from 50 mV below GND to 50 mV above AV voltage on any input pin must be limited to 250 mV within the power supply rails.

Polarity select bit. When this bit is set, unipolar operation is selected. When this bit is cleared, bipolar operation is selected.

G2 G1 G0 Gain ADC Input Range (5 V Reference, Bipolar Mode) 0 0 0 1 +5 V 0 0 1 Reserved 0 1 0 Reserved 0 1 1 8 +625 mV 1 0 0 16 +312.5 mV 1 0 1 32 +156.2 mV 1 1 0 64 +78.125 mV 1 1 1 128 +39.06 mV

External reference applied between REFIN1(+) and REFIN1(−).

. When the buffer is enabled, it requires some headroom; therefore, the

U/B

(0)

G2(1) G1(1) G0(1)

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Table 20. Channel Selection

Channel Enable Bits in the Configuration Register

CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0

1 Temperature sensor 0010 None 1

Channel Enabled

AIN1 to AIN2

AIN3 to AIN4

AIN2 to AIN2

AIN1 to AINCOM

AIN2 to AINCOM

AIN3 to AINCOM

AIN4 to AINCOM

Status Register Bits CHD[3:0]

0000 0

0001 1

0011 0

0100 0

0101 1

0110 2

0111 3

Calibration Register Pair

DATA REGISTER

(RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x000000)

The conversion result from the ADC is stored in this data register. This is a read-only, 24-bit register. On completion of a read operation from this register, the the DAT_STA bit in the mode register is set to 1, the contents of the status register are appended to each 24-bit conversion. This is required when several analog input channels are enabled because the four LSBs of the status register (CHD3 to CHD0) identify the channel from which the conversion originated.

RDY

pin/bit is set. When

GPOCON REGISTER

(RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00)

The GPOCON register is an 8-bit register from which data can be read or to which data can be written. This register is used to enable the general-purpose digital outputs.

Tabl e 2 1 outlines the bit designations for the GPOCON register. GP0 through GP7 indicate the bit locations. GP denotes that the bits are in the GPOCON register. GP7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit.

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AD7190

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GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0

0(0) BPDSW(0) GP32EN(0) GP10EN(0) P3DAT(0) P2DAT(0) P1DAT(0) P0DAT(0)

Table 21. Register Bit Designations

Bit Location Bit Name Description GP7 0 This bit must be programmed with a Logic 0 for correct operation. GP 6 BPDSW

GP5 GP32EN

GP4 GP10EN

GP3 P3DAT

GP2 P2DAT

GP1 P1DAT

GP0 P0DAT

Bridge power-down switch control bit. This bit is s BPDSW to AGND. The switch can sink up to 30 mA. The bit is cleared by the user to open the bridge powerdown switch. When the ADC is placed in power-down mode, the bridge power-down switch remains active.

Digital Output P3 and Digital Output P2 enable. When GP32EN is set, the digital outputs, P3 and P2, are active. When GP32EN is cleared, the P3 and P2 pins are tristated, and the P3DAT and P2DAT bits are ignored.

Digital Output P1 and Digital Output P0 enable. When GP10EN is set, the digital outputs, P1 and P0, are active. When GP10EN is cleared, the P1 and P0 outputs are tristated, and the P1DAT and P0DAT bits are ignored. The P1 and P0 pins can be used as a reference input REFIN2 when the REFSEL bit in the configuration register is set to 1.

Digital Output P3. When GP32EN is set, the P3DAT bit sets the value of the P3 general-purpose output pin. When P3DAT is high, the P3 output pin is high. When P3DAT is low, the P3 output pin is low. When the GPOCON register is read, the P3DAT bit reflects the status of the P3 pin; that is, a fault condition on the P3 pin is detected.

Digital Output P2. When GP32EN is set, the P2DAT bit sets the value of the P2 general-purpose output pin. When P2DAT is high, the P2 output pin is high. When P2DAT is low, the P2 output pin is low. When the GPOCON register is read, the P2DAT bit reflects the status of the P2 pin; that is, a fault condition on the P2 pin is detected.

Digital Output P1. When GP10EN is set, the P1DAT bit sets the value of the P1 general-purpose output pin. When P1DAT is high, the P1 output pin is high. When P1DAT is low, the P1 output pin is low. When the GPOCON register is read, the P1DAT bit reflects the status of the P1 pin; that is, a fault condition on the P1 pin is detected.

Digital Output P0. When GP10EN is set, the P0DAT bit sets the value of the P0 general-purpose output pin. When P0DAT is high, the P0 output pin is high. When P0DAT is low, the P0 output pin is low. When the GPOCON register is read, the P0DAT bit reflects the status of the P0 pin; that is, a fault condition on the P0 pin is detected.

et by the user to close the bridge power-down switch

OFFSET REGISTER

(RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x800000)

The offset register holds the offset calibration coefficient for the ADC. The power-on reset value of the offset register is 0x800000. The AD7190 has four offset registers; therefore, each channel has a dedicated offset register. Each of these registers is a 24-bit read/write register. This register is used in conjunction with its associated full-scale register to form a register pair. The poweron reset value is automatically overwritten if an internal or system zero-scale calibration is initiated by the user. The AD7190 must be placed in power-down mode or idle mode when writing to the offset register.

FULL-SCALE REGISTER

(RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXXX0)

The full-scale register is a 24-bit register that holds the full-scale calibration coefficient for the ADC. The AD7190 has four fullscale registers; therefore, each channel has a dedicated full-scale register. The full-scale registers are read/write registers. However, when writing to the full-scale registers, the ADC must be placed in power-down mode or idle mode. These registers are configured at power-on with factory-calibrated, full-scale calibration coefficients, the calibration being performed at gain = 1. Therefore, every device has different default coefficients. The default value is automatically overwritten if an internal or system full-scale calibration is initiated by the user or if the full-scale register is written to.

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ADC CIRCUIT INFORMATION

REFIN1(+)

OUT–

IN+

OUT+

IN–

AIN1 AIN2 AIN3 AIN4 AINCOM

REFIN1(–)

BPDSW

AGND

MUX

AGND

PGA

TEMP

SENSOR

AD7190

AGND

Figure 18. Basic Connection Diagram

DGND

Σ-Δ

ADC

CLOCK

CIRCUITRY

MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+)

REFERENCE

DETECT

SERIAL

INTERFACE

AND

CONTROL

LOGIC

DOUT/RDY

DIN

SCLK

SYNC

7640-012

OVERVIEW

The AD7190 is an ultralow noise ADC that incorporates a ∑-∆ modulator, a buffer, PGA, and on-chip digital filtering intended for the measurement of wide dynamic range signals such as those in pressure transducers, weigh scales, and strain gauge applications.

The part can be configured to have two differential inputs or four pseudo differential inputs that can be buffered or unbuffered. Figure 18 shows the basic connections required to operate the part.

FILTER, OUTPUT DATA RATE, SETTLING TIME

A ∑-∆ ADC consists of a modulator followed by a digital filter. The AD7190 has two filter options: a sinc filter. The filter is selected using the sinc3 bit in the mode register. When sinc3 is set to 0 (default value), the sinc selected. The sinc

filter is selected when sinc3 is set to 1.

At low update rates (<1 kHz), the noise-free resolution is comparable for the two filter types. However, at the higher update rates, the sinc

The sinc

filter also leads to better 50 Hz and 60 Hz rejection.

filter gives better noise free resolution.

While the notch positions are not affected by the order of the filter, the higher order filter has wider notches, which leads to better rejection in the band (±1 Hz) around the notches. It also gives better stop-band attenuation. The benefit of the sinc is its lower settling time for the same output data rate.

Chop Disabled

The output data rate (the rate at which conversions are available on a single channel when the ADC is continuously converting) is equal to

= f

ADC

/(1024 × FS[9:0])

CLK

filter and a sinc4

filter is

filter

where:

is the output data rate.

ADC

= master clock (4.92 MHz nominal).

CLK

FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the

mode register.

The output data rate can be programmed from 4.7 Hz to 4800 Hz; that is, FS[9:0] can have a value from 1 to 1023.

The above equation is valid for both the sinc The settling time for the sinc

SETTLE

= 4/f

ADC

filter is equal to

Whereas the settling time for the sinc

SETTLE

= 3/f

ADC

and sinc4 filters.

filter is equal to

Figure 19 and Figure 20 show the frequency response of the sinc and sinc

filters, respectively, for an output data rate of 50 Hz.

–10

–20

–30

–40

–50

–60

FILTER GAIN (dB)

–70

–80

–90

–100

0 255075100125150

Figure 19. Sinc

FREQUENCY (Hz)

Filter Response (50 Hz Output Data Rate)

07640-013

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AD7190

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–10

–20

–30

–40

–50

–60

FILTER GAIN (dB)

–70

–80

–90

–100

0 255075100125150

Figure 20. Sinc

FREQUENCY (Hz)

Filter Response (50 Hz Output Data Rate)

07640-014

As shown in the plots, the sinc4 filter provides 50 Hz (±1 Hz) rejection in excess of 120 dB, assuming a stable master clock, while the sinc attenuation is typically 53 dB for the sinc 40 dB for the sinc

The 3 dB frequency for the sinc

3dB

and for the sinc

3dB

filter gives a rejection of 100 dB. The stop-band

filter.

filter is equal to

= 0.23 × f

= 0.272 × f

ADC

filter is equal to

ADC

filter but equal to

Chop Enabled

With chop enabled, the analog input offset and offset drift are minimized. When chop is enabled, the analog input pins are continuously swapped. Therefore, with the analog input pins connected in one direction, the settling time of the sinc filter is allowed to elapse until a valid conversion is available. The analog input pins are then inverted and another valid conversion is obtained. Subsequent conversions are then averaged so that the offset is minimized. This continuous swapping of the analog input pins and the averaging of subsequent conversions means that the offset drift is also minimized.

Chopping affects the output data rate and settling time of the ADC. For the sinc

= f

ADC

For sinc

filter, the output data rate is equal to

= f

ADC

filter, the output data rate is equal to

/(4 x 1024 × FS[9:0])

CLK

/(3 x 1024 × FS[9:0])

CLK

where:

is the output data rate.

ADC

= master clock (4.92 MHz nominal).

CLK

FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the

mode register.

The value of FS[9:0] can be varied from 1 to 1023. This results in an output data rate of 1.173 Hz to 1200 Hz for the sinc and 1.56 Hz to 1600 Hz for the sinc

the sinc

or sinc4 filter is equal to

SETTLE

= 2/f

ADC

filter. The settling time for

filter

Therefore, with chop enabled, the settling time is reduced for a given output data rate compared to the chop disabled mode. For either the sinc

or the sinc4 filter, the cutoff frequency f

3dB

equal to

= 0.24 × f

3dB

Figure 21 and Figure 22 show the filter response for the sinc and sinc

filters, respectively, when chop is enabled. As shown

ADC

in the plots, the stop-band attenuation is less compared with the chop disabled modes.

–10

–20

–30

–40

–50

–60

FILTER GAIN (dB)

–70

–80

–90

–100

0 255075100125150

Figure 21. Sinc

–10

–20

–30

–40

–50

–60

FILTER GAIN (dB)

–70

–80

–90

–100

0 255075100125150

Figure 22. Sinc

Filter Response (Output Data Rate = 12.5 Hz, Chop Enabled)

Filter Response (Output Data Rate = 16.6 Hz, Chop Enabled)

FREQUENCY (Hz)

07640-015

07640-016

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AD7190

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50 Hz/60 Hz Rejection

Normal mode rejection is one of the main functions of the digital filter. With chop disabled, 50 Hz rejection is obtained when the output data rate is set to 50 Hz, whereas 60 Hz rejection is achieved when the output data rate is set to 60 Hz. Simul-taneous 50 Hz and 60 Hz rejection is obtained when the output data rate is set to 10 Hz. Simultaneous 50 Hz/60 Hz rejection can also be achieved using the REJ60 bit in the mode register. When the output data rate is programmed to 50 Hz and the REJ60 bit is set to 1, notches are placed at both 50 Hz and 60 Hz.

Figure 23 and Figure 24 show the frequency response of the

sinc

and sinc3 filters, respectively, when the output data rate is

programmed to 50 Hz and REJ60 is set to 1.

–10

–20

–30

–40

–50

–60

FILTER GAIN (dB)

–70

–80

–90

–100

0 255075100125150

Figure 23. Sinc

–10

–20

–30

–40

–50

–60

FILTER GAIN (dB)

–70

–80

–90

–100

Figure 24. Sinc

Filter Response (50 Hz Output Data Rate, REJ60 = 1)

0 255075100125150

Filter Response (50 Hz Output Data Rate, REJ60 = 1)

Again, the sinc4 filter provides better 50 Hz/60 Hz rejection than the sinc

filter. In addition, better stop-band attenuation is

achieved with the sinc

When chop is enabled, lower output data rates must be used to achieve 50 Hz and 60 Hz rejection. An output data rate of 12.5 Hz gives simultaneous 50 Hz/60 Hz rejection when the sinc selected, whereas an output data rate of 16.7 Hz gives simultaneous 50 Hz/ 60 Hz rejection when the sinc

FREQUENCY (Hz)

filter.

filter is

filter is used. Setting the

07640-017

07640-018

REJ60 bit at these output data rates further improves the rejection at 60 Hz. Figure 25 and Figure 26 show the filter response for both output data rates when REJ60 is set to 1.

–10

–20

–30

–40

–50

–60

FILTER GAIN (dB)

–70

–80

–90

–100

0 255075100125150

Figure 25. Sinc

FREQUENCY (Hz)

Filter Response (12.5 Hz Output Data Rate,

07640-125

Chop Enabled, REJ60 = 1)

–10

–20

–30

–40

–50

–60

FILTER GAIN (dB)

–70

–80

–90

–100

0 255075100125150

Figure 26. Sinc

FREQUENCY (Hz)

Filter Response (16.7 Hz Output Data Rate,

07640-126

Chop Enabled, REJ60 = 1)

Channel Sequencer

The AD7190 includes a channel sequencer, which simplifies communications with the device in multichannel applications. Bis CH0 to Bit CH7 in the configuration register are used to enable the required channels. In continuous conversion mode, the ADC selects each of the enabled channels in sequence and performs a conversion on the channel. The

pin goes low

RDY

when a valid conversion is available on each channel. When several channels are enabled, the contents of the status register should be attached to the 24-bit word so that the user can identify the channel that corresponds to each conversion. To attach the status register value to the conversion, Bit DAT_STA in the mode register should be set to 1.

When several channels are enabled, the ADC must allow the complete settling time to generate a valid conversion each time that the channel is changed. The AD7190 takes care of this: when a channel is selected, the modulator and filter are reset

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AD7190

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and the

pin is taken high. The AD7190 then allows the

RDY

complete settling time to generate the first conversion.

only goes low when a valid conversion is available. The

RDY AD7190 then selects the next enabled channel and converts on

that channel. The user can then read the data register while the ADC is performing the conversion on the next channel.

The frequency at which all enabled channels are converted is equal to

× Number of Enabled Channels

SETTLE

For example, if the sinc zero latency is disabled, conversions are available at 1/f converting on a single channel, where f

filter is selected, chop is disabled and

when

ADC

is equal to the output

ADC

data rate. The settling time is equal to

SETTLE

= 4/f

ADC

The time required to sample N channels is

4/(f

× N)

ADC

RDY

CONVERSIONS

CHANNEL A CHANNEL B

1/f

ADC

Figure 27. Channel Sequencer

CHANNEL C

Zero Latency

Zero latency is enabled by setting the SINGLE bit in the mode register to 1. With zero latency, the complete settling time is allowed for each conversion. Therefore,

ADC

= 1/t

SETTLE

Zero latency means that the output data rate is constant irrespective of the number of analog input channels enabled; the user does not need to consider the effects of channel changes on the output data rate. The disadvantages of zero latency are the increased noise for a given output data rate compared with the nonzero latency mode. For example, when zero latency is not enabled, the AD7190 has a noise-free resolution of 18.5 bits when the output data rate is 50 Hz and the gain is set to 128. When zero latency is enabled, the ADC has a resolution of 17.5 bits peak-to-peak when the output data rate is 50 Hz. The filter response also changes. Figure 19 shows the filter response for the sinc

filter when the output data rate is 50 Hz (zero latency disabled). Figure 28 shows the filter response when zero latency is enabled and the output data rate is 50 Hz (sinc

filter); 50 Hz rejection is no longer achieved. The ADC needs to operate with an output data rate of 12.5 Hz to obtain 50 Hz rejection when zero latency is enabled. To obtain simultaneous 50 Hz/60 Hz rejection, the REJ60 bit in the mode register can be set when the output data rate is equal to 12.5 Hz. The stop-band attenuation is considerably reduced also (3 dB compared with 53 dB in the nonzero latency mode).

–10

–20

–30

–40

–50

–60

FILTER GAIN (dB)

–70

–80

–90

–100

010050 200 300 400 500150 250 350 450 550 600

Figure 28. Sinc

Filter Response (50 Hz Output Data Rate, Zero Latency)

FREQUENCY (Hz)

07640-020

DIGITAL INTERFACE

As indicated in the On-Chip Registers section, the programmable functions of the AD7190 are controlled using a set of on-chip registers. Data is written to these registers via the serial interface of the part. Read access to the on-chip registers is also provided by this interface. All communication with the part must start with a write to the communications register. After power-on or reset,

07640-019

the device expects a write to its communications register. The data written to this register determines whether the next operation is a read operation or a write operation and also determines which register this read or write operation affects. Therefore, write access to any of the other registers on the part begins with a write operation to the communications register, followed by a write to the selected register. A read operation from any other register (except when continuous read mode is selected) starts with a write to the communications register, followed by a read operation from the selected register.

The serial interface of the AD7190 consists of four signals: DIN, SCLK, and DOUT/ data into the on-chip registers, whereas DOUT/

RDY

. The DIN line is used to transfer

RDY

is used for accessing data from the on-chip registers. SCLK is the serial clock input for the device, and all data transfers (either on DIN or

RDY

DOUT/

The DOUT/

) occur with respect to the SCLK signal.

RDY

pin functions as a data ready signal also, the line going low when a new data-word is available in the output register. It is reset high when a read operation from the data register is complete. It also goes high prior to the updating of the data register to indicate when not to read from the device, to ensure that a data read is not attempted while the register is being updated.

is used to select a device. It can be used to decode the AD7190 in systems where several components are connected to the serial bus.

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Figure 3 and Figure 4 show timing diagrams for interfacing to the AD7190, with the timing for a read operation from the output shift register of the AD7190, and shows the timing for a write operation to the input shift register. It is possible to read the same word from the data register several times even though the DOUT/ line returns high after the first read operation. However, care must be taken to ensure that the read operations have been completed before the next output update occurs. In continuous read mode, the data register can be read only once.

The serial interface can operate in 3-wire mode by tying In this case, the SCLK, DIN, and DOUT/ communicate with the AD7190. The end of the conversion can be monitored using the interfacing to microcontrollers.

is required as a decoding signal, it can be generated from a port pin. For microcontroller interfaces, it is recommended that SCLK idle high between data transfers.

The AD7190 can be operated with ization signal. This scheme is useful for DSP interfaces. In this case, the first bit (MSB) is effectively clocked out by CS

normally occurs after the falling edge of SCLK in DSPs. The SCLK can continue to run between data transfers, provided the timing numbers are obeyed.

The serial interface can be reset by writing a series of 1s to the DIN input. If a Logic 1 is written to the AD7190 DIN line for at least 40 serial clock cycles, the serial interface is reset. This ensures that the interface can be reset to a known state if the interface gets lost due to a software error or some glitch in the system. Reset returns the interface to the state in which it is expecting a write to the communications register. This operation resets the contents of all registers to their power-on values. Following a reset, the user should allow a period of 500 μs before addressing the serial interface.

being used to decode the part. shows

Figure 4

RDY

bit or pin. This scheme is suitable for

used as a frame synchron-

Figure 3

RDY

lines are used to

because

RDY

low.

The AD7190 can be configured to continuously convert or to perform a single conversion. See Figure 29 through Figure 31.

Single Conversion Mode

In single conversion mode, the AD7190 is placed in powerdown mode after conversions. When a single conversion is initiated by setting MD2, MD1, and MD0 to 0, 0, 1, respectively, in the mode register, the AD7190 powers up, performs a single conversion, and then returns to power-down mode. The onchip oscillator requires 1 ms approximately to power up.

RDY

DOUT/ When the data word has been read from the data register, DOUT/ until another conversion is initiated and completed. The data register can be read several times, if required, even when DOUT/

If several channels are enabled, the ADC sequences through the enabled channels and performs a conversion on each channel. When a conversion is started, DOUT/

and remains high until a valid conversion is available. As soon as the conversion is available, DOUT/

then selects the next channel and begins a conversion. The user can read the present conversion while the next conversion is being performed. As soon as the next conversion is complete, the data register is updated; therefore, the user has a limited period in which to read the conversion. When the ADC has performed a single conversion on each of the selected channels, it returns to power-down mode.

If the DAT_STA bit in the mode register is set to 1, the contents of the status register are output along with the conversion each time that the data read is performed. The four LSBs of the status register indicate the channel to which the conversion corresponds.

goes low to indicate the completion of a conversion.

RDY

goes high. If CS is low, DOUT/

RDY

has gone high.

RDY

remains high

RDY

goes low. The ADC

RDY

goes high

DIN

DOUT/RDY

SCLK

0x08 0x58

0x280060

Figure 29. Single Conversion

Rev. 0 | Page 30 of 40

DATA

07640-021

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Continuous Conversion Mode

Continuous conversion is the default power-up mode. The AD7190 converts continuously, the register going low each time a conversion is complete. If low, the DOUT/ completed. To read a conversion, the user writes to the communications register, indicating that the next operation is a read of the data register. The digital conversion is placed on the DOUT/ ADC. DOUT/ The user can read this register additional times, if required. However, the user must ensure that the data register is not being

RDY

line also goes low when a conversion is

pin as soon as SCLK pulses are applied to the

RDY

returns high when the conversion is read.

RDY

bit in the status

accessed at the completion of the next conversion or else the new conversion word is lost.

When several channels are enabled, the ADC continuously loops through the enabled channels, performing one conversion on each channel per loop. The data register is updated as soon as each conversion is available. The DOUT/ each time a conversion is available. The user can then read the conversion while the ADC converts on the next enabled channel.

If the DAT_STA bit in the mode register is set to 1, the contents of the status register are output along with the conversion each time that the data read is performed. The status register indicates the channel to which the conversion corresponds.

RDY

pin pulses low

DIN

DOUT/RDY

SCLK

0x58 0x58

DATA DATA

Figure 30. Continuous Conversion

07640-022

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AD7190

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Continuous Read

Rather than write to the communications register each time a conversion is complete to access the data, the AD7190 can be configured so that the conversions are placed on the DOUT/ RDY

line automatically. By writing 01011100 to the communications register, the user need only apply the appropriate number of SCLK cycles to the ADC, and the conversion word is automatically placed on the DOUT/ conversion is complete. The ADC should be configured for continuous conversion mode.

When DOUT/ sufficient SCLK cycles must be applied to the ADC; the data conversion is then placed on the DOUT/ conversion is read, DOUT/ conversion is available. In this mode, the data can be read only once. Also, the user must ensure that the data-word is read before the next conversion is complete. If the user has not read the conversion before the completion of the next conversion, or if insufficient serial clocks are applied to the AD7190 to read the word, the serial output register is reset when the next

RDY

goes low to indicate the end of a conversion,

RDY

line when a

RDY

line. When the

returns high until the next

conversion is complete and the new conversion is placed in the output serial register.

To exit the continuous read mode, the instruction 01011000 must be written to the communications register while the RDY

pin is low. While in the continuous read mode, the ADC monitors activity on the DIN line so that it can receive the instruction to exit the continuous read mode. Additionally, a reset occurs if 40 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to the device.

When several channels are enabled, the ADC continuously steps through the enabled channels and performs one conversion on each channel each time that it is selected. DOUT/ RDY

pulses low when a conversion is available. When the user applies sufficient SCLK pulses, the data is automatically placed on the DOUT/ register is set to 1, the contents of the status register are output along with the conversion. The status register indicates the channel to which the conversion corresponds.

RDY

pin. If the DAT_STA bit in the mode

DIN

DOUT/RDY

SCLK

0x5C

DATA DATA DATA

7640-023

Figure 31. Continuous Read

Rev. 0 | Page 32 of 40

AD7190

www.BDTIC.com/ADI

CIRCUIT DESCRIPTION

ANALOG INPUT CHANNEL

The AD7190 has two differential/four pseudo differential analog input channels which can be buffered or unbuffered. In buffered mode (the BUF bit in the configuration register is set to 1), the input channel feeds into a high impedance input stage of the buffer amplifier. Therefore, the input can tolerate significant source impedances and is tailored for direct connection to external resistive-type sensors such as strain gauges or resistance temperature detectors (RTDs).

When BUF = 0, the part is operated in unbuffered mode. This results in a higher analog input current. Note that this unbuffered input path provides a dynamic load to the driving source. Therefore, resistor/capacitor combinations on the input pins can cause gain errors, depending on the output impedance of the source that is driving the ADC input. allowable external resistance/capacitance values for unbuffered mode at a gain of 1 such that no gain error at the 20-bit level is introduced.

Table 22. External R-C Combination for No 20-Bit Gain Error

C (pF) R (Ω)

50 1.4 k 100 850 500 300 1000 230 5000 30

The absolute input voltage range in buffered mode is restricted to a range between AGND + 250 mV and AV must be taken in setting up the common-mode voltage so that these limits are not exceeded. Otherwise, there is degradation in linearity and noise performance.

The absolute input voltage in unbuffered mode includes the range between AGND – 50 mV and AV negative absolute input voltage limit does allow the possibility of monitoring small true bipolar signals with respect to GND.

Table 2 2 shows the

– 250 mV. Care

+ 50 mV. The

PGA

When the gain stage is enabled, the output from the buffer is applied to the input of the programmable gain array (PGA). The presence of the PGA means that signals of small amplitude can be gained within the AD7190 while still maintaining excellent noise performance. For example, when the gain is set to 128, the rms noise is 8.5 nV, typically, when the output data rate is 4.7 Hz, which is equivalent to 23 bits of effective resolution or

20.5 bits of noise-free resolution.

The AD7190 can be programmed to have a gain of 1, 8, 16, 32, 64, and 128 using Bit G2 to Bit G0 in the configuration register. Therefore, with an external 2.5 V reference, the unipolar ranges are from 0 mV to 19.53 mV to 0 V to 2.5 V, and the bipolar ranges are from ±19.53 mV to ±2.5 V.

The analog input range must be limited to (AV because the PGA requires some headroom. Therefore, if V AV

= 5 V, the maximum analog input that can be applied to

the AD7190 is 0 to 3.75 V/gain in unipolar mode or ±3.75 V/ gain in bipolar mode.

BIPOLAR/UNIPOLAR CONFIGURATION

The analog input to the AD7190 can accept either unipolar or bipolar input voltage ranges. A bipolar input range does not imply that the part can tolerate negative voltages with respect to system GND. Unipolar and bipolar signals on the AIN(+) input are referenced to the voltage on the AIN(−) input. For example, if AIN(

−) is 2.5 V and the ADC is configured for unipolar mode

with a gain of 1, the input voltage range on the AIN(+) pin is

2.5 V to 5 V when a 2.5 V reference is used.

If the ADC is configured for bipolar mode, the analog input range on the AIN(+) input is 0 V to 5 V. The bipolar/unipolar option is chosen by programming the U/ ation register.

DATA OUTPUT CODING

When the ADC is configured for unipolar operation, the output code is natural (straight) binary with a zero differential input voltage resulting in a code of 00...00, a midscale voltage resulting in a code of 100...000, and a full-scale input voltage resulting in a code of 111...111. The output code for any analog input voltage can be represented as

Code = (2

When the ADC is configured for bipolar operation, the output code is offset binary with a negative full-scale voltage resulting in a code of 000...000, a zero differential input voltage resulting in a code of 100...000, and a positive full-scale input voltage resulting in a code of 111...111. The output code for any analog input voltage can be represented as

Code = 2

where AIN is the analog input voltage, gain is the PGA setting (1 to 128), and N = 24.

× AIN × gain)/V

N – 1

× [(AIN × gain/V

REF

) + 1]

CLOCK

The AD7190 includes an internal 4.92 MHz clock on-chip. This internal clock has a tolerance of ±4%. Either the internal clock or an external crystal/clock can be used as the clock source to the AD7190. The clock source is selected using the CLK1 and CLK0 bits in the mode register. When an external crystal is used, it must be connected across the MCLK1 and MCLK2 pins. The crystal manufacturer recommends the load capacitances required for the crystal. The MCLK1 and MCLK2 pins of the AD7190 have a capacitance of 15 pF, typically. If an external clock source is used, the clock source must be connected to the MCLK2 pin and the MCLK1 pin must be left floating.

− 1.25 V)/gain

REF

bit in the configur-

Rev. 0 | Page 33 of 40

AD7190

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The internal clock can also be made available at the MCLK2 pin. This is useful when several ADCs are used in an application and the devices need to be synchronized. The internal clock from one device can be used as the clock source for all ADCs in the system. Using a common clock, the devices can be synchronized by applying a common reset to all devices, or the

pin can be pulsed.

SYNC

BURNOUT CURRENTS

The AD7190 contains two 500 nA constant current generators, one sourcing current from AV current from AIN(−) to GND. The currents are switched to the selected analog input pair. Both currents are either on or off, depending on the burnout current enable (burn) bit in the configuration register. These currents can be used to verify that an external transducer remains operational before attempting to take measurements on that channel. After the burnout currents are turned on, they flow in the external transducer circuit, and a measurement of the input voltage on the analog input channel can be taken. If the resultant voltage measured is full scale, the user needs to verify why this is the case. A full-scale reading could mean that the front-end sensor is open circuit. It could also mean that the front-end sensor is overloaded and is justified in outputting full scale, or the reference may be absent and the NOREF bit in the status register is set, thus clamping the data to all 1s.

When reading all 1s from the output, the user needs to check these three cases before making a judgment. If the voltage measured is 0 V, it may indicate that the transducer has short circuited. The current sources work over the normal absolute input voltage range specifications when the analog inputs are buffered and chop is disabled.

REFERENCE

The ADC has a fully differential input capability for the reference channel. In addition, the user has the option of selecting one of two external reference options (REFIN1(x) or REFIN2(x)). The reference source for the AD7190 is selected using the REFSEL bit in the configuration register. The REFIN2(x) pins are dual purpose: they can function as two general-purpose output pins or as reference pins. When the REFSEL bit is set to 1, these pins automatically function as reference pins.

The common-mode range for these differential inputs is from GND to AV excessive R-C source impedances introduce gain errors. The reference voltage REFIN (REFINx(+) − REFINx(−)) is AV nominal, but the AD7190 is functional with reference voltages from 1 V to AV or current) for the transducer on the analog input also drives the reference voltage for the part, the effect of the low frequency noise in the excitation source is removed because the application is ratiometric. If the AD7190 is used in a nonratiometric application, use a low noise reference.

. The reference input is unbuffered; therefore,

. In applications where the excitation (voltage

to AIN(+) and one sinking

Recommended 2.5 V reference voltage sources for the AD7190 include the ADR421 and ADR431, which are low noise references. Also note that the reference inputs provide a high impedance, dynamic load. Because the input impedance of each reference input is dynamic, resistor/capacitor combinations on these inputs can cause dc gain errors, depending on the output impedance of the source driving the reference inputs.

Reference voltage sources like those recommended above (for example, ADR431) typically have low output impedances and are, therefore, tolerant to having decoupling capacitors on REFINx(+) without introducing gain errors in the system. Deriving the reference input voltage across an external resistor means that the reference input sees a significant external source impedance. External decoupling on the REFINx pins is not recommended in this type of circuit configuration.

REFERENCE DETECT

The AD7190 includes on-chip circuitry to detect whether the part has a valid reference for conversions or calibrations. This feature is enabled when the REFDET bit in the configuration register is set to 1. If the voltage between the selected REFINx(+) and REFINx(–) pins goes below 0.3 V or either the REFINx(+) or REFINx(–) input is open circuit, the AD7190 detects that it no longer has a valid reference. In this case, the NOREF bit of the status register is set to 1. If the AD7190 is performing normal conversions and the NOREF bit becomes active, the conversion results is all 1s. Therefore, it is not necessary to continuously monitor the status of the NOREF bit when performing conversions. It is only necessary to verify its status if the conversion result read from the ADC data register is all 1s. If the AD7190 is performing either an offset or full-scale calibration and the NOREF bit becomes active, the updating of the respective calibration registers is inhibited to avoid loading incorrect coefficients to these registers, and the ERR bit in the status register is set. If the user is concerned about verifying that a valid reference is in place every time a calibration is performed, the status of the ERR bit should be checked at the end of the calibration cycle.

RESET

The circuitry and serial interface of the AD7190 can be reset by writing consecutive 1s to the device; 40 consecutive 1s are required to perform the reset. This resets the logic, the digital filter, and the analog modulator, whereas all on-chip registers are reset to their default values. A reset is automatically performed on power-up. When a reset is initiated, the user must allow a period of 500 μs before accessing any of the onchip registers. A reset is useful if the serial interface becomes asynchronous due to noise on the SCLK line.

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AD7190

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SYSTEM SYNCHRONIZATION

SYNC

The digital filter without affecting any of the setup conditions on the part. This allows the user to start gathering samples of the analog input from a known point in time, that is, the rising edge of SYNC to implement the synchronization function.

If multiple AD7190 devices are operated from a common master clock, they can be synchronized so that their data registers are updated simultaneously. A falling edge on the the digital filter and the analog modulator and places the AD7190 into a consistent, known state. While the

AD7190 is maintained in this state. On the the modulator and filter are taken out of this reset state and, on the next clock edge, the part starts to gather input samples again. In a system using multiple AD7190 devices, a common signal to their done after each AD7190 has performed its own calibration or has had calibration coefficients loaded into its calibration registers. The conversions from the AD7190s are then synchronized.

The part is taken out of reset on the master clock falling edge following the multiple devices are being synchronized, the be taken high on the master clock rising edge to ensure that all devices begin sampling on the master clock falling edge. If the SYNC have a difference of one master clock cycle between the devices; that is, the instant at which conversions are available differs from part to part by a maximum of one master clock cycle.

The In this mode, the rising edge of falling edge of The disadvantage of this scheme is that the settling time of the

filter has to be allowed for each data register update. This means that the rate at which the data register is updated is reduced. For example, if the ADC is configured to use the sinc latency is disabled and chop is disabled, the data register update takes four times longer.

input allows the user to reset the modulator and the

SYNC

needs to be taken low for four master clock cycles

SYNC

pin resets

SYNC

pin is low, the

SYNC

rising edge,

SYNC

pins synchronizes their operation. This is normally

SYNC

low to high transition. Therefore, when

SYNC

pin should

pin is not taken high in sufficient time, it is possible to

SYNC

pin can also be used as a start conversion command.

SYNC

starts conversion, and the

RDY

indicates when the conversion is complete.

filter, zero

TEMPERATURE SENSOR

Embedded in the AD7190 is a temperature sensor. This is selected using the CH2 bit in the configuration register. When the CH2 bit is set to 1, the temperature sensor is enabled. When the temperature sensor is selected and bipolar mode is selected, the device should return a code of 0x800000 when the temperature is 0 K. A one-point calibration is needed to get the optimum performance from the sensor. Therefore, a conversion at a known temperature should be recorded. Using this point along with the 0 K point, the gain error can be calculated. The sensitivity is 2815 codes/°C, typically. The equation for the temperature sensor is

Temp (K) = (Conversion – 0x800000)/2815 K

Temp (°C) = Temp (K) – 273

Following the one point calibration, the internal temperature sensor has an accuracy of ±2 °C, typically.

BRIDGE POWER-DOWN SWITCH

In bridge applications such as strain gauges and load cells, the bridge itself consumes the majority of the current in the system. For example, a 350  load cell requires 15 mA of current when excited with a 5 V supply. To minimize the current consumption of the system, the bridge can be disconnected (when it is not being used) using the bridge power-down switch. Figure 18 shows how the bridge power-down switch is used. The switch can withstand 30 mA of continuous current, and it has an on resistance of 10  maximum.

LOGIC OUTPUTS

The AD7190 has four general-purpose digital outputs, P0, P1, P2, and P3. These are enabled using the GP32EN and GP10EN bits in the GPOCON register. The pins can be pulled high or low using the P0DAT to P3DAT bits in the GPOCON register; that is, the value at the pin is determined by the setting of the P0DAT to P3DAT bits. The logic levels for these pins are determined by AV register is read, the bits P0DAT to P3DAT reflect the actual value at the pins. This is useful for short-circuit detection.

These pins can be used to drive external circuitry, for example, an external multiplexer. If an external multiplexer is used to increase the channel count, the multiplexer logic pins can be controlled via the AD7190 general-purpose output pins. The general-purpose output pins can be used to select the active multiplexer pin. Because the operation of the multiplexer is independent of the AD7190, the AD7190 modulator and filter should be reset using the plexer channel is changed.

rather than by DVDD. When the GPOCON

SYNC

pin each time that the multi-

ENABLE PARITY

The AD7190 also has a parity check function on-chip that detects 1-bit errors in the serial communications between the ADC and the microprocessor. When the ENPAR bit in the mode register is set to 1, parity is enabled. The contents of the status register must be transmitted along with each 24-bit conversion when the parity function is enabled. To append the contents of the status register to each conversion read, the DAT_STA bit in the mode register should be set to 1. For each conversion read, the parity bit in the status register is programmed so that the overall number of 1s transmitted in the 24-bit data-word is even. Therefore, for example, if the 24-bit conversion contains eleven 1s (binary format), the parity bit is set to 1 so that the total number of 1s in the serial transmission is even. If the microprocessor receives an odd number of 1s, it knows that the data received has been corrupted.

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AD7190

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The parity function only detects 1-bit errors. For example, two bits of corrupt data can result in the microprocessor receiving an even number of 1s. Therefore, an error condition is not detected.

CALIBRATION

The AD7190 provides four calibration modes that can be programmed via the mode bits in the mode register. These modes are internal zero-scale calibration, internal full-scale calibration, system zero-scale calibration, and system full-scale calibration. A calibration can be performed at any time by setting the MD2 to MD0 bits in the mode register appropriately. A calibration should be performed when the gain is changed. After each conversion, the ADC conversion result is scaled using the ADC calibration registers before being written to the data register. The offset calibration coefficient is subtracted from the result prior to multiplication by the full-scale coefficient.

To start a calibration, write the relevant value to the MD2 to MD0 bits. The DOUT/ register go high when the calibration is initiated. When the calibration is complete, the contents of the corresponding calibration registers are updated, the register is reset, the DOUT/ and the AD7190 reverts to idle mode.

During an internal zero-scale or full-scale calibration, the respective zero input and full-scale input are automatically connected internally to the ADC input pins. A system calibration, however, expects the system zero-scale and system full-scale voltages to be applied to the ADC pins before initiating the calibration mode. In this way, external ADC errors are removed.

From an operational point of view, treat a calibration like another ADC conversion. A zero-scale calibration, if required, must always be performed before a full-scale calibration. Set the system software to monitor the

the DOUT/ polling sequence or an interrupt-driven routine.

With chop disabled, both an internal zero-scale calibration and a system zero-scale calibration require a time equal to the settling time, t sinc

With chop enabled, an internal zero-scale calibration is not needed because the ADC itself minimizes the offset continuously. However, if an internal zero-scale calibration is performed, the settling time, t tion. Similarly, a system zero-scale calibration requires a time of t

SETTLE

To perform an internal full-scale calibration, a full-scale input voltage is automatically connected to the selected analog input for this calibration. For a gain of 1, the time required for an internal full-scale calibration is equal to t the internal full-scale calibration requires a time of 2 × t A full-scale calibration is required each time the gain of a channel is changed to minimize the full-scale error.

RDY

filter).

to complete.

SETTLE

SETTLE,

RDY

pin and the

RDY

pin to determine the end of calibration via a

, (4/f

for the sinc4 filter and 3/f

ADC

(2/f

) is required to perform the calibra-

ADC

RDY

bit in the status

RDY

bit in the status

pin returns low (if CS is low),

bit in the status register or

for the

ADC

. For higher gains,

SETTLE

A system full-scale calibration requires a time of t chop disabled, the zero-scale calibration (internal or system zero-scale) should be performed before the system full-scale calibration is initiated.

An internal zero-scale calibration, system zero-scale calibration and system full-scale calibration can be performed at any output data rate. An internal full-scale calibration can be performed at any output data rate for which the filter word FS[9:0] is divisible by 16, FS[9:0] being the decimal equivalent of the 10-bit word written to Bit FS9 to Bit FS0 in the mode register. Therefore, internal full-scale calibrations can be performed at output data rates such as 300 Hz, 150 Hz, and 100 Hz. Using these lower output data rates results in better calibration accuracy.

The gain error of the AD7190 is factory calibrated at a gain of 1 with a 5 V power supply at ambient temperature. Following this calibration, the gain error is 0.001%, typically, at 5 V. The offset error is, typically, 100 µV/gain. If the gain is changed, it is advisable to perform a calibration. A zero-scale calibration (an internal zero-scale calibration or system zero-scale calibration) reduces the offset error to the order of the noise. Tabl e 23 shows the uncalibrated gain error for the different gain settings. An internal full-scale calibration reduces the gain error to 0.001%, typically, when the gain is equal to 1. For higher gains, the gain error post internal full-scale calibration is 0.0075%, typically. A system full-sale calibration reduces the gain error to the order of the noise.

Table 23. Precalibration Gain Error vs. Gain

Gain Precalibration Gain Error (%)

8 −0.11 16 −0.20 32 −0.23 64 −0.29 128 −0.39

The AD7190 gives the user access to the on-chip calibration registers, allowing the microprocessor to read the calibration coefficients of the device and also to write its own calibration coefficients from prestored values in the EEPROM. A read of the registers can be performed at any time. However, the ADC must be placed in power-down or idle mode when writing to the registers. The values in the calibration registers are 24-bits wide. The span and offset of the part can also be manipulated using the registers.

SETTLE

. With

GROUNDING AND LAYOUT

Because the analog inputs and reference inputs are differential, most of the voltages in the analog modulator are commonmode voltages. The high common-mode rejection of the part removes common-mode noise on these inputs. The analog and digital supplies to the AD7190 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The digital filter provides rejection of broadband noise on the power supplies, except at

Rev. 0 | Page 36 of 40

AD7190

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integer multiples of the modulator sampling frequency. Connect an R-C filter to each analog input pin to provide rejection at the modulator sampling frequency. A 100 Ω resistor in series with each analog input (a 0.1 F capacitor from AINx(+) to AINx(−) along with a 0.01 F capacitor from each analog input to AGND) is advised. The digital filter also removes noise from the analog and reference inputs provided these noise sources do not saturate the analog modulator. As a result, the AD7190 is more immune to noise interference than a conventional high resolution converter. However, because the resolution of the AD7190 is so high and the noise levels from the converter so low, care must be taken with regard to grounding and layout.

The printed circuit board (PCB) that houses the ADC must be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes because it gives the best shielding.

Although the AD7190 has separate pins for analog and digital ground, the AGND and DGND pins are tied together internally via the substrate. Therefore, the user must not tie these two pins to separate ground planes unless the ground planes are connected together near the AD7190.

In systems in which the AGND and DGND are connected somewhere else in the system (that is, the power supply of the system), they should not be connected again at the AD7190 because a ground loop results. In these situations, it is recommended that ground pins of the AD7190 be tied to the AGND plane.

In any layout, the user must keep in mind the flow of currents in the system, ensuring that the paths for all currents are as close as possible to the paths the currents took to reach their destinations. Avoid forcing digital currents to flow through the AGND.

Avoid running digital lines under the device because this couples noise onto the die, and allow the analog ground plane to run under the AD7190 to prevent noise coupling. The power supply lines to the AD7190 must use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Shield fast switching signals like clocks with digital ground to prevent radiating noise to other sections of the board, and never run clock signals near the analog inputs. Avoid crossover of digital and analog signals. Run traces on opposite sides of the board at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, whereas signals are placed on the solder side.

Good decoupling is important when using high resolution ADCs. Decouple all analog supplies with 10 F tantalum in parallel with

0.1 F capacitors to AGND. To achieve the best from these decoupling components, place them as close as possible to the device, ideally right up against the device. Decouple all logic chips with 0.1 F ceramic capacitors to DGND. In systems in which a common supply voltage is used to drive both the AV of the AD7190, it is recommended that the system AVDD supply be used. For this supply, place the recommended analog supply decoupling capacitors between the AV and AGND and the recommended digital supply decoupling capacitor between the DV

DD pin of the AD7190 and DGND.

DD pin of the AD7190

DD and DVDD

Rev. 0 | Page 37 of 40

AD7190

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APPLICATIONS INFORMATION

The AD7190 provides a low-cost, high resolution analog-todigital function. Because the analog-to-digital function is provided by a ∑-∆ architecture, it makes the part more immune to noisy environments, making it ideal for use in sensor measurement and industrial and process control applications.

WEIGH SCALES

Figure 32 shows the AD7190 being used in a weigh scale application. The load cell is arranged in a bridge network and gives a differential output voltage between its OUT+ and OUT– terminals. Assuming a 5 V excitation voltage, the full-scale output range from the transducer is 10 mV when the sensitivity is 2 mV/V. The excitation voltage for the bridge can be used to directly provide the reference for the ADC because the reference input range includes the supply voltage.

A second advantage of using the AD7190 in transducer-based applications is that the bridge power-down switch can be fully utilized to minimize the power consumption of the system. The

bridge power-down switch is connected in series with the cold side of the bridge. In normal operation, the switch is closed and measurements can be taken. In applications in which current consumption is being minimized, the AD7190 can be placed in standby mode, thus significantly reducing the power consumed in the application. In addition, the bridge power-down switch can be opened while in standby mode, thus avoiding unnecessary power consumption by the front-end transducer. When the part is taken out of standby mode and the bridge power-down switch is closed, the user should ensure that the front-end circuitry is fully settled before attempting a read from the AD7190.

For simplicity, external filters are not included in Figure 32. However, an R-C antialias filter should be included on each analog input. This is required because the on-chip digital filter does not provide any rejection around the modulator sampling frequency or multiples of this frequency. Suitable values are a 100  resistor in series with each analog input, a 0.1 F capacitor from AINx(+) to AINx(−), and 0.01 F capacitors from AINx(+)/AINx(−) to AGND.

Σ-Δ

ADC

DGND

REFERENCE

DETECT

SERIAL

INTERFACE

AND

CONTROL

LOGIC

DOUT/RDY

DIN

SCLK

SYNC

7640-024

OUT–

IN+

IN–

OUT+

REFIN1(+)

AIN1 AIN2 AIN3 AIN4 AINCOM

REFIN1(–)

BPDSW

AGND

MUX

Figure 32. Typical Application (Weigh Scale)

AGND

AD7190

PGA

TEMP

SENSOR

CLOCK

CIRCUITRY

MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+)

Rev. 0 | Page 38 of 40

AD7190

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OUTLINE DIMENSIONS

7.90

7.80

7.70

PIN 1

0.15

0.05

0.10 COPLANARITY

0.65

BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AD

121

1.20

MAX

SEATING PLANE

4.50

4.40

4.30

6.40 BSC

0.20

0.09

8° 0°

0.75

0.60

0.45

Figure 33. 24-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-24)

Dimensions shown in millimeters

ORDERING GUIDE

Models Temperature Range Package Description Package Option

AD7190BRUZ AD7190BRUZ-REEL

Z = RoHS Compliant Part.

–40°C to +105°C 24-Lead TSSOP RU-24

Rev. 0 | Page 39 of 40

AD7190

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NOTES

Rev. 0 | Page 40 of 40

ANALOG DEVICES AD7190 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING CHARACTERISTICS

CIRCUIT AND TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

RMS NOISE AND RESOLUTION

SINC4 CHOP DISABLED

SINC3 CHOP DISABLED

SINC4 CHOP ENABLED

SINC3 CHOP ENABLED

ON-CHIP REGISTERS

COMMUNICATIONS REGISTER

STATUS REGISTER

MODE REGISTER

CONFIGURATION REGISTER

DATA REGISTER

GPOCON REGISTER

OFFSET REGISTER

FULL-SCALE REGISTER

ADC CIRCUIT INFORMATION

OVERVIEW

FILTER, OUTPUT DATA RATE, SETTLING TIME

Chop Disabled

Chop Enabled

50 Hz/60 Hz Rejection

Channel Sequencer

Zero Latency

DIGITAL INTERFACE

Single Conversion Mode

Continuous Conversion Mode

Continuous Read

CIRCUIT DESCRIPTION

ANALOG INPUT CHANNEL

BIPOLAR/UNIPOLAR CONFIGURATION

DATA OUTPUT CODING

CLOCK

BURNOUT CURRENTS

REFERENCE

REFERENCE DETECT

RESET

SYSTEM SYNCHRONIZATION

TEMPERATURE SENSOR

BRIDGE POWER-DOWN SWITCH

LOGIC OUTPUTS

ENABLE PARITY

CALIBRATION

GROUNDING AND LAYOUT

APPLICATIONS INFORMATION

WEIGH SCALES

OUTLINE DIMENSIONS

ORDERING GUIDE