ANALOG DEVICES AD7156 Service Manual

Ultralow Power, 1.8 V, 3 mm × 3 mm,

V

www.BDTIC.com/ADI

FEATURES

Ultralow power

Power supply voltage: 1.8 V to 3.6 V
Operation power supply current: 70 μA typical
Power-down current: 2 μA typical

Fast response time

Conversion time: 10 ms per channel

Wake-up time from serial interface: 300 μs
Adaptive environmental compensation
2 capacitance input channels

Sensor capacitance (C

Sensitivity up to 3 fF
2 modes of operation

Standalone with fixed settings

Interfaced to a microcontroller for user-defined settings
2 detection output flags
2-wire serial interface (I
Operating temperature: −40°C to +85°C
10-lead LFCSP package (3 mm × 3 mm × 0.8 mm)

APPLICATIONS

Buttons and switches
Proximity sensing
Contactless switching
Position detection
Level detection
Portable products

): 0 pF up to 13 pF

SENS

2

C-compatible)

2-Channel Capacitance Converter

AD7156

GENERAL DESCRIPTION

The AD7156 delivers a complete signal processing solution for
capacitive sensors, featuring an ultralow power converter with
fast response time.

The AD7156 uses an Analog Devices, Inc., capacitance-to­digital converter (CDC) technology, which combines features
important for interfacing to real sensors, such as high input
sensitivity and high tolerance of both input parasitic ground
capacitance and leakage current.

The integrated adaptive threshold algorithm compensates for
any variations in the sensor capacitance due to environmental
factors like humidity and temperature or due to changes in the
dielectric material over time.

By default, the AD7156 operates in standalone mode using the
fixed power-up settings and indicates detection on two digital
outputs. Alternatively, the AD7156 can be interfaced to a micro­controller via the serial interface, the internal registers can be
programmed with user-defined settings, and the data and status
can be read from the part.

The AD7156 operates with a 1.8 V to 3.6 V power supply. It is
specified over the temperature range of −40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

C

SENS1

C

SENS2

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of p atents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

CIN1

EXC1

CIN2

EXC2

MUX

- CDC

AD7156

EXCITATION

DD

DIGITAL

FILTER

THRESHOLD

THRESHOLD

GND

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

SERIAL

INTERFACE

SCL

SDA

OUT1

OUT2

7726-001

AD7156

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Specifications .................................................................. 5

Absolute Maximum Ratings ............................................................ 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 11

Capacitance-to-Digital Converter ............................................ 11

CAPDAC ..................................................................................... 11

Comparator and Threshold Modes .......................................... 12

Adaptive Threshold .................................................................... 12

Sensitivity..................................................................................... 12

Data Average ............................................................................... 13

Hysteresis ..................................................................................... 13

Timeout ........................................................................................ 13

Auto-DAC Adjustment .............................................................. 14

Power-Down Timer ................................................................... 14

Register Descriptions ..................................................................... 15

Status Register ............................................................................. 16

Data Registers ............................................................................. 17

Average Registers ........................................................................ 18

Fixed Threshold Registers ......................................................... 18

Sensitivity Registers ................................................................... 18

Timeout Registers ....................................................................... 18

Setup Registers ............................................................................ 19

Configuration Register .............................................................. 20

Power-Down Timer Register .................................................... 21

CAPDAC Registers .................................................................... 21

Serial Number Register .............................................................. 21

Chip ID Register ......................................................................... 21

Serial Interface ................................................................................ 22

Read Operation........................................................................... 22

Write Operation.......................................................................... 22

AD7156 Reset ............................................................................. 23

General Call ................................................................................ 23

Hardware Design Considerations ................................................ 24

Overview ..................................................................................... 24

Parasitic Capacitance to Ground .............................................. 24

Parasitic Resistance to Ground ................................................. 24

Parasitic Parallel Resistance ...................................................... 24

Parasitic Serial Resistance ......................................................... 25

Input Overvoltage Protection ................................................... 25

Input EMC Protection ............................................................... 25

Power Supply Decoupling and Filtering .................................. 25

Application Examples ................................................................ 26

Outline Dimensions ....................................................................... 27

Ordering Guide .......................................................................... 27

REVISION HISTORY

10/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 28

AD7156

www.BDTIC.com/ADI

SPECIFICATIONS

VDD = 1.8 V to 3.6 V, GND = 0 V, temperature range = −40°C to +85°C, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit

CAPACITIVE INPUT

2, 3

Conversion Input Range, CIN to EXC

3.2 4 pF 4 pF input range

1.6 2 pF 2 pF input range

0.8 1 pF 1 pF input range

0.4 0.5 pF 0.5 pF input range

Resolution

4, 5

2.0 fF 4 pF input range

1.6 fF 2 pF input range

1.4 fF 1 pF input range

1.0 fF 0.5 pF input range

4, 6

Maximum Allowed Capacitance, CIN to GND

Minimum Allowed Resistance, CIN to GND

Maximum Allowed Serial Resistance

4, 6

50 kΩ See Figure 14

4, 6

50 pF

10 MΩ See Figure 10 and Figure 11

Gain Error −20 +20 %

Gain Deviation over Temperature

Gain Matching Between Ranges

Offset Error

4

50 fF CIN and EXC pins disconnected

Offset Deviation over Temperature

Integral Nonlinearity (INL)

Channel-to-Channel Isolation

Power Supply Rejection

4

4 fF/V

4

0.5 %FSR See Figure 17

4

−2 +2 %

4

4

0.05 %

4

60 dB

5 fF

CAPDAC

Full Range 10 12.5 pF

Resolution (LSB)

Differential Nonlinearity (DNL)

Auto-DAC Increment/Decrement

4

200 fF

4

0.25 LSB

4, 7

25 75 % of C

EXCITATION

4, 7

Voltage

±VDD/2 V

Frequency 16 kHz See Figure 18

4, 6

Maximum Allowed Capacitance EXC to GND

Minimum Allowed Resistance EXC to GND

4, 6

1 MΩ See Figure 12 and Figure 13

1000 pF

LOGIC OUTPUTS (OUT1, OUT2)

Output Low Voltage (VOL) 0.4 V I

Output High Voltage (VOH) VDD – 0.6 V I
SERIAL INTERFACE INPUTS (SCL, SDA)

Input High Voltage (VIH) 70 % of VDD

Input Low Voltage (VIL) 25 % of VDD

Input Leakage Current ±0.1 ±5 µA

Input Pin Capacitance 6 pF
OPEN-DRAIN OUTPUT (SDA)

Output Low Voltage (VOL) 0.4 V

Output High Leakage Current (IOH) 0.1 5 µA V

1

range

IN

Test Conditions/Comments

See Figure 4, Figure 5, and
Figure 6

CIN and EXC pins disconnected
See Figure 16

See Figure 7, Figure 8, and

= −3 mA

SINK

= +3 mA

SOURCE

= −6.0 mA

SINK

= VDD

OUT

Figure 9

I

Rev. 0 | Page 3 of 28

AD7156

www.BDTIC.com/ADI

Parameter Min Typ Max Unit

1

Test Conditions/Comments

POWER REQUIREMENTS

VDD-to-GND Voltage 1.8 3.6 V
IDD Current

4, 8

65 75 µA V

≤ 2.7 V, see Figure 20

DD

70 85 µA VDD = 3.6 V, see Figure 20
IDD Current Power-Down Mode

4, 8

2 10 µA V

≤ 2.7 V, see Figure 21

DD

2 17 µA VDD = 3.6 V, see Figure 21

1

Capacitance units: 1 pF = 1 × 10

2

The CAPDAC can be used to shift (offset) the input range. The total capacitance of the sensor can therefore be up to the sum of the CAPDAC value and the conversion

input range. With the auto-DAC feature, the CAPDAC is adjusted automatically when the CDC input value is lower than 25% or higher than 75% of the CDC nominal
input range.

3

The maximum capacitance of the sensor connected between the EXCx and CINx pins is equal to the sum of the minimum guaranteed value of the CAPDAC and the

minimum guaranteed input range.

4

The maximum specification is not production tested but is supported by characterization data at initial product release.

5

The resolution of the converter is not limited by the output data format or output data LSB (least significant bit) size, but by the converter and system noise level. The

noise-free resolution is defined as level of peak-to-peak noise coming from the converter itself, with no connection to the CIN and EXC pins.

6

These specifications are understood separately. Any combination of the capacitance to ground and serial resistance may result in additional errors, for example gain

error, gain drift, offset error, offset drift, and power supply rejection.

7

Specification is not production tested but is guaranteed by design.

8

Digital inputs equal to VDD or GND.

−12

F; 1 fF = 10

−15

F.

Rev. 0 | Page 4 of 28

AD7156

www.BDTIC.com/ADI

TIMING SPECIFICATIONS

VDD = 1.8 V to 3.6 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = VDD, temperature range = −40°C to +85°C, unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

CONVERTER

Conversion Time

Wake-Up Time from Power-Down Mode

Power-Up Time

Reset Time
SERIAL INTERFACE

SCL Frequency 0 400 kHz

SCL High Pulse Width, t

SCL Low Pulse Width, t

SCL, SDA Rise Time, tR 0.3 µs

SCL, SDA Fall Time, t

Hold Time (Start Condition), t

Setup Time (Start Condition), t

Data Setup Time, t

Setup Time (Stop Condition), t

Data Hold Time (Master), t

Bus-Free Time (Between Stop and Start Conditions), t

1

Conversion time is 304 internal clock cycles for both channels (nominal clock 16 kHz); the internal clock frequency is equal to the specified excitation frequency.

2

Specification is not production tested but is supported by characterization data at initial product release.

3

Wake-up time is the maximum delay between the last SCL edge writing the configuration register and the start of conversion.

4

Power-up time is the maximum delay between the VDD crossing the minimum level (1.8 V) and either the start of conversion or when ready to receive a serial

interface command.

5

Reset time is the maximum delay between the last SCL edge writing the reset command and either the start of conversion or when ready to receive a serial

interface command.

6

Sample tested during initial release to ensure compliance.

7

All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.

Output load = 10 pF.

1

2, 3

2, 4

2 ms

2, 5

6, 7

0.6 µs

HIGH

1.3 µs

LOW

F

0.6 µs After this period, the first clock is generated.

HD;STA

SU;STA

0.1 µs

SU;DAT

SU;STO

10 ns

HD;DAT

t

LOW

0.3 ms

0.6 µs Relevant for repeated start condition.

0.6 µs

t

R

20 ms Both channels, 10 ms per channel.

2 ms
See Figure 2.

0.3 µs

1.3 µs

BUF

t

F

t

HD;STA

SCL

SDA

t

t

BUF

PS

HD;STA

t

HD;DAT

t

HIGH

t

SU;DAT

t

SU;STA

S

Figure 2. Serial Interface Timing Diagram

Rev. 0 | Page 5 of 28

t

SU;STO

P

07726-002

AD7156

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

Positive Supply Voltage VDD to GND

Voltage on Any Input or Output to GND –0.3 V to VDD + 0.3 V
ESD Rating

ESD Association Human Body Model, S5.1

Field-Inducted Charged Device Model
Operating Temperature Range −40°C to +85°C
Storage Temperature Range –65°C to +150°C
Maximum Junction Temperature 150°C
LFCSP Package

θJA, Thermal Impedance to Air

θJC, Thermal Impedance to Case

Reflow Soldering (Pb-Free)

Peak Temperature 260(0/−5)°C

Time at Peak Temperature 10 sec to 40 sec

−0.3 V to +3.9 V

4 kV
500 V

49°C/W
3°C/W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 6 of 28

AD7156

www.BDTIC.com/ADI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

GND

VDD

2

CIN2

CIN1

EXC2

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO
GND OR IT MUST BE ISOLATED (FLOATING).

AD7156

3

TOP VIEW

(Not to Scale)

4

5

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 GND Ground Pin.
2 VDD

Power Supply Voltage. This pin should be decoupled to GND using a low impedance capacitor, such as a

0.1 F X7R multilayer ceramic capacitor.

3 CIN2

CDC Capacitive Input Channel 2. The measured capacitance (sensor) is connected between the EXC2 pin and
the CIN2 pin. If not used, this pin can be left open circuit or be connected to GND. When a conversion is
performed on Channel 2, the CIN2 pin is internally connected to a high impedance input of the Σ-∆
modulator. When a conversion is performed on the other channel or in idle mode or power-down mode,

the CIN2 pin is internally disconnected and left floating by the part.

4 CIN1

CDC Capacitive Input Channel 1. The measured capacitance (sensor) is connected between the EXC1 pin and
the CIN1 pin. If not used, this pin can be left open circuit or be connected to GND. When a conversion is
performed on Channel 1, the CIN1 pin is internally connected to a high impedance input of the Σ-∆
modulator. When a conversion is performed on the other channel or in idle mode or power-down mode,

the CIN1 pin is internally disconnected and left floating by the part.

5 EXC2

CDC Excitation Output Channel 2. The measured capacitance is connected between the EXC2 pin and the
CIN2 pin. If not used, this pin should be left as an open circuit. When a conversion is performed on Channel 2,
the EXC2 pin is internally connected to the output of the excitation signal driver. When a conversion is per­formed on the other channel or in idle mode or power-

to GND.

6 EXC1

CDC Excitation Output Channel 1. The measured capacitance is connected between the EXC1 pin and the
CIN1 pin. If not used, this pin should be left as an open circuit. When a conversion is performed on Channel 1,
the EXC1 pin is internally connected to the output of the excitation signal driver. When a conversion is per­formed on the other channel or in idle mode or power-

to GND.

7 OUT1 Logic Output Channel 1. A high level on this output indicates proximity detected on CIN1.
8 OUT2 Logic Output Channel 2. A high level on this output indicates proximity detected on CIN2.
9 SCL

Serial Interface Clock Input. This pin connects to the master clock line and requires a pull-up resistor if not
provided elsewhere in the system.

10 SDA

Serial Interface Bidirectional Data. This pin connects to the master data line and requires a pull-up resistor if
not provided elsewhere in the system.

10

SDA

SCL

9

OUT2

8

7

OUT1

EXC1

6

07726-003

down mode, the EXC2 pin is internally connected

down mode, the EXC1 pin is internally connected

Rev. 0 | Page 7 of 28

AD7156

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

2.0

1.8

1.6

1.4

1.2

1.0

0.8

OFFSET ERROR (pF)

0.6

0.4

0.2

0

0 50 100 150 200 250 300

CAPACITANCE CIN T O GROUND (pF )

1.8V

3.3V

Figure 4. Capacitance Input Offset Error vs. Capacitance CIN to GND,

= 1.8 V and 3.3 V, EXC Pin Open Circuit

V

DD

5

0

–5

–10

1.8V

–15

GAIN ERROR (%F SR)

–20

3.3V

1

0

–1

–2

OFFSET ERROR (fF)

–3

07726-004

–4

0 500 1000 1500 2000

CAPACITANCE EXC TO GROUND (pF )

3.3V

1.8V

07726-007

Figure 7. Capacitance Input Offset Error vs. Capacitance EXC to GND,

VDD = 1.8 V and 3.3 V, CIN Pin Open Circuit

1

0

–1

–2

GAIN ERROR (%F SR)

–3

3.3V

1.8V

–25

0 50 100 150 200 250 300

CAPACITANCE CIN T O GROUND (pF )

Figure 5. Capacitance Input Gain Error vs. Capacitance CIN to GND,

= 1.8 V and 3.3 V, CIN to EXC = 3 pF

V

DD

5

0

–5

–10

–15

GAIN ERROR (%F SR)

–20

–25

0 50 100 150 200 250 300

1.8V

CAPACITANCE CIN T O GROUND (pF )

3.3V

Figure 6. Capacitance Input Gain Error vs. Capacitance CIN to GND,

= 1.8 V and 3.3 V, CIN to EXC = 9 pF

V

DD

07726-005

07726-006

Rev. 0 | Page 8 of 2

–4

0 500 1000 1500 2000

CAPACITANCE EXC TO GROUND (pF )

Figure 8. Capacitance Input Gain Error vs. Capacitance EXC to GND,

VDD = 1.8 V and 3.3 V, CIN to EXC = 3 pF

1

0

–1

–2

GAIN ERROR (%F SR)

–3

–4

0 500 1000 1500 2000

CAPACITANCE EXC TO GROUND (pF )

3.3V

1.8V

Figure 9. Capacitance Input Gain Error vs. Capacitance EXC to GND,

= 1.8 V and 3.3 V, CIN to EXC = 9 pF

V

DD

8

07726-008

07726-009

AD7156

www.BDTIC.com/ADI

2

0.2

0

3.3V

–2

–4

–6

GAIN ERROR (%F SR)

–8

–10

1 10 100 1k

1.8V

RESISTANCE CIN T O GND (M)

Figure 10. Capacitance Input Gain Error vs. Resistance CIN to GND,

= 1.8 V and 3.3 V, CIN to EXC = 3 pF

V

DD

2

0

3.3V

–2

–4

–6

GAIN ERROR (%F SR)

–8

–10

1 10 100 1k

1.8V

RESISTANCE CI N TO GND (M)

Figure 11. Capacitance Input Gain Error vs. Resistance CIN to GND,

= 1.8 V and 3.3 V, CIN to EXC = 9 pF

V

DD

0

–0.2

–0.4

–0.6

GAIN ERROR (%F SR)

–0.8

07726-010

–1.0

3.3V

1.8V

07726-013

0.1 1 10 100 1k

RESISTANCE EXC TO GROUND (M )

Figure 13. Capacitance Input Gain Error vs. Resistance EXC to GND,

= 1.8 V and 3.3 V, CIN to EXC = 9 pF

V

DD

1

0

–1

–2

–3

–4

GAIN ERROR (%F SR)

–5

1

07726-01

–6

–7

0 20406080100

SERIAL RESI STANCE (k)

1.8V

3.3V

07726-014

Figure 14. Capacitance Input Gain Error vs. Serial Resistance,

= 1.8 V and 3.3 V, CIN to EXC = 3 pF

V

DD

0.2

0

–0.2

–0.4

–0.6

GAIN ERROR (%F SR)

–0.8

–1.0

1.8V

3.3V

0.1 1 10 100 1k

RESISTANCE EXC TO GROUND (M )

Figure 12. Capacitance Input Gain Error vs. Resistance EXC to GND,

= 1.8 V and 3.3 V, CIN to EXC = 3 pF

V

DD

2

07726-01

10

1.8V

0

–10

–20

–30

GAIN ERROR (%F SR)

–40

–50

1 10 100 1k

Figure 15. Capacitance Input Gain Error vs. Parallel Resistance,

= 1.8 V and 3.3 V, CIN to EXC = 3 pF

V

DD

Rev. 0 | Page 9 of 28

3.3V

07726-015

PARELLEL RE SISTANCE (M)