ANALOG DEVICES AD7147A Service Manual

CapTouch Programmable Controller for

A

V

Single-Electrode Capacitance Sensors

FEATURES

Programmable capacitance-to-digital converter (CDC)

Femtofarad (fF) resolution
13 capacitance sensor inputs
9 ms update rate, all 13 sensor inputs
No external RC components required
Automatic conversion sequencer

On-chip automatic calibration logic

Automatic compensation for environmental changes

Automatic adaptive threshold and sensitivity levels
Register map is compatible with the AD714x
On-chip RAM to store calibration data
Serial peripheral interface (SPI) (AD7147A)

2

I

C-compatible serial interface (AD7147A-1)
Separate V
Interrupt output and general-purpose input/output (GPIO)
25-ball, 2.3 mm × 2.1 mm WLCSP

2.6 V to 3.6 V supply voltage
Low operating current

Full power mode: 1 mA
Low power mode: 28.96 µA

level for serial interface

DRIVE

CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8

CIN9
CIN10
CIN

CIN12

DRIVE

AD7147A

FUNCTIONAL BLOCK DIAGRAM

C

SHIELDVCC

E4 D2 E2 E3

D3

A3

B3

A4

C3

A5

B4

B5

C4

C5

D4

D5

11

E5

MATRIX

SWITCH

SERIAL INT E RFACE

AND CONTROL L OGIC

GND BIAS

EXCITATION

SOURCE

AD7147A

16-BIT

-

CDC

CALIBRATION

CALIBRATION

ENGINE

CONTROL

AND DATA

REGISTERS

INTERRUPT

AND GPIO

LOGIC

POWER-ON

RESET LOGIC

RAM

B2

TP

A2C2

GPIO

APPLICATIONS

Cell phones
Personal music and multimedia players
Smart handheld devices
Television, A/V, and remote controls
Gaming consoles
Digital still cameras

GENERAL DESCRIPTION

The AD7147A CapTouch™ controller is designed for use with
capacitance sensors implementing functions such as buttons,
scroll bars, and wheels. The sensors need only one PCB layer,
enabling ultrathin applications.

The AD7147A is an integrated CDC with on-chip environmen­tal calibration. The CDC has 13 inputs channeled through a
switch matrix to a 16-bit, 250 kHz sigma-delta (Σ-∆) converter.
The CDC is capable of sensing changes in the capacitance of the
external sensors and uses this information to register a sensor
activation. By programming the registers, the user has full control
over the CDC setup.

High resolution sensors require minor software to run on the
host processor and may require two PCB layers.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

E1 D1 C1 B1 A1

SDO

SDI

(ADD0)

SCLK CS

(ADD1)

NOTES

1. PIN NAMES IN PARENTHESES ARE FOR THE AD7147A-1.

(SDA)

INT

Figure 1.

The AD7147A is designed for single electrode capacitance
sensors (grounded sensors). There is an active shield output to
minimize noise pickup in the sensor.

The AD7147A has on-chip calibration logic to compensate for
changes in the ambient environment. The calibration sequence
is performed automatically and at continuous intervals as long
as the sensors are not touched. This ensures that there are no
false or nonregistering touches on the external sensors due to a
changing environment.

The AD7147A has an SPI-compatible serial interface, and the
AD7147A-1 has an I

2

C®-compatible serial interface. Both parts
have an interrupt output, as well as a GPIO. There is a V
to set the voltage level for the serial interface independent of V

The AD7147A is available in a 25-ball, 2.3 mm × 2.1 mm
WLCSP and operates from a 2.6 V to 3.6 V supply. The operating
current consumption in low power mode is typically 28.96 A
for 13 sensors.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009 Analog Devices, Inc. All rights reserved.

DRIVE

pin

CC

06663-001

.

AD7147A

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Average Current Specifications .................................................. 4

SPI Timing Specifications (AD7147A) ...................................... 5

I2C Timing Specifications (AD7147A-1) .................................. 6

Absolute Maximum Ratings ............................................................ 7

ESD Caution .................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 11

Capacitance Sensing Theory ..................................................... 11

BIAS Pin ....................................................................................... 12

Operating Modes ........................................................................ 12

Capacitance-to-Digital Converter ................................................ 14

Oversampling the CDC Output ............................................... 14

Capacitance Sensor Offset Control .......................................... 14

Conversion Sequencer ............................................................... 14

CDC Conversion Sequence Time ............................................ 16

CDC Conversion Results ........................................................... 16

Capacitance Sensor Input Configuration .................................... 17

CINx Input Multiplexer Setup .................................................. 17

Single-Ended Connections to the CDC .................................. 17

Noncontact Proximity Detection ................................................. 18

Recalibration ............................................................................... 18

Proximity Sensitivity .................................................................. 18

FF_SKIP_CNT ............................................................................ 21

Environmental Calibration ........................................................... 23

REVISION HISTORY

12/09—Rev. A to Rev. B

Changes to Figure 1 .......................................................................... 1

Changes to Figure 5, Figure 6, and Pin Description for B2 ........ 8

Changes to Figure 59 and Figure 60 ............................................. 39

Changes to Ordering Guide .......................................................... 68

Capacitance Sensor Behavior Without Calibration ............... 23

Threshold Equations .................................................................. 23

Capacitance Sensor Behavior with Calibration ...................... 24

Slow FIFO .................................................................................... 24

SLOW_FILTER _UPDATE_LVL .............................................. 24

Adaptive Threshold and Sensitivity ............................................. 25

Interrupt Output ............................................................................. 27

CDC Conversion-Complete Interrupt .................................... 27

Sensor-Touch Interrupt ............................................................. 27

INT

GPIO

Outputs ............................................................................................ 31

AC

General-Purpose Input/Output (GPIO) ................................. 31

Using the GPIO to Turn On/Off an LED ................................ 31

Serial Interfaces ............................................................................... 32

SPI Interface ................................................................................ 32

I2C-Compatible Interface .......................................................... 34

V

DRIVE

PCB Design Guidelines ................................................................. 37

Capacitive Sensor Board Mechanical Specifications ............. 37

WLCSP Package ......................................................................... 37

Power-Up Sequence ....................................................................... 38

Typical Application Circuits ......................................................... 39

Register Map ................................................................................... 40

Detailed Register Descriptions ..................................................... 41

Bank 1 Registers ......................................................................... 41

Bank 2 Registers ......................................................................... 51

Bank 3 Registers ......................................................................... 56

Outline Dimensions ....................................................................... 68

Ordering Guide .......................................................................... 68

3/09—Rev. 0 to Rev. A

Changes to Ordering Guide .......................................................... 68

1/09—Revision 0: Initial Version

Output Control ....................................................... 29

Output .......................................................................... 31

SHIELD

Input ................................................................................. 36

Rev. B | Page 2 of 68

AD7147A

SPECIFICATIONS

VCC = 2.6 V to 3.6 V, TA = −40oC to +85°C, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

CAPACITANCE-TO-DIGITAL CONVERTER

Update Rate 8.73 9 9.27 ms 12 conversion stages, decimation = 64

17.46 18 18.54 ms 12 conversion stages, decimation = 128

34.9 36 37.1 ms 12 conversion stages, decimation = 256
Resolution 16 Bits
CINx Input Range ±8 pF
No Missing Codes 16 Bits Guaranteed by design, but not production tested
CINx Input Leakage 25 nA
Maximum Output Load 20 pF Capacitance load on CINx to ground
Total Unadjusted Error ±20 %
Output Noise (Peak-to-Peak) 12 Codes Decimation rate = 64
7 Codes Decimation rate = 128
3 Codes Decimation rate = 256
Output Noise (RMS) 1.1 Codes Decimation rate = 64

0.8 Codes Decimation rate = 128

0.5 Codes Decimation rate = 256
C

Offset Range 20 pF

STRAY

C

Offset Resolution 0.32 pF

STRAY

Low Power Mode Delay Accuracy 4 % Percentage of 200 ms, 400 ms, 600 ms, or 800 ms

AC

SHIELD

Frequency 250 kHz
Output Voltage 0 VCC V Oscillating
Short-Circuit Source Current 10 mA
Short-Circuit Sink Current 10 mA
Maximum Output Load 150 pF Capacitance load on AC

LOGIC INPUTS (SDI, SCLK, CS, SDA, GPIO)

Input High Voltage, VIH 0.7 × V

V

DRIVE

Input Low Voltage, VIL 0.4 V
Input High Current, IIH −1 μA VIN = V

DRIVE

Input Low Current, IIL 1 μA VIN = GND
Hysteresis 150 mV

OPEN-DRAIN OUTPUTS (SCLK, SDA,

Output Low Voltage, VOL 0.4 V I
Output High Leakage Current, IOH ±0.1 ±1 μA V

INT

)

= −1 mA

SINK

= V

DRIVE

OUT

LOGIC OUTPUTS (SDO, GPIO)

Output Low Voltage, VOL 0.4 V I
Output High Voltage, VOH V
GPO, SDO Floating State Leakage

− 0.6 V I

DRIVE

±1 μA Pin three-state, leakage measured to GND and VCC

= 1 mA, V

SINK

= 1 mA, V

SOURCE

= 1.65 V to 3.6 V

DRIVE

= 1.65 V to 3.6 V

DRIVE

Current

POWER

VCC 2.6 3.3 3.6 V
V

1.65 3.6 V Serial interface operating voltage

DRIVE

ICC 0.8 1 mA In full power mode, VCC + V

1.1 1.3 mA In full power mode, VCC + V

1.2 1.5 mA In full power mode, VCC + V

1.6 1.8 mA In full power mode, VCC + V

15.5 24 μA Low power mode, converter idle, VCC + V
Register 0x00, Bits[15:14] = 01

2.3 10 μA Full shutdown, VCC + V

to ground

SHIELD

, Register 0x00, Bits[15:14] = 00

DRIVE

, Register 0x00, Bits[15:14] = 01

DRIVE

, Register 0x00, Bits[15:14] = 10

DRIVE

, Register 0x00, Bits[15:14] = 11

DRIVE

, decimation = 256;

DRIVE

, Register 0x00, Bits[15:14] = 01

DRIVE

Rev. B | Page 3 of 68

AD7147A

AVERAGE CURRENT SPECIFICATIONS

Table 2. Typical Average Current in Low Power Mode1

Low Power
Mode Delay

Decimation
Rate

1 2 3 4 5 6 7 8 9 10 11 12

200 ms 64 22.27 26.53 30.77 34.98 39.15 43.29 47.40 51.48 55.53 59.55 63.54 67.51
128 27.95 36.37 44.66 52.84 60.89 68.82 76.64 84.34 91.94 99.42 106.80 114.08
256 39.15 55.53 71.44 86.89 101.9 116.48 130.67 144.47 157.90 170.98 183.71 196.11
400 ms 64 18.89 21.04 23.19 25.32 27.45 29.57 31.68 33.78. 35.88 37.96 40.04 42.11
128 21.76 26.03 30.27 34.48 38.66 42.80 46.92 51.00 55.05 59.08 63.07 67.04
256 27.45 35.88 44.18 52.36 60.41 68.35 76.18 83.89 91.49 98.98 106.37 113.65
600 ms 64 17.76 19.20 20.63 22.06 23.49 24.91 26.33 27.75 29.16 30.57 31.98 33.38
128 19.68 22.54 25.39 28.22 31.04 33.85 36.64 39.42 42.18 44.93 47.67 50.39
256 23.49 29.16 34.78 40.34 45.84 51.29 56.69 62.03 67.32 72.56 77.75 82.89
800 ms 64 17.20 18.28 19.35 20.43 21.50 22.57 23.64 24.71 25.78 26.84 27.90 28.96
128 18.63 20.79 22.93 25.07 27.20 29.32 31.43 33.53 35.63 37.72 39.80 41.87
256 21.50 25.78 30.02 34.23 38.41 42.56 46.67 50.76 54.82 58.84 62.84 66.80

1

VCC = 3.3 V, TA = 25°C, load = 50 pF.

Table 3. Maximum Average Current in Low Power Mode

Low Power
Mode Delay

Decimation
Rate

1 2 3 4 5 6 7 8 9 10 11 12

200 ms 64 32.62 38.12 43.58 48.99 54.35 59.67 64.95 70.18 75.37 80.52 85.63 90.69
128 39.95 50.78 61.44 71.92 82.23 92.37 102.36 112.18 121.85 131.27 140.74 149.97
256 54.35 75.37 95.72 115.42 134.51 153.02 170.96 188.38 205.28 221.70 237.65 253.15
400 ms 64 28.32 31.10 33.86 36.61 39.35 42.08 44.80 47.50 50.19 52.88 55.55 58.21
128 32.02 37.53 42.99 48.40 53.77 59.09 64.38 69.61 74.81 79.96 85.07 90.14
256 39.35 50.19 60.86 71.35 81.67 91.82 101.82 111.65 121.33 130.86 140.24 149.47
600 ms 64 26.88 28.74 30.59 32.43 34.27 36.11 37.94 39.76 41.58 43.39 45.20 47.00
128 29.36 33.05 36.72 40.37 44.00 47.60 51.19 54.76 58.31 61.84 65.35 68.84
256 34.27 41.58 48.80 55.95 63.01 70.00 76.92 83.76 90.52 97.21 103.83 110.39
800 ms 64 26.16 27.56 28.95 30.33 31.72 33.10 34.48 35.85 37.23 38.60 39.96 41.33
128 28.02 30.80 33.56 36.31 39.05 41.78 44.50 47.21 49.90 52.59 55.26 57.92
256 31.72 37.23 42.69 48.11 53.48 58.80 64.09 69.33 74.53 79.68 84.80 89.87

1

VCC = 3.6 V, TA = −40°C to +85°C, load = 50 pF.

Current Values of Conversion Stages (A)

1

Current Values of Conversion Stages (A)

Rev. B | Page 4 of 68

AD7147A

K

SPI TIMING SPECIFICATIONS (AD7147A)

TA = −40°C to +85°C, sample tested at 25°C to ensure compliance. V
noted. All input signals are specified with t

= tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V.

R

Table 4. SPI Timing Specifications

Parameter Limit Unit Description

f

5 MHz max SCLK frequency

SCLK

t1 5 ns min
t2 20 ns min SCLK high pulse width
t3 20 ns min SCLK low pulse width
t4 15 ns min SDI setup time
t5 15 ns min SDI hold time
t6 20 ns max SDO access time after SCLK falling edge
t7 16 ns max
t8 15 ns min

SPI Timing Diagram

CS

t

1

t

SCL

SDI

2

116

t

4

t

5

MSB LSB

t

3

23

= 1.65 V to 3.6 V, and VCC = 2.6 V to 3.6 V, unless otherwise

DRIVE

falling edge to first SCLK falling edge

CS

rising edge to SDO high impedance

CS
SCLK rising edge to CS

15

high

12

t

8

15

16

t

SDO

6

MSB

LSB

t

7

07727-002

Figure 2. SPI Detailed Timing Diagram

Rev. B | Page 5 of 68

AD7147A

I2C TIMING SPECIFICATIONS (AD7147A-1)

TA = −40°C to +85°C, sample tested at 25°C to ensure compliance. V
noted. All input signals timed from a voltage level of 1.6 V.

Table 5. I

2

C Timing Specifications1

Parameter Limit Unit Description

f

400 kHz max

SCLK

t1 0.6 μs min Start condition hold time, t
t2 1.3 μs min Clock low period, t
t3 0.6 μs min Clock high period, t
t4 100 ns min Data setup time, t
t5 300 ns min Data hold time, t
t6 0.6 μs min Stop condition setup time, t
t7 0.6 μs min Start condition setup time, t
t8 1.3 μs min Bus-free time between stop and start conditions, t
tR 300 ns max Clock/data rise time
tF 300 ns max Clock/data fall time

1

Guaranteed by design, not production tested.

I2C Timing Diagram

t

t

2

SCLK

t

1

SDA

t

8

STOP START STOPSTART

R

t

5

t

F

t

3

Figure 3. I

t

4

2

C Detailed Timing Diagram

= 1.65 V to 3.6 V, and VCC = 2.6 V to 3.6 V, unless otherwise

DRIVE

HD; STA

LOW

HIGH

SU; DAT

HD; DAT

SU; STO

SU; STA

BUF

t

1

t

7

t

6

07727-003

TO OUTPUT

PIN

50pF

C

200µA I

L

200µA I

OL

1.6V

OH

07727-004

Figure 4. Load Circuit for Digital Output Timing Specifications

Rev. B | Page 6 of 68

AD7147A

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

VCC to GND −0.3 V to +3.6 V
Analog Input Voltage to GND −0.3 V to VCC + 0.3 V
Digital Input Voltage to GND −0.3 V to V
Digital Output Voltage to GND −0.3 V to V
Input Current to Any Pin Except Supplies1 10 mA
ESD Rating

BIAS and AC
and Air Discharge)

All Other Pins (HBM Contact) 2 kV
Operating Temperature Range −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
WLCSP

Power Dissipation 1 W

θJA Thermal Impedance 65°C/W
IR Reflow Peak Temperature 260°C (± 0.5°C)
Lead Temperature (Soldering, 10 sec) 300°C

1

Transient currents of up to 100 mA do not cause SCR latch-up.

Pins (HBM Contact

SHIELD

8 kV

DRIVE

DRIVE

+ 0.3 V

+ 0.3 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. B | Page 7 of 68

AD7147A

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

BALL A1
INDICATOR

5

3

CIN1

CIN2

CIN4

CIN0

BIAS

4

CIN3

CIN5

CIN6 CIN7

CIN8 CIN9

CIN10 CIN11

CIN12SDO

AC

SHIELD

07727-005

2

1

INT GPIO

A

TP

CS

B

V

SCLK

DRIVE

C

SDI

V

CC

D

GND

E

TOP VIEW

(BALL SIDE DOWN)

NOTES

1. TP DENOTES FACTORY TEST POINT.

Not to Scale

Figure 5. AD7147A Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

AD7147A AD7147A-1 Mnemonic Description

B4 B4 CIN6 Capacitance Sensor Input.
B5 B5 CIN7 Capacitance Sensor Input.
C4 C4 CIN8 Capacitance Sensor Input.
C5 C5 CIN9 Capacitance Sensor Input.
D4 D4 CIN10 Capacitance Sensor Input.
D5 D5 CIN11 Capacitance Sensor Input.
E5 E5 CIN12 Capacitance Sensor Input.
E4 E4 AC

CDC Active Shield Output. Connect to external shield or plane.

SHIELD

E3 E3 BIAS Bias Node for Internal Circuitry. Requires 100 nF capacitor to ground.
E2 E2 GND Ground Reference Point for All Circuitry.
D2 D2 VCC Supply Voltage.
C2 C2 V

Serial Interface Operating Voltage Supply.

DRIVE

E1 N/A SDO SPI Serial Data Output.
N/A E1 SDA I2C Serial Data Input/Output. SDA requires pull-up resistor.
D1 N/A SDI SPI Serial Data Input.
N/A D1 ADD0 I2C Address Bit 0.
C1 C1 SCLK Clock Input for Serial Interface.
B1 N/A

CS

SPI Chip Select Signal.

N/A B1 ADD1 I2C Address Bit 1.
A1 A1

INT

General-Purpose Open-Drain Interrupt Output. Programmable polarity; requires pull-up resistor.

A2 A2 GPIO Programmable General-Purpose Input/Output.
D3 D3 CIN0 Capacitance Sensor Input.
A3 A3 CIN1 Capacitance Sensor Input.
B3 B3 CIN2 Capacitance Sensor Input.
A4 A4 CIN3 Capacitance Sensor Input.
C3 C3 CIN4 Capacitance Sensor Input.
A5 A5 CIN5 Capacitance Sensor Input.
B2 B2 Factory Test Point Only. Tie to ground.

BALL A1
INDICATOR

4

1

INT GPIO

A

ADD1

B

SCLK

C

ADD0

D

E

NOTES

1. TP DENOTES FACTORY TEST POINT.

3

2

CIN1

CIN3

TP

CIN2

CIN6 CIN7

CIN4

CIN0

BIAS

TOP VIEW

CIN8 CIN9

CIN10 CIN11

AC

V

DRIVE

V

CC

GND

(BALL SIDE DOWN)

Not to Scale

SHIELD

CIN5

CIN12SDA

Figure 6. AD7147A-1 Pin Configuration

5

07727-006

Rev. B | Page 8 of 68

AD7147A

TYPICAL PERFORMANCE CHARACTERISTICS

935

70

915

895

875

(µA)

CC

I

855

835

815

795

DECIMATI ON = 128

2.6 3.7

2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6

DECIMATION = 64

V

(V)

CC

DECIMATI ON = 256

Figure 7. Supply Current vs. Supply Voltage

180

160

140

120

100

(A)

CC

80

I

60

40

20

0

2.5 3.7

2.7 2.9 3.1 3.3 3.5

200ms

400ms

600ms

800ms

V

(V)

CC

Figure 8. Low Power Supply Current vs. Supply Voltage,

Decimation Rate = 256

0.12

60

50

40

(A)

CC

I

30

20

10

0

2.5 3.72.7 2.9 3.1 3.3 3.5

07727-007

200ms

400ms

600ms

800ms

V

(V)

CC

07727-010

Figure 10. Low Power Supply Current vs. Supply Voltage,

Decimation Rate = 64

2.5

2.0

1.5

(µA)

CC

I

1.0

0.5

0

2.7

2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
V

(V)

07727-008

CC

07727-011

Figure 11. Shutdown Supply Current vs. Supply Voltage

1150

0.10

0.08

0.06

(mA)

CC

I

0.04

0.02

0

2.5 3.7

2.72.93.13.33.5

200ms

400ms

600ms

800ms

V

(V)

CC

Figure 9. Low Power Supply Current vs. Supply Voltage,

Decimation Rate = 128

07727-009

Rev. B | Page 9 of 68

1100

1050

(µA)

CC

I

1000

950

900

0

100 200 300 400 500

AC

CAPACITIVE LOAD (pF)

SHIELD

Figure 12. Supply Current vs. Capacitive Load on AC

SHIELD

07727-012

AD7147A

58,000

56,000

54,000

52,000

50,000

48,000

CDC CODE (d)

46,000

44,000

42,000

40,000

0

100 200 300 400 500

AC

CAPACITIVE LOAD (pF)

SHIELD

Figure 13. CDC Code vs. Capacitive Load on AC

SHIELD

07727-013

160

140

120

100

CDC NOISE p-p (LSB)

25mV 75mV 125mV 175mV
50mV 100mV 150mV 200mV

80

60

40

20

0

25

50

100

200

400

800

1600

3200

SINE WAVE F RE QUENCY (Hz)

6400

12,800

25,600

51,200

102,400

Figure 16. Power Supply Sine Wave Rejection, VCC = 3.6 V

204,800

409,600

819,200

1,640,000

07727-016

960

940

920

900

880

(µA)

CC

860

I

840

820

800

780

–60 –40 –20 0 20 40 60 80 100 120

3.6V

3.3V

2.6V

TEMPERATURE (°C)

Figure 14. Supply Current vs. Temperature

12

10

8

6

(µA)

CC

I

4

2

3.6V

3.3V

2.6V

120

100

CDC NOISE p-p (LSB)

07727-014

25mV 75mV 125mV 175mV
50mV 100mV 150mV 200mV

80

60

40

20

0

25

50

100

200

400

800

1600

3200

SQUARE WAVE F RE QUENCY (Hz)

6400

12,800

25,600

51,200

102,400

204,800

409,600

819,200

1,640,000

07727-017

Figure 17. Power Supply Square Wave Rejection, VCC = 3.6 V

35

30

25

20

15

10

INPUT CAPACIT ANCE (pF)

5

0

–45 135

–25 –5 15 35 55 75 95 115

TEMPERATURE (°C)

Figure 15. Shutdown Supply Current vs. Temperature

07727-015

0

0 10,000 20,000 30,000 40,000 50,000 60,000

CDC OUTPUT CO DE

Figure 18. CDC Linearity, VCC = 3.3 V

07727-018

Rev. B | Page 10 of 68

AD7147A

THEORY OF OPERATION

The AD7147A and AD7147A-1 are CDCs with on-chip environ­mental compensation. They are intended for use in portable
systems requiring high resolution user input. The internal
circuitry consists of a 16-bit, Σ-∆ converter that can change a
capacitive input signal into a digital value. There are 13 input
pins, CIN0 to CIN12. A switch matrix routes the input signals
to the CDC. The result of each capacitance-to-digital conversion
is stored in on-chip registers. The host subsequently reads the
results over the serial interface. The AD7147A has an SPI interface,
and the AD7147A-1 has an I

2

C interface, ensuring that the parts
are compatible with a wide range of host processors. AD7147A
refers to both the AD7147A and AD7147A-1, unless otherwise
noted, from this point forward in this data sheet.

The AD7147A interfaces with up to 13 external capacitance
sensors. These sensors can be arranged as buttons, scroll bars,
or wheels, or as a combination of sensor types. The external
sensors consist of an electrode on a single- or multiple-layer
PCB that interfaces directly to the AD7147A.

The AD7147A can be set up to implement any set of input
sensors by programming the on-chip registers. The registers
can also be programmed to control features such as averaging,
offsets, and gains for each of the external sensors. There is an
on-chip sequencer that controls how each of the capacitance
inputs is polled.

The AD7147A has on-chip digital logic and 528 words of RAM
that are used for environmental compensation. The effects of
humidity, temperature, and other environmental factors can
affect the operation of capacitance sensors. Transparent to the
user, the AD7147A performs continuous calibration to compen­sate for these effects, allowing the AD7147A to consistently
provide error-free results.

The AD7147A requires a companion algorithm that runs on the
host or another microcontroller to implement high resolution
sensor functions, such as scroll bars or wheels. However, no
companion algorithm is required to implement buttons. Button
sensors are implemented on chip, entirely in digital logic.

The AD7147A can be programmed to operate in either full
power mode or low power automatic wake-up mode. The
automatic wake-up mode is particularly suited for portable
devices that require low power operation to provide the user
with significant power savings and full functionality.

The AD7147A has an interrupt output,
data has been placed into the registers.

INT

, to indicate when new

INT

is used to interrupt the

host on sensor activation. The AD7147A operates from a 2.6 V to

3.6 V supply and is available in a 2.3 mm × 2.1 mm WLCSP.

CAPACITANCE SENSING THEORY

The AD7147A measures capacitance changes from single electrode
sensors. The sensor electrode on the PCB comprises one plate
of a virtual capacitor. The other plate of the capacitor is the user’s
finger, which is grounded with respect to the sensor input.

The AD7147A first outputs an excitation signal to charge the
plate of the capacitor. When the user comes close to the sensor,
the virtual capacitor is formed, with the user acting as the second
capacitor plate.

PLASTIC CO V E R

SENSOR PCB

-

ADC

MUX

AD7147A

Figure 19. Capacitance-Sensing Method

A square wave excitation signal is applied to CINx during
the conversion, and the modulator continuously samples the
charge going through CINx. The output of the modulator is
processed via a digital filter, and the resulting digital data is
stored in the CDC_RESULT_Sx registers for each conversion
stage, at Address 0x00B to Address 0x016.

16-BIT
DATA

EXCITATION
SIGNAL
250kHz

07727-019

Rev. B | Page 11 of 68

AD7147A

A

Registering a Sensor Activation

When a user approaches a sensor, the total capacitance associated
with that sensor changes and is measured by the AD7147A. If
the change causes a set threshold to be exceeded, the AD7147A
interprets this as a sensor activation.

On-chip threshold limits are used to determine when a sensor
activation occurs. Figure 20 shows the change in CDC_RESULT_Sx
when a user activates a sensor. The sensor is deemed to be active
only when the value of CDC_RESULT_Sx is either greater than the
value of STAGEx_HIGH_THRESHOLD or less than the value
of STAGEx_LOW_THRESHOLD.

SENSOR ACTIVE

STAGEx_HIGH_THRESHOLD

CDC_RESULT_Sx

AMBIENT OR
NO-TOUCH VALUE

CDC OUTPUT CODES

SENSOR ACTIVE B

Figure 20. Sensor Activation Thresholds

STAGEx_LOW_THRESHOLD

In Figure 20, two sensor activations are shown. Sensor Active A
occurs when a sensor is connected to the positive input of the
converter. In this case, when a user activates the sensor, there is an
increase in CDC code, and the value of CDC_RESULT_Sx exceeds
that of STAGEx_HIGH_THRESHOLD. Sensor Active B occurs
when the sensor is connected to the negative input of the converter.
In this case, when a user activates the sensor, there is a decrease
in CDC code, and the value of CDC_RESULT_Sx becomes less
than the value of STAGEx_LOW_THRESHOLD.

For each conversion stage, the STAGEx_HIGH_THRESHOLD
and STAGEx_LOW_THRESHOLD registers are in Bank 3.
The values in these registers are updated automatically by the
AD7147A due to its environmental calibration and adaptive
threshold logic.

At power-up, the values in the STAGEx_HIGH_THRESHOLD
and STAGEx_LOW_THRESHOLD registers are the same as those
in the STAGEx_OFFSET_HIGH and STAGEx_OFFSET_LOW
registers in Bank 2. The user must program the STAGEx_OFFSET
_HIGH and STAGEx_OFFSET_LOW registers on device power­up. See the Environmental Calibration section of the data sheet
for more information.

07727-020

Complete Solution for Capacitance Sensing

Analog Devices, Inc., provides a complete solution for capacitance
sensing. The two main elements to the solution are the sensor
PCB and the AD7147A.

If the application requires high resolution sensors such as scroll
bars or wheels, software that runs on the host processor is required.
The memory requirements for the host depend on the sensor
and are typically 10 kB of code and 600 bytes of data memory,
depending on the sensor type.

SENSOR PCB

AD7147A

Figure 21. Three-Part Capacitance Sensing Solution

SPI OR I2C

HOST PROCESSOR

1 MIPS

10kB ROM

600 BYTES RAM

07727-021

Analog Devices supplies the sensor PCB footprint design
libraries to the customer and supplies any necessary software on
an open-source basis.

BIAS PIN

This pin is connected internally to a bias node of the AD7147A.
To ensure correct operation of the AD7147A, connect a 100 nF
capacitor between the BIAS pin and ground. The voltage seen at
the BIAS pin is V

/2.

CC

OPERATING MODES

The AD7147A has three operating modes. Full power mode, where
the device is always fully powered, is suited for applications where
power is not a concern (for example, game consoles that have an
ac power supply). Low power mode, where the part automatically
powers down when no sensor is active, is tailored to provide
significant power savings compared with full power mode and
is suited for mobile applications, where power must be conserved.
In shutdown mode, the part shuts down completely.

The POWER_MODE Bits[1:0] of the power control register
(PWR_CONTROL, Address 0x000) set the operating mode on
the AD7147A. Tabl e 8 shows the POWER_MODE settings for
each operating mode. To put the AD7147A into shutdown
mode, set the POWER_MODE bits to either 01 or 11.

Table 8. POWER_MODE Settings

POWER_MODE Bits Operating Mode

00 Full power mode
01 Shutdown mode
10 Low power mode
11 Shutdown mode

The power-on default setting of the POWER_MODE bits is 00,
full power mode.

Rev. B | Page 12 of 68

AD7147A

Full Power Mode

In full power mode, all sections of the AD7147A remain fully
powered and converting at all times. While a sensor is being
touched, the AD7147A processes the sensor data. If no sensor is
touched, the AD7147A measures the ambient capacitance level
and uses this data for the on-chip compensation routines. In full
power mode, the AD7147A converts at a constant rate. See the
CDC Conversion Sequence Time section for more information.

Low Power Mode

When AD7147A is in low power mode, the POWER_MODE
bits are set to 10 upon device initialization. If the external
sensors are not touched, the AD7147A reduces its conversion
frequency, thereby greatly reducing its power consumption.
The part remains in a reduced power state while the sensors are
not touched. The AD7147A performs a conversion after a delay
defined by the LP_CONV_DELAY bits, and it uses this data to
update the compensation logic and check if the sensors are active.
The LP_CONV_DELAY bits set the delay between conversions
to 200 ms, 400 ms, 600 ms, or 800 ms.

In low power mode, the total current consumption of the
AD7147A is an average of the current used during a conversion
and the current used while the AD7147A is waiting for the next
conversion to begin. For example, when LP_CONV_DELAY

is 400 ms, the AD7147A typically uses 0.85 mA of current for
36 ms and 14 A of current for 400 ms during the conversion
interval. (Note that these conversion timings can be altered
through the register settings. See the CDC Conversion Sequence
Time section for more information.)

The time for the AD7147A to transition from a full power state
to a reduced power state after the user stops touching the external
sensors is configurable. The PWR_DOWN_TIMEOUT bits in
the Ambient Compensation Control 0 register (AMB_COMP_
CTRL0, Address 0x002) control the time delay before the
AD7147A transitions to the reduced power state after the user
stops touching the sensors.

Low Latency from Touch to Response

In low power mode, the AD7147A remains in a low power state
until proximity is detected on any one of the external sensors.
When proximity is detected, the AD7147A begins a conversion
sequence every 36 ms, or 18 ms, or 9 ms to read back data from
the sensors. The latency between first touch and AD7147A
response is greatly reduced compared to the AD7147 because
the part is already in a full power state by the time the user
touches the sensor.

AD7147A SETUP

AND INITIALIZATION

POWER_MODE = 10

USER IN

NO YES

PROXIMITY

TO SENSOR?

CONVERSION SEQUENCE

EVERY LP_CONV_DELAY
UPDATE COMPENSATION

LOGIC DATA PATH

Figure 22. Low Power Mode Operation, AD7147A

CONVERSION SE Q UENCE

EVERY 9ms, 18ms, OR

36ms FOR SENSO R

READBACK

USER IN

YES

PROXIMITY

TO SENSOR?

NO

PROXIMITY TIMER

COUNTDOWN

TIMEOUT

07727-022

Rev. B | Page 13 of 68

AD7147A

CAPACITANCE-TO-DIGITAL CONVERTER

The capacitance-to-digital converter on the AD7147A has a
Σ- architecture with 16-bit resolution. There are 13 possible
inputs to the CDC that are connected to the input of the converter
through a switch matrix. The sampling frequency of the CDC is
250 kHz.

OVERSAMPLING THE CDC OUTPUT

The decimation rate, or oversampling ratio, is determined by
Bits[9:8] of the power control register (PWR_CONTROL,
Address 0x000), as listed in Tab l e 9.

Table 9. CDC Decimation Rate

CDC Output Rate

Decimation Bits Decimation Rate

Per Stage (ms)

00 256 3.072
01 128 1.536
10 64 0.768
11 64 0.768

The decimation process on the AD7147A is an averaging
process, where a number of samples are taken and the averaged
result is output. Due to the architecture of the digital filter
employed, the number of samples taken (per stage) is equal to 3×
the decimation rate. So 3 × 256 or 3 × 128 samples are averaged
to obtain each stage result.

The decimation process reduces the amount of noise present in
the final CDC result. However, the higher the decimation rate,
the lower the output rate per stage; therefore, there is a trade-off
possible between the amount of noise in the signal and the
speed of sampling.

CAPACITANCE SENSOR OFFSET CONTROL

There are two programmable DACs on board the AD7147A to null
the effect of any stray capacitances on the CDC measurement.
These offsets are due to stray capacitance to ground.

A simplified block diagram in Figure 23 shows how to apply
the STAGEx_AFE_OFFSET registers to null the offsets. The
POS_AFE_OFFSET and NEG_AFE_OFFSET bits (Bits[13:8] and
Bits[5:0], respectively) program the offset DACs to provide 0.32
pF resolution offset adjustment over a range of 20 pF.

The best practice is to ensure that the CDC output for any stage
is approximately equal to midscale (~32,700) when all sensors
are inactive. To correctly offset the stray capacitance to ground for
each stage, use the following procedure:

1. Read back the CDC value from the CDC_RESULT_Sx

register.

2. If this value is not close to midscale, increase the value of

POS_AFE_OFFSET or NEG_AFE_OFFSET (depending
on if the CINx input is connected to the positive or negative
input of the converter) by 1. The CINx connections are
determined by the STAGEx_CONNECTION registers.

3. If the CDC value in CDC_RESULT_Sx is now closer

to midscale, repeat Step 2. If the CDC value is further

from midscale, decrease the POS_AFE_OFFSET or
NEG_AFE_OFFSET value by 1.

The goal is to ensure that the CDC_RESULT_Sx is as close
to midscale as possible. This process is required only once
during the initial capacitance sensor characterization.

6

POS_AFE_OFFSET

POS_AFE_OFFSET_SWAP BIT

+

16-BIT

CDC

_

NEG_AFE_OFFSET_SWAP BIT

16

6

NEG_AFE_OFFSET

07727-023

CINx

CINx_CONNECTION_SETUP

Figure 23. Analog Front-End Offset Control

+DAC

(20pF RANGE)

–DAC

(20pF RANGE)

CONVERSION SEQUENCER

The AD7147A has an on-chip sequencer to implement conversion
control for the input channels. Up to 12 conversion stages can be
performed in one sequence. Each of the 12 conversions stages can
measure the input from a different sensor. By using the Bank 2
registers, each stage can be uniquely configured to support multiple
capacitance sensor interface requirements. For example, a slider
sensor can be assigned to STAGE1 through STAGE8, with a
button sensor assigned to STAGE0. For each conversion stage,
the input mux that connects the CINx inputs to the converter
can have a unique setting.

The AD7147A on-chip sequence controller provides conversion
control, beginning with STAGE0. Figure 24 shows a block diagram
of the CDC conversion stages and CINx inputs. A conversion
sequence is defined as a sequence of CDC conversions starting
at STAGE0 and ending at the stage determined by the value
programmed in the SEQUENCE_STAGE_NUM bits (Bits[7:4],
Address 0x00). Depending on the number and type of capacitance
sensors that are used, not all conversion stages are required. Use
the SEQUENCE_STAGE_NUM bits to set the number of conver­sions in one sequence. This number depends on the sensor
interface requirements. For example, the register should be set
to 5 if the CINx inputs are mapped to only six conversion stages.
In addition, the STAGE_CAL_EN register (Address 0x001)
should be set according to the number of stages that are used.

The number of required conversion stages depends solely on
the number of sensors attached to the AD7147A. Figure 25
shows how many conversion stages are required for each sensor
and how many inputs to the AD7147A each sensor requires.

Rev. B | Page 14 of 68

AD7147A

A button sensor generally requires one sequencer stage; this is
shown in Figure 25 as B1. However, it is possible to configure
two button sensors to operate differentially for one conversion
stage. Only one button can be activated at a time; pressing both
buttons simultaneously results in neither button being activated.
The configuration with two button sensors operating differen­tially requires one conversion stage and is shown in Figure 25,
with B2 and B3 representing the differentially configured button
sensors.

STAGE3

STAGE2

STAGE1

STAGE0

CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8

CIN9
CIN10
CIN11
CIN12

SWITCH MATRIX

Figure 24. CDC Conversion Stages

STAGE6

STAGE5

STAGE4

16-BIT

A wheel sensor requires eight stages, whereas a slider requires
two stages. The result from each stage is used by the host soft­ware to determine the user’s position on the slider or wheel. The
algorithms that perform this process are available from Analog
Devices and are free of charge but require signing a software
license.

STAGE11

STAGE10

STAGE9

STAGE8

STAGE7

E

C

N

E

-

ADC

U

Q

E

S

N

O

I

S

R

E

V

N

O

C

07727-024

SCROLL

WHEEL

AD7147A

SEQUENCER

STAGE0

+

CDC

–

STAGE1

+

CDC

–

STAGE2

+

CDC

–

STAGE3

+

CDC

–

STAGE4

+

CDC

–

STAGE5

+

CDC

–

STAGE6

+

CDC

–

STAGE7

+

CDC

–

BUTTONS

B1

B2

B3

SLIDER

AD7147A

SEQUENCER

STAGE8

+

CDC

–

STAGE9

+

CDC

–

AD7147A

SEQUENCER

STAGE10

+

CDC

–

STAGE11

+

CDC

–

07727-025

Figure 25. Sequencer Setup for Sensors

Rev. B | Page 15 of 68

AD7147A

C

CDC CONVERSION SEQUENCE TIME

Table 10. CDC Conversion Times for Full Power Mode

Conversion Time (ms)

SEQUENCE_STAGE_NUM

0 0.768 1.536 3.072
1 1.536 3.072 6.144
2 2.304 4.608
3 3.072 6.144
4 3.84 7.68
5 4.608 9.216
6 5.376 10.752
7 6.144 12.288
8 6.912 13.824
9 7.68 15.36
10 8.448 16.896
11 9.216 18.432 36.864

The time required for the CDC to complete the measurement of
all 12 stages is defined as the CDC conversion sequence time. The
SEQUENCE_STAGE_NUM and DECIMATION bits determine
the conversion time, as listed in Tab le 1 0.

For example, if the device is operated with a decimation rate
of 128 and the SEQUENCE_STAGE_NUM bit is set to 5 for the
conversion of six stages in a sequence, the conversion sequence
time is 9.216 ms.

Full Power Mode CDC Conversion Sequence Time

The full power mode CDC conversion sequence time for all
12 stages is set by configuring the SEQUENCE_STAGE_NUM
and DECIMATION bits as outlined in Tabl e 10 .

Figure 26 shows a simplified timing diagram of the full power
mode CDC conversion time. The full power mode CDC con­version time (t

CDC

ONVERSION

Figure 26. Full Power Mode CDC Conversion Sequence Time

) is set using the values shown in Tabl e 10 .

CONV_FP

t

CONV_FP

CONVERSION

SEQUENCE N

Low Power Mode CDC Conversion Sequence Time with Delay

The frequency of each CDC conversion while operating in the
low power automatic wake-up mode is controlled by using the
LP_CONV_DELAY Bits[3:2] located at Address 0x000 in addi­tion to the registers listed in Tab le 10 . This feature provides some
flexibility for optimizing the trade-off between the conversion time
needed to meet system requirements and the power consumption
of the AD7147A.

Decimation = 64 Decimation = 128 Decimation = 256

9.216

12.288

15.36

18.432

21.504

24.576

27.648

30.72

33.792

For example, maximum power savings is achieved when the
LP_CONV_DELAY bits are set to 11. With a setting of 11,
the AD7147A automatically wakes up, performing a conversion
every 800 ms.

Table 11. LP_CONV_DELAY Settings

LP_CONV_DELAY Bits Delay Between Conversions (ms)

00 200
01 400
10 600
11 800

Figure 27 shows a simplified timing example of the low power
mode CDC conversion time. As shown, the low power mode CDC

and the LP_CONV_DELAY bits.

CONV_FP

t

CONV_LP

LP_CONV_DELAY

CONVERSION

SEQUENCE N + 1

CONVERSION

SEQUENCE N + 1

CONVERSION

SEQUENCE N + 2

conversion time is set by t

t

CONV_FP

CDC

CONVERSION

07727-026

CONVERSION

SEQUENCE N

Figure 27. Low Power Mode CDC Conversion Sequence Time

CDC CONVERSION RESULTS

Certain high resolution sensors require the host to read back the
CDC conversion results for processing. The registers required
for host processing are located in Bank 3. The host processes the
data read back from these registers using a software algorithm to
determine position information.

In addition to the results registers in Bank 3, the AD7147A
provides the 16-bit CDC output data directly, starting at
Address 0x00B of Bank 1. Reading back the CDC 16-bit
conversion data register allows for customer-specific application
data processing.

7727-027

Rev. B | Page 16 of 68

AD7147A

CAPACITANCE SENSOR INPUT CONFIGURATION

Each input connection from the external capacitance sensors to
the converter of the AD7147A can be uniquely configured by
using the stage configuration registers in Bank 2 (see Ta b le 39).
These registers are used to configure the input pin connection
setups, sensor offsets, sensor sensitivities, and sensor limits
for each stage. Each sensor can be individually optimized. For
example, a button sensor connected to STAGE0 can have differ­ent sensitivity and offset values than a button with another
function that is connected to a different stage.

CINx INPUT MULTIPLEXER SETUP

Tabl e 35 and Ta bl e 36 list the available options for the CINx_
CONNECTION_SETUP bits when the sensor input pins are
connected to the CDC.

The AD7147A has an on-chip multiplexer that routes the input
signals from each CINx pin to the input of the converter. Each
input pin can be tied to either the negative or positive input of
the CDC, or it can be left floating. Each input can also be
internally connected to the BIAS signal to help prevent cross­coupling. If an input is not used, always connect it to BIAS.

Connecting a CINx input pin to the positive CDC input results
in an increase in CDC output code when the corresponding
sensor is activated. Connecting a CINx input pin to the negative
CDC input results in a decrease in CDC output code when the
corresponding sensor is activated.

The AD7147A performs a sequence of 12 conversions. The multi­plexer can have different settings for each of the 12 conversions.
For example, CIN0 is connected to the negative CDC input for
conversion STAGE1, left floating for conversion STAGE1, and
so on, for all 12 conversion stages.

For each CINx input for each conversion stage, two bits control
how the input is connected to the converter, as shown in Figure 28.

Examples

To connect CIN3 to the positive CDC input on Stage 0, use the
following setting:

STAGE0_CONNECTION[6:0] = 0xFFBF
STAGE0_CONNECTION[12:7] = 0x2FFF

To connect CIN0 to the positive CDC input and CIN12 to the
negative CIN input on STAGE5, use the following settings:

STAGE5_CONNECTION[6:0] = 0xFFFE
STAGE5_CONNECTION[12:7] = 0x37FF

SINGLE-ENDED CONNECTIONS TO THE CDC

A single-ended connection to the CDC is defined as one CINx
input connected to either the positive or negative CDC input
for one conversion stage. A differential connection to the CDC is
defined as one CINx input connected to the positive CDC input
and a second CINx input connected to the negative input of the
CDC for one conversion stage.

For any stage, if a single-ended connection to the CDC is made
in that stage, the SE_CONNECTION_SETUP Bits[13:12] in the
STAGEx_CONNECTION[12:7] register should be applied as
described in Tab l e 1 2.

Table 12. SE_CONNECTION_SETUP Bits

SE_CONNECTION_SETUP Description

00 Do not use.
01

10

11

The SE_CONNECTION_SETUP Bits[13:12] ensure that during a
single-ended connection to the CDC, the input paths to both
CDC terminals are matched, which, in turn, improves the
power-supply rejection of the converter measurement.

These bits should be applied in addition to setting the other bits
in the STAGEx_CONNECTION registers, as outlined in the
CINX Input Multiplexer Setup section.

If more than one CINx input is connected to either the positive
or negative input of the converter for the same conversion, set
SE_CONNECTION_SETUP to 11. For example, if CIN0 and
CIN3 are connected to the positive input of the CDC, set
SE_CONNECTION_SETUP to 11.

Single-ended connection. For this
stage, there is one CINx connected
to the positive CDC input.

Single-ended connection. For this
stage, there is one CINx connected
to the negative CDC input.

Differential connection. For this
stage, there is one CINx connected
to the negative CDC input and one
CINx connected to the positive
CDC input.

CIN CONNECTION SETUP BITS CINSETTING

CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8

CIN9
CIN10
CIN11
CIN12

00 CINx FLOATING

01

10

11

Figure 28. Input Mux Configuration Options

Rev. B | Page 17 of 68

CINx CONNECTED TO
NEGATIVE CDC INPUT

CINx CONNECTED TO
POSITIVE CDC INP UT

CINx CONNECTED TO
BIAS

+

CDC

–

07727-028

AD7147A

NONCONTACT PROXIMITY DETECTION

The AD7147A internal signal processing continuously monitors
all capacitance sensors for noncontact proximity detection. This
feature provides the ability to detect when a user is approaching
a sensor, at which time all internal calibration is immediately
disabled while the AD7147 is automatically configured to detect
a valid contact.

The proximity control register bits are described in Ta bl e 1 3 . The
FP_PROXIMITY_CNT and LP_PROXIMITY_CNT register
bits control the length of the calibration disable period after the
user stops touching the sensor and is not in close proximity to
the sensor during full or low power mode. The calibration is
disabled during this period and then enabled again. Figure 29
and Figure 30 show examples of how these register bits are
used to set the calibration disable periods for the full and low
power modes.

The calibration disable period in full power mode is the value
of the FP_PROXIMITY_CNT multiplied by 16 multiplied by
the time for one conversion sequence in full power mode. The
calibration disable period in low power mode is the value of the
LP_PROXIMITY_CNT multiplied by 4 multiplied by the time
for one conversion sequence in low power mode.

The AD7147A recalibrates automatically when the measured CDC
value exceeds the stored ambient value by an amount determined
by the PROXIMITY_RECAL_LVL bits for a set period of time
known as the recalibration timeout. In full power mode, the recali­bration timeout is controlled by FP_PROXIMITY_RECAL; in
low power mode, by LP_PROXMTY_RECAL.

The recalibration timeout in full power mode is the value of
FP_PROXIMITY_RECAL multiplied by the time for one
conversion sequence in full power mode. The recalibration time­out in low power mode is the value of LP_PROXIMITY_RECAL
multiplied by the time for one conversion sequence in low
power mode.

Figure 31 and Figure 32 show examples of how the FP_
PROXIMITY_RECAL and LP_PROXIMITY_RECAL register
bits control the timeout period before a recalibration while
operating in the full and low power modes. In these examples,
a user approaches a sensor and then leaves, but the proximity
detection remains active. The measured CDC value exceeds the
stored ambient value by the amount set in the PROXIMITY_
RECAL_LVL bits for the entire timeout period. The sensor is
automatically recalibrated at the end of the timeout period.

RECALIBRATION

In certain situations, for example, when a user hovers over a
sensor for a long time, the proximity flag can be set for a long
period. The environmental calibration on the AD7147A is sus­pended while proximity is detected, but changes may occur
to the ambient capacitance level during the proximity event.
This means that the ambient value stored on the AD7147A no
longer represents the actual ambient value. In this case, even
when the user is not in close proximity to the sensor, the prox­imity flag may still be set. This situation can occur if the user
interaction creates some moisture on the sensor, causing the
new sensor ambient value to be different from the expected
value. In this situation, the AD7147A automatically forces a
recalibration internally. This ensures that the ambient values
are recalibrated, regardless of how long the user hovers over
the sensor. A recalibration ensures maximum AD7147A sensor
performance.

PROXIMITY SENSITIVITY

The fast filter in Figure 33 is used to detect when someone is
close to the sensor (proximity). Two conditions, detected by
Comparator 1 and Comparator 2, set the internal proximity
detection signal: Comparator 1 detects when a user is approach­ing or leaving a sensor, and Comparator 2 detects when a user
hovers over a sensor or approaches a sensor very slowly.

The sensitivity of Comparator 1 is controlled by the PROXIMITY_
DETECTION_RATE bits (Address 0x003). For example, if
PROXIMITY_DETECTION_RATE is set to 4, the Proximity 1
signal is set when the absolute difference between WORD1 and
WORD3 exceeds (4 × 16) LSB codes.

The PROXIMITY_RECAL_LVL bits (Address 0x003) control
the sensitivity of Comparator 2. For example, if PROXIMITY_
RECAL_LVL is set to 75, the Proximity 2 signal is set when the
absolute difference between the fast filter average value and the
ambient value exceeds (75 × 16) LSB codes.

Rev. B | Page 18 of 68

AD7147A

Table 13. Proximity Control Registers (See Figure 33)

Length

Bit Name

FP_PROXIMITY_CNT 4 0x002[7:4] Calibration disable time in full power mode.
LP_PROXIMITY_CNT 4 0x002[11:8] Calibration disable time in low power mode.
FP_PROXIMITY_RECAL 10 0x004[9:0]
LP_PROXIMITY_RECAL 6 0x004[15:10]
PROXIMITY_RECAL_LVL 8 0x003[7:0]

PROXIMITY_DETECTION_RATE 6 0x003[13:8]

CDC CONVERSION

SEQUENCE

(INTERNAL)

PROXIMITY
DETECTION
(INTERNAL)

(Bits) Register Address Description

Full power mode proximity recalibration time control.
Low power mode proximity recalibration time control.
Proximity recalibration level. This value, multiplied by 16, controls the

sensitivity of Comparator 2 (see Figure 33).
Proximity detection rate. This value, multiplied by 16, controls the

sensitivity of Comparator 1 (see Figure 33).

USER APPROACHES

SENSOR

12345678910111213141516

USER LEAVES

SENSOR AREA

t

CALDIS

17 18 19 20 21 22 23 24

t

CONV_FP

CALIBRATION

(INTERNAL)

CALIBRATIO N E NABLEDCALIBRATIO N DISABLED

07727-029

Figure 29. Example of Full Power Mode Proximity Detection (FP_PROXIMITY_CNT = 1)

USER LEAVES

SENSOR AREA

t

=

CONV_LP

t

+ LP_CONV_DELAY.

CONV_FP

17 18 19 20 21 22 23 24

t

CALDIS

t

CONV_LP

CALIBRATIO N E NABLEDCALIBRATION DISABLED

07727-030

CDC CONVERSION

SEQUENCE
(INTERNAL)

PROXIMITY

DETECTION

(INTERNAL)

CALIBRATION

(INTERNAL)

USER APPROACHES

SENSOR

12345678910111213141516

NOTES

1. SEQUENCE CONVERSIO N TIME

2. PROXIMITY IS S E T WHEN THE USER APPROACHES THE S E NS OR, AT WHI CH TIME THE INTERNAL CALIBRATION I S DISABLED.

3.

t

= (

t

CALDIS

× LP_PROXIMIT Y _CNT × 4).

CONV_LP

Figure 30. Example of Low Power Mode Proximity Detection (LP_PROXIMITY_CNT = 4)

Rev. B | Page 19 of 68

AD7147A

CDC CONVERSION

SEQUENCE
(INTERNAL)

PROXIMITY

DETECTION

(INTERNAL)

CALIBRATION

(INTERNAL)

RECALIBRATIO N

COUNTER

(INTERNAL)

Figure 31. Example of Full Power Mode Proximity Detection with Forced Recalibration (FP_PROXIMITY_CNT = 1 and FP_PROXIMITY_RECAL = 40)

CDC CONVERSION

SEQUENCE
(INTERNAL)

USER APPROACHES

SENSOR

USER LEAVES

SENSOR AREA

CALIBRATIO N DISABLED

NOTES

1. SEQUENCE CO NV E RS ION TIME

t

=

t

2.

CALDIS

t

3.

RECAL_TIMEOUT

t

= 2 ×

4.

RECAL

USER APPROACHES

SENSOR

× FP_PROXIMITY _CNT × 16.

CONV_FP

=

t

CONV_FP

t

.

CONV_FP

USER LEAVES

SENSOR AREA

× FP_PROX IMITY_RECAL .

t

MEASURED CDC VALUE > S TORED AMBIENT

BY PROXIMITY_RECAL _LVL

16 30 70

t

CALDIS

RECALIBRATIO N T I M EO UT

t

RECAL_TIMEOUT

t

(SEE TABLE 10).

CONV_FP

MEASURED CDC VALUE > S TORED AMBIENT

BY PROXIMITY_RECAL _LVL

16 30 70

RECAL

t

RECAL

t

CONV_FP

CALIBRATION ENABLED

t

CONV_LP

07727-031

PROXIMITY

DETECTION

(INTERNAL)

CALIBRATION

(INTERNAL)

RECALIBRATIO N

(INTERNAL)

t

CALDIS

CALIBRATIO N DISABLED

NOTES

1. SEQUENCE CO NV E RS ION TIME

2.

t

=

t

CALDIS

3.

t

RECAL_TIMEOUT

4.

t

= 2 ×

RECAL

× LP_PROXIMITY_CNT × 4.

CONV_LP

=

t

CONV_LP

t

.

CONV_LP

× LP_PROXIMITY_RECAL.

t

CONV_LP

=

t

+ LP_CONV_DELAY.

CONV_FP

RECALIBRATIO N T I M EO UT

t

RECAL_TIMEOUT

CALIBRATION ENABLED

Figure 32. Example of Low Power Mode Proximity Detection with Forced Recalibration (LP_PROXIMITY_CNT = 4 and LP_PROXIMITY_RECAL = 40)

07727-032

Rev. B | Page 20 of 68

AD7147A

FF_SKIP_CNT

The proximity detection fast FIFO is used by the on-chip logic
to determine if proximity is detected. The fast FIFO expects to
receive samples from the converter at a set rate. The fast filter
skip control, FF_SKIP_CNT (Bits[3:0], Address 0x002), is used
to normalize the frequency of the samples going into the FIFO,
regardless of how many conversion stages are in a sequence.
This value determines which CDC samples are not used
(skipped) by the proximity detection fast FIFO.

Table 14. FF_SKIP_CNT Settings

FF_SKIP
_CNT

0 0.768 × (SEQUENCE_STAGE_NUM + 1) ms 1.536 × (SEQUENCE_STAGE_NUM + 1) ms 3.072 × (SEQUENCE_STAGE_NUM + 1) ms
1 1.536 × (SEQUENCE_STAGE_NUM + 1) ms 3.072 × (SEQUENCE_STAGE_NUM + 1) ms 6.144 × (SEQUENCE_STAGE_NUM + 1) ms
2 2.304 × (SEQUENCE_STAGE_NUM + 1) ms 4.608 × (SEQUENCE_STAGE_NUM + 1) ms 9.216 × (SEQUENCE_STAGE_NUM + 1) ms
3 3.072 × (SEQUENCE_STAGE_NUM + 1) ms 6.144 × (SEQUENCE_STAGE_NUM + 1) ms 12.288 × (SEQUENCE_STAGE_NUM + 1) ms
4 3.84 × (SEQUENCE_STAGE_NUM + 1) ms 7.68 × (SEQUENCE_STAGE_NUM + 1) ms 15.36 × (SEQUENCE_STAGE_NUM + 1) ms
5 4.608 × (SEQUENCE_STAGE_NUM + 1) ms 9.216 × (SEQUENCE_STAGE_NUM + 1) ms 18.432 × (SEQUENCE_STAGE_NUM + 1) ms
6 5.376 × (SEQUENCE_STAGE_NUM + 1) ms 10.752 × (SEQUENCE_STAGE_NUM + 1) ms 21.504 × (SEQUENCE_STAGE_NUM + 1) ms
7 6.144 × (SEQUENCE_STAGE_NUM + 1) ms 12.288 × (SEQUENCE_STAGE_NUM + 1) ms 24.576 × (SEQUENCE_STAGE_NUM + 1) ms
8 6.912 × (SEQUENCE_STAGE_NUM + 1) ms 13.824 × (SEQUENCE_STAGE_NUM + 1) ms 27.648 × (SEQUENCE_STAGE_NUM + 1) ms
9 7.68 × (SEQUENCE_STAGE_NUM + 1) ms 15.36 × (SEQUENCE_STAGE_NUM + 1) ms 30.72 × (SEQUENCE_STAGE_NUM + 1) ms
10 8.448 × (SEQUENCE_STAGE_NUM + 1) ms 16.896 × (SEQUENCE_STAGE_NUM + 1) ms 33.792 × (SEQUENCE_STAGE_NUM + 1) ms
11 9.216 × (SEQUENCE_STAGE_NUM + 1) ms 18.432 × (SEQUENCE_STAGE_NUM + 1) ms 36.864 × (SEQUENCE_STAGE_NUM + 1) ms
12 9.984 × (SEQUENCE_STAGE_NUM + 1) ms 19.968 × (SEQUENCE_STAGE_NUM + 1) ms 39.936 × (SEQUENCE_STAGE_NUM + 1) ms
13 10.752 × (SEQUENCE_STAGE_NUM + 1) ms 21.504 × (SEQUENCE_STAGE_NUM + 1) ms 43.008 × (SEQUENCE_STAGE_NUM + 1) ms
14 11.52 × (SEQUENCE_STAGE_NUM + 1) ms 23.04 × (SEQUENCE_STAGE_NUM + 1) ms 46.08 × (SEQUENCE_STAGE_NUM + 1) ms
15 12.288 × (SEQUENCE_STAGE_NUM + 1) ms 24.576 × (SEQUENCE_STAGE_NUM + 1) ms 49.152 × (SEQUENCE_STAGE_NUM + 1) ms

Decimation = 64 Decimation = 128 Decimation = 256

FAST FIFO Update Rate

Determining the FF_SKIP_CNT value is required only once
during the initial setup of the capacitance sensor interface.
Table 13 shows how FF_SKIP_CNT controls the update rate of
the fast FIFO. The recommended value for the setting when
using all 12 conversion stages on the AD7147A is 0000, or no
samples skipped.

Rev. B | Page 21 of 68