ANALOG DEVICES AD7143 Service Manual

Programmable Controller for

FEATURES

Programmable capacitance-to-digital converter

25 ms update rate (@ maximum sequence length)
Better than 1 fF resolution
8 capacitance sensor input channels
No external RC tuning components required
Automatic conversion sequencer

On-chip automatic calibration logic

Automatic compensation for environmental changes
Automatic adaptive threshold and sensitivity levels

On-chip RAM to store calibration data

2

I

C®-compatible serial interface
Separate VDRIVE level for serial interface
Interrupt output for host controller
16-lead, 4 mm x 4 mm LFCSP-VQ

2.6 V to 3.6 V supply voltage
Low operating current

Full power mode: less than 1 mA
Low power mode: 50 µA

Capacitance Touch Sensors

AD7143

FUNCTIONAL BLOCK DIAGRAM

POWER-ON

TION

ENGINE

TION
RAM

RESET
LOGIC

INTERRUPT

LOGIC

9

VCC

10

GND

CIN0

CIN1

CIN2

CIN3

CIN4

CIN5

CIN6

CIN7

CSHIELD

SRC

15

16

1

2

3

4

5

6

7

8

MATRIX

SWITCH

CONTROL

DATA

REGISTERS

250kHz

EXCITATION

SOURCE

2

I

C SERIAL INT ERFACE

AND CONTROL L OGIC

SDA SCLK INT

VDRIVE

AD7143

16-BIT

Σ-Δ

CDC

AND

Figure 1.

CALIBRA-

CALIBRA-

13 141211

06472-001

APPLICATIONS

Personal music and multimedia players
Cell phones
Digital still cameras
Smart hand-held devices
Television, A/V, and remote controls
Gaming consoles

GENERAL DESCRIPTION

The AD7143 is an integrated capacitance-to-digital converter
(CDC) with on-chip environmental calibration for use in
systems requiring a novel user input method. The AD7143
interfaces to external capacitance sensors implementing
functions, such as capacitive buttons, scroll bars, and
scroll wheels.

The CDC has eight inputs channeled through a switch matrix to
a 16-bit, 250 kHz sigma-delta (∑-∆) capacitance-to-digital
converter. The CDC is capable of sensing changes in the
capacitance of the external sensors and uses this information to
register a sensor activation. The external sensors can be
arranged as a series of buttons, as a scroll bar or wheel, or as a
combination of sensor types. By programming the registers, the
user has full control over the CDC setup. High resolution
sensors require software to run on the host processor.

The AD7143 has on-chip calibration logic to account for
changes in the ambient environment. The calibration sequence is
performed automatically and at continuous intervals, while the
sensors are not touched. This ensures that there are no false or
nonregistering touches on the external sensors due to a
changing environment.

2

The AD7143 has an I
separate VDRIVE pin for I

C-compatible serial interface and a

2

C serial interface operating voltages

between 1.65 V and 3.6 V.

The AD7143 is available in a 16-lead, 4 mm × 4 mm LFCSP-VQ
and operates from a 2.6 V to 3.6 V supply. The operating
current consumption is less than 1 mA, falling to 50 µA in low
power mode (conversion interval of 400 ms).

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

AD7143

TABLE OF CONTENTS

Features .............................................................................................. 1

Proximity Sensitivity.................................................................. 17

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

2

I

C Timing Specifications............................................................ 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 11

Capacitance Sensing Theory ..................................................... 11

Operating Modes........................................................................ 12

Capacitance Sensor Input Configuration.................................... 13

CIN Input Multiplexer Setup.................................................... 13

Slow FIFO.................................................................................... 19

SLOW_FILTER_UPDATE_LVL.............................................. 19

Environmental Calibration........................................................... 22

Capacitance Sensor Behavior without Calibration ................ 22

Capacitance Sensor Behavior with Calibration...................... 23

Adaptive Threshold and Sensitivity............................................. 25

Interrupt Output............................................................................. 26

CDC Conversion Complete Interrupt..................................... 26

Sensor Touch Interrupt.............................................................. 26

Serial Interface................................................................................ 28

2

I

C Compatible Interface........................................................... 28

PCB Design Guidelines ................................................................. 31

Capacitive Sensor Board Mechanical Specifications............. 31

Chip Scale Packages ................................................................... 31

Power-Up Sequence ....................................................................... 32

Capacitiance-to-Digital Converter............................................... 14

Oversampling the CDC Output ............................................... 14

Capacitance Sensor Offset Control .......................................... 14

Conversion Sequencer ............................................................... 14

CDC Conversion Sequence Time ............................................ 15

CDC Conversion Results........................................................... 16

Noncontact Proximity Detection .................................................17

Recalibration ............................................................................... 17

REVISION HISTORY

1/07—Revision 0: Initial Version

Typical Applicat i o n C i rc uits ......................................................... 33

Register Map ................................................................................... 34

Detailed Register Descriptions..................................................... 35

Bank 1 Registers ......................................................................... 35

Bank 2 Registers ......................................................................... 43

Bank 3 Registers ......................................................................... 47

Outline Dimensions ....................................................................... 55

Ordering Guide .......................................................................... 55

Rev. 0 | Page 2 of 56

AD7143

SPECIFICATIONS

VCC = 2.6 V to 3.6 V, TA = −40oC to +85°C, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

CAPACITANCE-TO-DIGITAL CONVERTER

Update Rate 23 25 26 ms Eight conversion stages in sequencer, decimation = 256
Resolution 16 Bit
CIN Input Range
No Missing Codes 16 Bit Guaranteed by design, but not production tested
CIN Input Leakage 25 nA
Total Unadjusted Error ±20 %
Output Noise (Peak-to-Peak) 7 Codes Decimation rate = 128
3 Codes Decimation rate = 256
Output Noise (RMS) 0.8 Codes Decimation rate = 128

0.5 Codes Decimation rate = 256
Parasitic Capacitance 40 pF

C

Offset Range

BULK

C

Offset Resolution 156.25 fF

BULK

Low Power Mode Delay Accuracy 5 % % of 200 ms, 400 ms, 600 ms, or 800 ms

EXCITATION SOURCE

Frequency 237.5 240 262.5 kHz
Output Voltage VCC V
Short-Circuit Source Current 20 mA
Short-Circuit Sink Current 50 mA
Maximum Output Load 250 pF Capacitance load on source to ground
C

Output Drive 10 μA

SHIELD

C

Bias Level VCC/2 V

SHIELD

LOGIC INPUTS (SCLK, SDA)

V

Input High Voltage 0.7 × V

IH

VIL Input Low Voltage 0.4 V
I

Input High Voltage −1 μA

IH

IIL Input Low Voltage 1 μA VIN = GND
Hysteresis 150 mV

OPEN-DRAIN OUTPUTS (SCLK, SDA, INT)

VOL Output Low Voltage 0.4 V I
IOH Output High Leakage Current +0.1 ±1 μA

POWER

V

CC

V

DRIVE

I

CC

20 μA Low power mode, converter idle, TA = 25°C
16 30 μA Low power mode, converter idle

4.5 μA Full shutdown, TA = 25°C

2.25 15 μA Full shutdown

1

C

and C

IN

BULK

PLASTIC O VERLAY

SENSOR BOARD

CAPACITIVE SENSO R

1

1

are defined as follows:

±2 pF

Parasitic capacitance to ground, per CIN input guaranteed
by characterization

±20 pF

DRIVE

V

= −1 mA

SINK

2.6 3.3 3.6 V

1.65 3.6 V

0.9 1 mA In full power mode

C

IN

C

BULK

05702-054

Rev. 0 | Page 3 of 56

AD7143

Table 2. Typical Average Current in Low Power Mode, VCC = 3.6 V, T = 25°C, Load of 50 pF on SRC Pin

Number of Conversion Stages, Current Values Expressed in A

Low Power Mode Delay Decimation Rate

200 ms 128 26.4 33.3 40.1 46.9 53.5 60 66.5 72.8
256 35.6 49.1 62.2 74.9 87.3 99.3 111 122.3
400 ms 128 21.3 24.8 28.3 31.7 35.2 38.6 42 45.4
256 26 32.9 39.7 46.5 53.1 59.6 66.1 72.4
600 ms 128 19.6 21.9 24.3 26.6 28.9 31.2 33.5 35.8
256 22.7 27.4 32 25.6 41.1 45.6 50 54.4
800 ms 128 18.7 20.5 22.2 24 25.7 27.5 29.2 31
256 21.1 24.6 28.1 31.5 35 38.4 41.8 45.2

Table 3. Maximum Average Current in Low Power Mode, VCC = 3.6 V, Load of 50 pF on SRC Pin

Low Power Mode Delay Decimation Rate
200 ms 128 42.2 50.5 58.7 66.7 74.6 82.3 90.0 97.5
256 53.2 69.3 84.9 100.0 114.6 128.7 142.5 155.8
400 ms 128 36.1 40.4 44.5 48.7 52.8 56.9 60.9 64.5
256 41.8 50.1 58.2 66.2 74.1 82.0 89.5 97.1
600 ms 128 34.1 37.0 39.7 42.5 45.3 48.1 50.8 53.4
256 37.9 43.5 49.0 54.5 60.0 65.2 70.5 75.7
800 ms 128 33.1 35.2 37.3 39.4 41.5 43.6 45.7 47.7
256 35.9 40.1 44.3 48.4 52.6 56.6 60.7 64.7

1 2 3 4 5 6 7 8

Number of Conversion Stages, Current Values Expressed in A

1 2 3 4 5 6 7 8

Rev. 0 | Page 4 of 56

AD7143

I2C TIMING SPECIFICATIONS

TA = −40°C to +85°C, VCC = 2.6 V to 3.6 V, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input signals timed
from a voltage level of 1.6 V.

Table 4. I

2

C Timing Specifications

1

Parameter Limit Unit Description

f
t
t
t
t
t
t
t
t

SCLK

1

2

3

4

5

6

7

8

400 kHz max

0.6 μs min Start condition hold time, t

1.3 μs min Clock low period, t

0.6 μs min Clock high period, t
100 ns min Data setup time, t
300 ns min Data hold time, t

SU; DAT

HD; DAT

0.6 μs min Stop condition setup time, t

0.6 μs min Start condition setup time, t

1.3 μs min Bus free time between stop and start conditions, t
tR 300 ns max Clock/data rise time
tF 300 ns max Clock/data fall time

1

Guaranteed by design, not production tested.

200µA I

TO OUTPUT

PIN

C

L

50pF

200µA I

Figure 2. Load Circuit for Digital Output Timing Specifications

LOW

HIGH

HD; STA

SU; STO

SU; STA

BUF

OL

1.6V

OH

06472-003

Rev. 0 | Page 5 of 56

AD7143

ABSOLUTE MAXIMUM RATINGS

Parameter Rating

VCC to GND −0.3 V to +3.6 V
Analog Input Voltage to GND −0.3 V to VCC + 0.3 V
Digital Input Voltage to GND −0.3 V to VDRIVE + 0.3 V
Digital Output Voltage to GND −0.3 V to VDRIVE + 0.3 V
Input Current to Any Pin Except

Supplies
ESD Rating (Human Body Model) 2.5 kV
Operating Temperature Range −40°C to +150°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
LFCSP_VQ

Power Dissipation 450 mW

θJA Thermal Impedance 135.7°C/W
IR Reflow Peak Temperature 260°C (±0.5°C)
Lead Temperature (Soldering 10 sec) 300°C

1

Transient currents of up to 100 mA do not cause SCR latch-up.

1

10 mA

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 6 of 56

AD7143

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

CIN0

CIN1

INT

SCLK

14

13

15

16

PIN 1
INDICATO R

1CIN2

2CIN3

AD7143

3CIN4

TOP VIEW

(Not to Scale)

4CIN5

5

6

CIN6

CIN7

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 CIN2 Capacitance Sensor Input.
2 CIN3 Capacitance Sensor Input.
3 CIN4 Capacitance Sensor Input.
4 CIN5 Capacitance Sensor Input.
5 CIN6 Capacitance Sensor Input.
6 CIN7 Capacitance Sensor Input.
7 CSHIELD CDC Shield Potential Output. Requires 10 nF capacitor to ground.
8 SRC CDC Excitation Source Output.
9 VCC CDC Supply Voltage.
10 GND Ground Reference Point for All CDC Circuitry. Tie to ground plane.
11 VDRIVE I2C Serial Interface Operating Voltage
12 SDA I2C Serial Data Input/Output. SDA requires pull-up resistor.
13 SCLK Clock Input for Serial Interface. SCLK requires pull-up resistor.
14

INT

General-Purpose Open-Drain Interrupt Output. Programmable polarity; requires pull-up resistor.
15 CIN0 Capacitance Sensor Input.
16 CIN1 Capacitance Sensor Input.

12 SDA

11 VDRIVE

10 GND

9VCC

8

7

SRC

CSHIELD

06472-004

Rev. 0 | Page 7 of 56

AD7143

TYPICAL PERFORMANCE CHARACTERISTICS

1000

980

960

940

920

(µA)

I

DEVICE 2

CC

900

880

860

840

820

2.7 2. 92. 8 3.0 3.1 3.2 3.3 3.4 3.5 3.6

DEVICE 3

DEVICE 1

VCC(V)

Figure 4. Supply Current vs. Supply Voltage

06472-005

2.45

2.30

2.15

(µA)

CC

2.00

1.85

SHUTDOWN I

1.70

1.55

1.40

2.7 2. 92.8 3.03.13.23.33.43.53.6

DEVICE 1

VCC (V)

DEVICE 2

DEVICE 3

Figure 7. Shutdown Supply Current vs. Supply Voltage

06472-008

180

160

140

120

(µA)

CC

I

100

80

LP_CONV_DEL AY = 600ms

60

40

2.72.82.93.03.13.2 3.43.3 3.5 3.6

LP_CONV_DEL AY = 200ms

LP_CONV_DELAY = 400ms

LP_CONV_DELAY = 800ms

VCC(V)

Figure 5. Low Power Supply Current vs. Supply Voltage,

Decimation Rate = 256

120

100

80

(µA)

CC

I

60

40

20

LP_CONV_DEL AY = 200ms

LP_CONV_DEL AY = 400ms

LP_CONV_DEL AY = 600ms

LP_CONV_DEL AY = 800ms

2.7 2.8 2.9 3.0 3.1 3.2 3.43.3 3.5 3. 6

VCC(V)

Figure 6. Low Power Supply Current vs. Supply Voltage

Decimation Rate = 128

1.10

DEVICE 1

1.05

1.00

(mA)

0.95

CC

I

DEVICE 3

0.90

0.85

06472-006

0.80
0 50 100 150 200 250 300 350 400 450 500

CAPACITANCE LOAD O N SOURCE (pF )

DEVICE 2

06472-009

Figure 8. Supply Current vs. Capacitive Load on SRC

16015

16010

16005

16000

15995

CDC OUTPUT CODE

15990

15985

06472-007

15980

DEVICE 1

DEVICE 2

DEVICE 3

0 50 100 150 200 250 300 350 400 450 500

CAPACITANCE LO AD ON SOURCE (pF )

06472-010

Figure 9. Output Code vs. Capacitive Load on SRC

Rev. 0 | Page 8 of 56

AD7143

960

940

920

900

880

860

840

SUPPLY CURRENT (µA)

820

800

780

–40 120100

TEMPERATURE ( °C)

Figure 10. Supply Current vs. Temperature

12

10

8

6

4

SUPPLY CURRENT (µA)

2

0

–40 120100806040

200–20

TEMPERATURE (°C)

3.3V

Figure 11. Shutdown Supply Current vs. Temperature

3.6V

3.3V

2.7V

3.6V

806040200–20

06472-011

2.7V

06472-012

0.020

0.015

0.010

0.005

ERROR (pF)

0

–0.005

–0.010

0 70k

10k 20k 30k 40k 50k 60k

CDC OUTPUT CODE

CDC OUTPUT CODE

Figure 13. 3.3 V Linearity Error

2.5

2.0

1.5

1.0

0.5

CDC PEAK-TO-PEAK NOISE (Codes)

0

10 10M100k1k

100mV
200mV

FREQUENCY (Hz)

300mV
400mV
500mV

Figure 14. Power Supply Sine Wave Rejection

06472-046

06472-013

4.8

4.3

3.8

3.3

2.8

CAPACITANCE (pF )

2.3

1.8

1.3
0 10k 20k 30k 40k 50k 60k

CDC OUTPUT CODE

CDC OUTPUT CODE

Figure 12. 3.3 V Linearity

06472-045

Rev. 0 | Page 9 of 56

180

160

140

120

100

80

60

40

CDC PEAK-TO-PEAK NOISE (Codes)

20

0

100 10M

SQUARE WAVE F REQUENCY (Hz)

Figure 15. Power Supply Square Wave Rejection

1M10k 100k1k

300mV

200mV

100mV

50mV
25mV

06472-014

AD7143

32900

32800

32700

32600

32500

32400

32300

32200

CDC OUTPUT CODE (D)

32100

32000

31900

06

PARASITIC

CAPACITANCE

10 20 30 40 50

PCB PARASITIC CAPACI TANCE (pF )

06472-047

0

Figure 16. CDC Output Codes vs. Parasitic Capacitance

Rev. 0 | Page 10 of 56

AD7143

R

THEORY OF OPERATION

The AD7143 is a capacitance-to-digital converter (CDC) with
on-chip environmental compensation, intended for use in
portable systems requiring high resolution user input. The
internal circuitry consists of a 16-bit, ∑-∆ converter that
converts a capacitive input signal into a digital value. There are
eight input pins, CIN0 to CIN7, on the AD7143. A switch
matrix routes the input signals to the CDC. The result of each
capacitance-to-digital conversion is stored in on-chip registers.
The host subsequently reads the results over the serial interface.
The AD7143 has an I

2

C interface, ensuring that the parts are

compatible with a wide range of host processors.

The AD7143 interfaces with up to eight external capacitance
sensors. These sensors can be arranged as buttons, scroll bars,
wheels, or as a combination of sensor types. The external
sensors consist of electrodes on a single or multiple layer PCB
that interface directly to the AD7143.

The AD7143 can be set up to implement any set of input
sensors by programming the on-chip registers. The registers can
also be programmed to control features such as averaging,
offsets, and gains for each of the external sensors. There is a
sequencer on-chip to control how each of the capacitance
inputs is polled.

The AD7143 operates from a 2.6 V to 3.6 V supply, and is
available in a 16-lead, 4 mm × 4 mm LFCSP_VQ.

CAPACITANCE SENSING THEORY

The AD7143 uses a method of sensing capacitance known as
the shunt method. Using this method, an excitation source is
connected to a transmitter generating an electric field to a
receiver. The field lines measured at the receiver are translated
into the digital domain by a ∑-∆ converter. When a finger, or
other grounded object, interferes with the electric field, some of
the field lines are shunted to ground and do not reach the
receiver (see
measured at the receiver decreases when an object comes close
to the induced field.

Figure 17). Therefore, the total capacitance

PLAST IC COVE

TxRx PCB L AYER

The AD7143 has on-chip digital logic and 528 words of RAM
used for environmental compensation. The effects of humidity,
temperature, and other environmental factors can effect the
operation of capacitance sensors. Transparent to the user, the
AD7143 performs continuous calibration to compensate for
these effects, allowing the AD7143 to give error-free results at
all times.

The AD7143 requires some minor companion software that
runs on the host or other microcontroller to implement high
resolution sensor functions, such as a scroll bar or wheel.
However, no host software is required to implement buttons,
including 8-way button functionality. Button sensors are
implemented completely in digital logic on-chip with the status
of each button reported in interrupt status registers.

The AD7143 can be programmed to operate in either full power
mode, or in low power automatic wake-up mode. The
automatic wake-up mode is particularly suited for portable
devices that require low power operation giving the user
significant power savings coupled with full functionality.

INT

The AD7143 has an interrupt output,
new data has been placed into the registers.

, to indicate when

INT

is used to

interrupt the host on sensor activation.

16-BIT

DATA

Σ-Δ

ADC

AD7143

Figure 17. Single Layer Sensing Capacitance Method

EXCITATIO N
SIGNAL
250kHz

06472-015

In practice, the excitation source and ∑-∆ ADC are implemented
on the AD7143, while the transmitter and receiver are constructed
on a PCB that comprises the external sensor.

Registering a Sensor Activation

When a sensor is approached, the total capacitance associated
with that sensor, measured by the AD7143, changes. When the
capacitance changes to such an extent that a set threshold is
exceeded, the AD7143 registers this as a sensor touch and then
automatically updates the internal interrupt status registers.

Preprogrammed threshold levels are used to determine if a
change in capacitance is due to a button being activated. If the
capacitance exceeds one of the threshold limits, the AD7143
registers this as a true button activation. The same threshold
principle is used to determine if other types of sensors, such as
sliders or scroll wheels, are activated.

Rev. 0 | Page 11 of 56

AD7143

Complete Solution for Capacitance Sensing

Analog Devices, Inc. provides a complete solution for
capacitance sensing. The two main elements to the solution are
the sensor PCB and the AD7143.

If the application requires high resolution sensors, such as scroll
bars or wheels, software is required that runs on the host
processor. (No software is required for button sensors.) The
memory requirements for the host depend upon the sensor, and
are typically 9 kB of code and 600 bytes of data memory.

SENSOR PCB

S1

S2

S3

S4

S5

S6

S7

S8

8

AD7143

SRC

I2C

HOST PROCESSOR

1 MIPS

9kB ROM

600 BYTES RAM

Full Power Mode

In full power mode, all sections of the AD7143 remain fully
powered at all times. While a sensor is being touched, the
AD7143 processes the sensor data. If no sensor is touched, the
AD7143 measures the ambient capacitance level and uses this
data for the on-chip compensation routines. In full power
mode, the AD7143 converts at a constant rate. See the
Conversion Sequence Time

section for more information.

CDC

Low Power Mode

When in low power mode, the AD7143 POWER_MODE bits
are set to 10 upon device initialization. If the external sensors
are not touched, the AD7143 reduces its conversion frequency,
thereby greatly reducing its power consumption. The part
remains in a reduced power state when the sensors are not
touched. Every LP_CONV_DELAY ms (200 ms, 400 ms, 600
ms or 800 ms), the AD7143 performs a conversion and uses this
data to update the compensation logic. When an external
sensor is touched, the AD7143 begins a conversion sequence
every 25 ms to read back data from the sensors.

06472-016

Figure 18. Three Part Capacitance Sensing Solution

Analog Devices supplies the sensor PCB footprint design
libraries to the customer based on the customer’s specifications,
and supplies any necessary software on an open-source basis.

OPERATING MODES

The AD7143 has three operating modes. Full power mode,
where the device is always fully powered, is suited for applications
where power is not a concern. One example is game consoles
that have an ac power supply. Low power mode, where the part
automatically powers down, is tailored to give significant power
savings over full power mode, and is suited for mobile applications
where power must be conserved. In shutdown mode, the part
shuts down completely.

The POWER_MODE bits (Bit 0 and Bit 1) of the control
register set the operating mode on the AD7143. The control
register is at Address 0x000.
settings for each operating mode. To put the AD7143 into
shutdown mode, set the POWER_MODE bits to either 01 or 11.

Table 6. POWER_MODE Settings

POWER_MODE Bits Operating Mode

00 Full power mode
01 Full shutdown mode
10 Low power mode
11 Full shutdown mode

The power-on default setting of the POWER_MODE bits is 00,
full power mode.

Tabl e 6 shows the POWER_MODE

In low power mode, the total current consumption of the
AD7143 is an average of the current used during a conversion,
and the current used while the AD7143 is waiting for the next
conversion to begin. For example, when LP_CONV_DELAY is
400 ms, the AD7143 typically uses 0.9 mA current for 25 ms
and 15 A for 400 ms of the conversion interval. Note that these
conversion timings can be altered through the register settings.
See the

CDC Conversion Sequence Time section for more

information.

AD7143 SETUP

AND INITIALIZATION

POWER_MO DE = 10

ANY

NO YES

SENSOR

TOUCHED?

CONVERSIO N SEQUENCE

EVERY LP_CONV_DELAY m s

UPDATE COMPENSATIO N

LOGIC DATA PATH

Figure 19. Low Power Mode Operation

CONVERSION SE QUENCE

EVERY 25ms FOR

SENSOR READ BACK

YES

ANY SENSOR

TOUCHED?

NO

PROXIMITY TIMER

COUNT DO WN

TIMEOUT

The time taken for the AD7143 to go from a full power state to
a reduced power state, once the user stops touching the external
sensors, is configurable. Once the sensors are not touched, the
PWR_DWN_TIMEOUT bits, in the Ambient Compensation
Ctrl 0 Register at Address 0x002, control the amount of time
necessary for the device to return to a reduced power state.

06472-017

Rev. 0 | Page 12 of 56

AD7143

CAPACITANCE SENSOR INPUT CONFIGURATION

Each input connection from the external capacitance sensors to
the AD7143 converter can be uniquely configured by using the
registers in

Tabl e 38 and Ta b l e 3 9. These registers are used to
configure input pin connection setups, sensor offsets, sensor
sensitivities, and sensor limits for each stage. Each sensor can be
individually optimized. For example, a button sensor connected
to STAGE0 can have a different sensitivity and offset values
than a button with a different function that is connected to a
different stage.

CIN INPUT MULTIPLEXER SETUP

The CIN_CONNECTION_SETUP registers in Tabl e 38 list the
available options for connecting the sensor input pin to the CDC.

CIN CONNECTIO N SETUP BIT S CIN SETTING

The AD7143 has an on-chip multiplexer to route the input
signals from each pin to the input of the converter. Each input
pin can be tied to either the negative or the positive input of the
CDC or can be left floating. Each input can also be internally
connected to the C
an input is not used, always connect it to C

signal to help prevent cross coupling. If

SHIELD

.

SHIELD

Connecting a CINx input pin to the positive CDC input results
in a decrease in CDC output code when the corresponding
sensor is activated. Connecting a CINx input pin to the negative
CDC input results in an increase in CDC output code when the
corresponding sensor is activated.

Two bits in each sequencer stage register control the mux
setting for the input pin.

CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7

00 CINx FLOATING

01

10

11

Figure 20. Input Mux Configuration Options

CINx CONNECTED T O
NEGATIVE CDC I NPUT

CINx CONNECTED T O
POSITI VE CDC INPUT

CINx CONNECTED T O
INTERNAL BIAS

+

CDC

–

06472-018

Rev. 0 | Page 13 of 56

AD7143

R

CAPACITIANCE-TO-DIGITAL CONVERTER

The capacitance-to-digital converter on the AD7143 has a Σ-
architecture with 16-bit resolution. Eight possible inputs to the
CDC are connected to the input of the converter through a
switch matrix. The sampling frequency of the CDC is 250 kHz.

OVERSAMPLING THE CDC OUTPUT

The decimation rate, or oversampling ratio, is determined by
Bits[9:8] of the PWR_CONTROL register located at Address 0x000
and listed in

Tabl e 7.

A simplified block diagram in Figure 22 shows how to apply the
STAGE_OFFSET registers to null the offsets. The 7-bit
POS_AFE_OFFSET and NEG_AFE_OFFSET registers program
the offset DAC to provide 0.16 pF resolution offset adjustment
over a range of ±20 pF. Apply the positive and negative offsets
to either the positive or the negative CDC input using the
NEG_AFE_OFFSET register and POS_AFE_OFFSET register.
This process is only required once during the initial capacitance
sensor characterization.

Table 7. CDC Decimation Rate

Decimation Bit
Value

Decimation
Rate

CDC Output Rate
Per Stage

00 256 3.072 ms
01 128 1.525 ms

1

10

1

11

1

Do not use this setting.

– –
– –

The decimation process on the AD7143 is an averaging process
where a number of samples are taken and the averaged result is
output. Due to the architecture of the digital filter employed, the
amount of samples taken (per stage) is equal to 3× the
decimation rate. Therefore, 3 × 256 or 3 × 128 samples are
averaged to obtain each stage result.

The decimation process reduces the amount of noise present in
the final CDC result. However, the higher the decimation rate,
the lower the output rate per stage thus, a trade-off is possible
between a noise free signal and speed of sampling.

CAPACITANCE SENSOR OFFSET CONTROL

There are two programmable DACs on board the AD7143 to
null any capacitance sensor offsets. These offsets are associated
with printed circuit board capacitance or capacitance due to any
other source, such as connectors. In
capacitance of the input sensors, while C
between layers of the sensor PCB. C
on-board DACs.

PLAST IC OVE RLAY

SENSOR BOARD

CAPACITIVE SENSOR

Figure 21. Capacitances Around the Sensor PCB

Figure 21, CIN is the

is the capacitance

BULK

can be offset using the

BULK

C

IN

C

BULK

6472-019

+DAC

(20pF RANGE)

CIN

SENSO

SRC

CIN_CONNECTIO N_SETUP

REGISTER

Figure 22. Analog Front-End Offset Control

–DAC

(20pF RANGE)

7

POS_AFE_OFFSET

POS_AFE_OFFSET_SWAP BIT

+

16-BIT

CDC

_

NEG_AFE_OFFSET_SWAP BIT

16

7

NEG_AFE_OF FSET

CONVERSION SEQUENCER

The AD7143 has an on-chip sequencer to implement
conversion control for the input channels. Up to eight
conversion stages can be performed in sequence. Each of the
eight conversion stages can measure an input from a different
sensor. By using the Bank 2 registers, each stage can be uniquely
configured to support multiple capacitance sensor interface
requirements. For example, a sensor S1 can be assigned to
STAGE1 and sensor S2 assigned to STAGE2.

The AD7143 on-chip sequence controller provides conversion
control beginning with STAGE0.
the CDC conversion stages and CIN inputs. A conversion sequence is
a sequence of CDC conversions starting at STAGE0 and ending at
the stage determined by the value programmed in the
SEQUENCE_STAGE_NUM register. Depending on the number and
type of capacitance sensors used, not all conversion stages are
required. Use the SEQUENCE_STAGE_NUM register to set the
number of conversions in one sequence, depending on the sensor
interface requirements. For example, this register is set to 5 if the CIN
inputs are mapped to only six stages. In addition, set the
STAGE_CAL_EN registers according to the number of stages that
are used.

Figure 23 shows a block diagram of

6472-020

Rev. 0 | Page 14 of 56

AD7143

STAGE7

STAGE6

STAGE5

STAGE4

STAGE3

STAGE2

STAGE1

STAGE0

CIN0

CIN1

CIN2

CIN3

CIN4

CIN5

CIN6

CIN7

SWITCH MA TRIX

Σ-Δ

16-BIT

ADC

CO

NV

CE

N

E

U

Q

E

S

N

O

I

RS

E

06472-021

Figure 23. CDC Conversion Stages

The number of required conversion stages depends completely
on the number of sensors attached to the AD7143.

Figure 24
shows how many conversion stages are required for each sensor,
and how many inputs each sensor requires to the AD7143.

AD7143

SEQUENCER

STAGE0

8-ELEMENT

SLIDER

SRC

+

CDC

–

STAGE1

+

CDC

–

STAGE2

+

CDC

–

STAGE3

+

CDC

–

STAGE4

+

CDC

–

STAGE5

+

CDC

–

STAGE6

+

CDC

–

STAGE7

+

CDC

–

BUTTONS

S1

S2

S3

SRC

AD7143

SEQUENCER

STAGE0

+

CDC

–

STAGE1

+

CDC

–

Figure 24. Sequencer Setup for Sensors

A button sensor generally requires one sequencer stage.
However, it is possible to configure two button sensors to
operate differentially for special applications where the user
should not press both buttons simultaneously, such as a with
rocker zoom switch on a digital camera.

6472-022

In this case, only one button from the pair is activated at a time;
pressing both buttons together activates neither button. This
example is shown in

Figure 24 for sensor buttons S2 and S3.

A scroll bar or slider requires eight stages. The result from each
stage is used by the host software to determine the user’s
position on the scroll bar. The algorithm that performs this
process is available from Analog Devices free of charge, upon
signing a software license. Scroll wheels also require eight stages.

CDC CONVERSION SEQUENCE TIME

The time required for one complete measurement for all eight
stages by the CDC is defined as the CDC conversion sequence
time. The SEQUENCE_STAGE_NUM register and
DECIMATION register determine the conversion time as listed
in

Tabl e 8.

Table 8. CDC Conversion Times for Full Power Mode

Conversion Time (ms)

SEQUENCE_STAGE_NUM

0 1.525 3.072
1 3.072 6.144
2 4.608 9.216
3 6.144 12.288
4 7.68 15.25
5 9.216 18.432
6 10.752 21.504
7 12.288 24.576

For example, while operating with a decimation rate of 128,
if the SEQUENCE_STAGE_NUM register is set to 5 for the
conversion of six stages in a sequence, the conversion sequence
time is 9.216 ms.

Full Power Mode CDC Conversion Sequence Time

The full power mode CDC conversion sequence time for all
eight stages is set by configuring the SEQUENCE_STAGE_NUM
register and the DECIMATION register as outlined in

Figure 25 shows a simplified timing diagram of the full power
CDC conversion time. The full power mode CDC conversion
time t

CONVERS ION

is set using Tabl e 8.

CONV_FP

t

CONVERSION

CDC

SEQUENCE N

Figure 25. Full Power Mode CDC Conversion Sequence Time

Decimation = 128 Decimation = 256

CONV_FP

CONVERSION

SEQUENCE N + 1

CONVERS ION

SEQUENCE N + 2

Tabl e 8.

06472-023

Rev. 0 | Page 15 of 56

AD7143

Low Power Mode CDC Conversion Sequence Time with Delay

The frequency of each CDC conversion while operating in the
low power automatic wake-up mode is controlled by using the
LP_CONV_DELAY register located at Address 0x000[3:2], in
addition to the registers listed in

Tabl e 8.

This feature provides some flexibility for optimizing the
conversion time to meet system requirements vs. AD7143
power consumption. For example, maximum power savings is
achieved when the LP_CONV_DELAY register is set to 3. With
a setting of 3, the AD7143 automatically wakes up, performing a
conversion every 800 ms.

Table 9. LP_CONV_DELAY Settings

LP_CONV_DELAY Bits Delay Between Conversions

00 200 ms
01 400 ms
10 600 ms
11 800 ms

Figure 26 shows a simplified timing example of the low power
CDC conversion time. As shown, the low power CDC
conversion time is set by t

and the LP_CONV_DELAY

CONV_FP

register.

t

CONV_LP

t

CONV_FP

CDC

CONVERSION

CONVERSION
SEQUENCE N

Figure 26. Low Power Mode CDC Conversion Sequence Time

LP_CONV_DELAY

CONVERSION

SEQUENCE N + 1

06472-024

CDC CONVERSION RESULTS

Certain high-resolution sensors require the host to read back
the CDC conversion results for processing. The registers
required for host processing are located in the Bank 3 registers.
The host processes the data readback from these registers using
a software algorithm to determine position information. In
addition to the results registers in the Bank 3 registers, the
AD7143 provides the 16-bit CDC output data directly starting
at Address 0x00B of Bank 1. Reading back the CDC 16-bit
conversion data register allows for customer-specific application
data processing.

Rev. 0 | Page 16 of 56

AD7143

NONCONTACT PROXIMITY DETECTION

The AD7143 internal signal processing continuously monitors
all capacitance sensors for noncontact proximity detection. This
feature provides the ability to detect when a user is approaching
a sensor, immediately disabling all internal calibration while the
AD7143 is automatically configured to detect a valid contact.

The proximity control register bits are described in
FP_PROXIMITY_CNT register bits and LP_PROXIMITY
_CNT register bits control the length of the calibration disable
period after proximity is detected in full power and low power
modes. The calibration is disabled during this time and enabled
again at the end of this period if the user is no longer
approaching, or in contact with, the sensor.
28

show examples of how these registers are used to set the full

and low power mode calibration disable periods.

Calibration disable period in full power mode =

(FP_PROXIMITY_CNT × 16 × Time for one conversion

sequence in full power mode)

Calibration disable period in low power mode =
(LP_PROXIMITY_CNT × 4 × Time for one conversion
sequence in low power mode)

Figure 27 and Figure

Tabl e 10 .

RECALIBRATION

In certain situations, the proximity flag can be set for a long
period, such as when a user hovers over a sensor for a long
time. The environmental calibration on the AD7143 is
suspended while the proximity is detected, but changes may
occur to the ambient capacitance level during the proximity
event. Even when the user has left the sensor untouched, the
proximity flag may still be set. This could occur if the user
interaction creates some moisture on the sensor causing the
new sensor value to be different from the expected value. In this
case, the AD7143 automatically forces an internal recalibration.
This ensures that the ambient values are recalibrated, regardless
of how long the user hovers over a sensor.

The AD7143 recalibrates automatically when the measured CDC value
exceeds the stored ambient value by an amount determined by
PROXIMITY_RECAL_LVL, for a set period know as the
recalibration timeout. In full power mode, the recalibration

timeout is controlled by FP_PROXIMITY_RECAL and in low
power mode, it is controlled by LP_PROXMTY_RECAL.

Recalibration timeout in full power mode =
FP_PROXIMITY_RECAL × Time for one conversion
sequence in full power mode

Recalibration timeout in low power mode =
LP_PROXIMITY_RECAL × Time taken for one conversion
sequence in low power mode

Figure 29 and Figure 30 show examples of using the
FP_PROXIMITY_RECAL and LP_PROXIMITY_RECAL
register bits to force a recalibration while operating in the full
and low power modes. These figures show the result of a user
approaching a sensor then leaving the sensor while the
proximity detection remains active after the user discontinues
contact with the sensor. This situation could occur if the user
interaction created some moisture on the sensor causing the
new sensor value to be different from the expected value. In this
case, the internal recalibration is applied to automatically
recalibrate the sensor. The forced recalibration event takes two
interrupt cycles; therefore, it should not be set again during this
interval.

PROXIMITY SENSITIVITY

The fast filter in Figure 31 is used to detect when some one is in
close proximity to the sensor. Two conditions set the internal
proximity detection signal using Comparator 1 and Comparator 2.

Comparator 1 detects when a user is approaching a sensor.
The PROXIMITY_DETECTION_RATE register controls the
sensitivity of Comparator 1. Consider, for example, if the
PROXIMITY_DETECTION_RATE is set to 4, the Proximity 1
signal is set when the absolute difference between WORD1 and
WORD3 exceeds four LSB codes.

Comparator 2 detects when a user hovers over a sensor or
approaches a sensor very slowly. The PROXIMITY_RECAL_LVL
register (Address 0x003) controls the sensitivity of Comparator 2.
For example, if PROXIMITY_RECAL_LVL is set to 75, the
Proximity 2 signal is set when the absolute difference between
the fast filter average value and the ambient value exceeds 75
LSB codes.

Table 10. Proximity Control Registers (See

Register Length Register Address Description

FP_PROXIMITY_CNT 4 bits 0x002 [7:4] Calibration disable time in full power mode
LP_PROXIMITY_CNT 4 bits 0x002 [11:8] Calibration disable time in low power mode
FP_PROXIMITY_RECAL 8 bits 0x004 [9:0] Full power mode proximity recalibration control
LP_PROXIMITY_RECAL 6 bits 0x004 [15:10] Low power mode proximity recalibration control
PROXIMITY_RECAL_LVL 8 bits 0x003 [13:8] Proximity recalibration level
PROXIMITY_DETECTION_RATE 6 bits 0x003 [7:0] Proximity detection rate

Figure 31)

Rev. 0 | Page 17 of 56