ANALOG DEVICES AD 712 JR Datasheet

Precision, Low Cost,

A

FEATURES

Enhanced replacement for LF412 and TL082
AC performance

Settles to ±0.01% in 1.0 μs
16 V/μs minimum slew rate (AD712J)
3 MHz minimum unity-gain bandwidth (AD712J)

DC performance

200 V/mV minimum open-loop gain (AD712K)
Surface mount available in tape and reel in

accordance with the EIA-481A standard
MIL-STD-883B parts available
Single version available: AD711
Quad version: AD713
Available in PDIP, SOIC_N, and CERDIP packages

GENERAL DESCRIPTION

The AD712 is a high speed, precision, monolithic operational
amplifier offering high performance at very modest prices. Its
very low offset voltage and offset voltage drift are the results of
advanced laser wafer trimming technology. These performance
benefits allow the user to easily upgrade existing designs that
use older precision BiFETs and, in many cases, bipolar op amps.

The superior ac and dc performance of this op amp makes it
suitable for active filter applications. With a slew rate of 16 V/µs
and a settling time of 1 µs to ±0.01%, the AD712 is ideal as a
buffer for 12-bit digital-to-analog converters (DACs) and analog­to-digital converters (ADCs) and as a high speed integrator.
The settling time is unmatched by any similar IC amplifier.

The combination of excellent noise performance and low input
current also make the AD712 useful for photo diode preamps.
Common-mode rejection of 88 dB and open-loop gain of
400 V/mV ensure 12-bit performance even in high speed
unity-gain buffer circuits.

The AD712 is pinned out in a standard op amp configuration
and is available in seven performance grades. The AD712J and
AD712K are rated over the commercial temperature range of
0°C to 70°C. The AD712A is rated over the industrial tempera­ture range of −40°C to +85°C. The AD712S is rated over the
military temperature range of −55°C to +125°C and is available
processed to MIL-STD-883B, Rev. C.

High Speed BiFET Dual Op Amp

AD712

CONNECTION DIAGRAM

MPLIFIER NO. 1

OUTPUT

INVERTING

NONINVERTING

SOIC_N (R-Suffix), and CERDIP (Q-Suffix)

1

2

INPUT

3

INPUT

V–

4

AD712

Figure 1. 8-Lead PDIP (N-Suffix),

Extended reliability PLUS screening is available, specified
over the commercial and industrial temperature ranges. PLUS
screening includes 168-hour burn-in, in addition to other
environmental and physical tests.

The AD712 is available in 8-lead PDIP, SOIC_N, and CERDIP
packages.

PRODUCT HIGHLIGHTS

1. The AD712 offers excellent overall performance at very

competitive prices.

2. The Analog Devices, Inc., advanced processing technology

and 100% testing guarantee a low input offset voltage (3
mV maximum, J grade). Input offset voltage is specified in
the warmed-up condition.

3. Together with precision dc performance, the AD712 offers

excellent dynamic response. It settles to ±0.01% in 1 µs and
has a minimum slew rate of 16 V/µs. Thus, this device is
ideal for applications such as DAC and ADC buffers that
require a combination of superior ac and dc performance.

AMPLIFIER NO. 2

8

V+

OUTPUT

7

INVERTING

6

INPUT
NONINVERTING

5

INPUT

00823-001

Rev. H

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] ©1986–2010 Analog Devices, Inc. All rights reserved.

www.analog.com

AD712

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications Information .............................................................. 14

Connection Diagram ....................................................................... 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

Typical Performance Characteristics ............................................. 6

Settling Time ................................................................................... 11

Optimizing Settling Time .......................................................... 11

Op Amp Settling Time—A Mathematical Model .................. 12

REVISION HISTORY

7/10—Rev. G to Rev. H

Changes to Product Title ................................................................. 1

Added Input Voltage Noise Parameter, Input Current Noise

Parameter, and Open-Loop Gain Parameter, Table 1 .................. 4

Moved Figure 29 and Figure 30 .................................................... 11

Moved Figure 34 ............................................................................. 12

Moved Figure 44 and Figure 45 .................................................... 15

Changes to Ordering Guide .......................................................... 20

8/06—Rev. F to Rev. G

Edits to Figure 1 ................................................................................ 1

Change to 9-Pole Chebychev Filter Section ................................ 18

6/06—Rev. E to Rev. F

Updated Format .................................................................. Universal

Deleted B, C, and T Models............................................... Universal

Changes to General Description .................................................... 1

Changes to Product Highlights ....................................................... 1

Changes to Specifications Section .................................................. 3

Guarding ...................................................................................... 14

DAC Converter Applications .................................................... 14

Noise Characteristics ................................................................. 15

Driving the Analog Input of an ADC ...................................... 15

Driving a Large Capacitive Load .............................................. 16

Filters ................................................................................................ 17

Active Filter Applications .......................................................... 17

Second-Order Low-Pass Filter.................................................. 17

9-Pole Chebychev Filter ............................................................. 18

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 20

Changes to Figure 43 ...................................................................... 15

7/02—Rev. D to Rev. E

Edits to Features ................................................................................. 1

9/01—Rev. C to Rev. D

Edits to Features ................................................................................. 1

Edits to General Description ........................................................... 1

Edits to Connection Diagram .......................................................... 1

Edits to Ordering Guide ................................................................... 3

Deleted Metalization Photograph ................................................... 3

Edits to Absolute Maximum Ratings ............................................. 3

Edits to Figure 7 ................................................................................. 9

Edits to Outline Dimensions ......................................................... 15

Rev. H | Page 2 of 20

AD712

SPECIFICATIONS

VS = ±15 V @ TA = 25°C, unless otherwise noted. Specifications in boldface are tested on all production units at final electrical test.
Results from those tests are used to calculate outgoing quality levels. All minimum and maximum specifications are guaranteed, although
only those shown in boldface are tested on all production units.

Table 1.

AD712J/AD712A/AD712S AD712K
Parameter Min Typ Max Min Typ Max Unit

INPUT OFFSET VOLTAGE1

Initial Offset

T

to T

MAX

MIN

vs. Temperature 7

vs. Supply

T

to T

MAX

MIN

0.3

3/1/1

4/2/2
20/20/20

76

76/76/76

95

Long-Term Offset Stability 15 15 µV/month

INPUT BIAS CURRENT2

VCM = 0 V
VCM = 0 V @ T

0.6/1.6/26 1.7/4.8/77 0.5 1.7 nA

MAX

VCM = ±10 V

25

75

100

INPUT OFFSET CURRENT

VCM = 0 V
VCM = 0 V @ T

0.3/0.7/11 0.6/1.6/26 0.1 0.6 nA

MAX

10

25

MATCHING CHARACTERISTICS

Input Offset Voltage

T

to T

MAX

MIN

Input Offset Voltage Drift
Input Bias Current

3/1/1

4/2/2
20/20/20

25

Crosstalk

@ f = 1 kHz 120 120 dB

@ f = 100 kHz 90 90 dB

FREQUENCY RESPONSE

Small Signal Bandwidth 3.0 4.0 3.4 4.0 MHz
Full Power Response 200 200 kHz
Slew Rate

16

20
Settling Time to 0.01% 1.0 1.2 1.0 1.2 µs
Total Harmonic Distortion 0.0003 0.0003 %

INPUT IMPEDANCE

Differential 3×1012||5.5 3×1012||5.5 Ω||pF
Common Mode 3×1012||5.5 3×1012||5.5 Ω||pF

INPUT VOLTAGE RANGE

Differential3 ±20 ±20 V
Common-Mode Voltage4 +14.5, −11.5 +14.5, −11.5 V

T

to T

MIN

MAX

−V

+ 4

S

+VS − 2 −VS + 4

Common-Mode Rejection Ratio

VCM = ±10 V

T

to T

MIN

MAX

VCM = ±11 V

T

to T

MIN

MAX

76
76/76/76
70

70/70/70

88

84

84

80

0.2

7

80
80

100 dB
dB

20

5

18

20 V/µs

80
80
76
74

88 dB
84 dB
84 dB
80 dB

1.0

2.0
10

75

100

25

1.0

2.0
10
25

+VS − 2

mV
mV
V/°C

pA

pA

pA

mV
mV
µV/°C
pA

V

Rev. H | Page 3 of 20

AD712

AD712J/AD712A/AD712S AD712K
Parameter Min Typ Max Min Typ Max Unit

INPUT VOLTAGE NOISE

f = 0.1 Hz to 10 Hz 2 2 µV p-p
f = 10 Hz 45 45 nV/√Hz
f = 100 Hz 22 22 nV/√Hz
f = 1 kHz 18 18 nV/√Hz
f = 10 kHz 16 16 nV/√Hz

INPUT CURRENT NOISE

f = 1 kHz 0.01 0.01 pA/√Hz

OPEN-LOOP GAIN

V

= −10 V to +10 V

OUT

T

to T

MAX

MIN

OUTPUT CHARACTERISTICS

Voltage

150
100/100/100

+13, −12.5

±12/±12/±12

Current +25 +25 mA

POWER SUPPLY

Rated Performance ±15 ±15 V
Operating Range
Quiescent Current

1

Input offset voltage specifications are guaranteed after 5 minutes of operation at TA = 25°C.

2

Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at TA = 25°C. For higher temperatures, the current doubles every 10°C.

3

Defined as voltage between inputs, such that neither exceeds ±10 V from ground.

4

Typically exceeding −14.1 V negative common-mode voltage on either input results in an output phase reversal.

±4.5

+5.0

400

200
100

400 V/mV
V/mV

+13.9, −13.3
+13.8, −13.1

+13, −12.5
±12

±18 ±4.5
+6.8

+5.0

+13.9, −13.3 V
+13.8, −13.1 V

±18
+6.0

V
mA

Rev. H | Page 4 of 20

AD712

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage ±18 V
Internal Power Dissipation1
Input Voltage2 ±18 V
Output Short-Circuit Duration Indefinite
Differential Input Voltage +VS and −VS
Storage Temperature Range

Q-Suffix −65°C to +150°C
N-Suffix and R-Suffix −65°C to +125°C

Operating Temperature Range

AD712J/K 0°C to 70°C
AD712A −40°C to +85°C
AD712S −55°C to +125°C

Lead Temperature Range (Soldering 60 sec) 300°C

1

Thermal characteristics:

8-lead PDIP package: θJA = 165°C/W

8-lead CERDIP package: θJC = 22°C/W; θJA = 110°C/W
8-lead SOIC package: θJA = 100°C/W

2

For supply voltages less than ±18 V, the absolute maximum voltage is equal

to the supply voltage.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. H | Page 5 of 20

AD712

V

TYPICAL PERFORMANCE CHARACTERISTICS

20

6

15

10

= 2kΩ

R

L

25°C

5

INPUT VOLTAGE SWING (V)

0

0510

SUPPLY VOLTAGE ± V

Figure 2. Input Voltage Swing vs. Supply Voltage

20

15

10

5

OUTPUT VOLTAGE SWING (V)

0

05

SUPPLY VOLTAGE ± V

+V

OUT

RL= 2kΩ
25°C

10 15 20

Figure 3. Output Voltage Swing vs. Supply Voltage

15 20

–V

OUT

5

4

3

QUIESCENT CURRENT (mA)

2

0 5 10 15 20

00823-002

SUPPLY VOLTAGE ± V

00823-005

Figure 5. Quiescent Current vs. Supply Voltage

6

10

7

10

8

= 0) (Amps)

10

CM

9

10

10

10

11

10

INPUT BIAS CURRENT (

12

10

–40 –20

00823-003

–60

0 20 40 60 80 100 120 140

TEMPERATURE (°C)

0823-006

Figure 6. Input Bias Current vs. Temperature

30

25

20

±15V SUPPLIES

15

10

OUTPUT VO LTAGE SW ING (V p-p)

5

0

10 100 1k 10k

LOAD RESIS T ANCE ( Ω)

0823-004

Figure 4. Output Voltage Swing vs. Load Resistance

100

OUTPUT IM PE DANCE (Ω)

0.01

1.0

0.1

10

1k

10k 100k 1M 10M

FREQUENCY (Hz)

0823-007

Figure 7. Output Impedance vs. Frequency

Rev. H | Page 6 of 20

AD712

100

100

100

MAX J GRADE LIMIT

75

= 15V

V

S

50

25

INPUT BIAS CURRENT ( pA)

0
–10

–5 0 5 10

COMMON MODE VO LTAGE (V)

25°C

Figure 8. Input Bias Current vs. Common-Mode Voltage

26

24

22

20

18

16

14

SHORT-CIRCUI T CURRENT LIMIT (mA)

12

– OUTPUT CURRENT

+ OUTPUT CURRENT

80

60

40

20

OPEN-LOOP GAIN (dB)

0

–20

10 100 1k 10k 100k 1M 10M

00823-008

GAIN
PHASE
2kΩ
100pF
LOAD

FREQUENCY (Hz)

80

60

40

20

PHASE MARGIN ( Degrees)

0

–20

0823-011

Figure 11. Open-Loop Gain and Phase Margin vs. Frequency

125

120

115

= 2kΩ

R

L

110

105

OPEN-LOOP GAIN (dB)

100

25°C

10

–60

–40 –20 0 20 40 60 80 100 120 140

AMBIENT TEM P E RATURE (°C)

Figure 9. Short-Circuit Current Limit vs. Temperature

5.0

4.5

4.0

3.5

UNITY-GAIN BANDWIDTH (MHz)

3.0

–40 –20 0 20 40 60 80 100 120 140

–60

TEMPERATURE (°C)

Figure 10. Unity-Gain Bandwidth vs. Temperature

95

0 5 10 15 20

00823-009

SUPPLY VOLTAGE ± V

00823-012

Figure 12. Open-Loop Gain vs. Supply Voltage

110
100

80

60

40

POWER SUPPLY REJECTION (dB)

20

VS = ±15V SUPPLIES
WITH 1V p-p SINEWAVE 25°C

0

10 100 1k 10k 100k 1M

00823-010

SUPPLY MODULATION FREQUENCY (Hz)

+ SUPPLY

– SUPPLY

00823-013

Figure 13. Power Supply Rejection vs. Frequency

Rev. H | Page 7 of 20

AD712

–

√

100

CMR (dB)

VS = ±15V

= 1V p-p

V

CM

80

60

40

25°C

THD (dB)

–80

–90

–100

–110

70

3V rms
R

= 2kΩ

L

C

= 100pF

L

20

0

10 100 1k 10k 100k 1M

FREQUENCY (Hz)

Figure 14. Common-Mode Rejection vs. Frequency

30

25

20

15

10

OUTPUT VOLTAGE SW ING (V p-p)

5

0

100k 1M 10M

FREQUENCY (Hz)

RL= 2kΩ
25°C

= ±15V

V

S

Figure 15. Large Signal Frequency Response

10

8

6

4

OUTPUT SWING FROM 0V TO ±VOLTS

–10

2

0

–2

–4
–6

–8

0.5

0.6 0.7

0.01%0.1%1%

0.1%1%ERROR

0.01%

SETTLING TIME (µs)

0.8 0.9 1.0

Figure 16. Output Swing and Error vs. Settling Time

–120

–130

100 1k 10k 100k

00823-014

FREQUENCY (Hz)

00823-017

Figure 17. Total Harmonic Distortion vs. Frequency

1k

Hz)

100

10

INPUT NOISE VOLTAGE (nV/

1

00823-015

10 100 1k 10k 100k1

FREQUENCY (Hz)

0823-018

Figure 18. Input Noise Voltage Spectral Density

25

20

15

10

SLEW RATE (V/µ s)

5

0

0 100

00823-016

200 300 400 500 600 700 800 900

INPUT ERROR SIGNAL (mV)

(AT SUMMING J UNC TION )

00823-019

Figure 19. Slew Rate vs. Input Error Signal

Rev. H | Page 8 of 20

AD712

V

V

V

25

+V

S

0.1µF

–

8

1/2

20

SLEW RATE (V/µs)

IN

SQUARE
WAVE
INPUT

AD712

+

4

0.1µF

–V

S

R
2kΩ

V

OUT

C

L

L

100pF

00823-023

15

–60 –40 –20

Figure 20. Slew Rate vs. Temperature

INPUT

–

2

20V p-p

CROSSTALK = 20 log

AD712

+

3

V

IN

0 20 40 60 80 100 120 140

TEMPERATURE ( °C)

+

S

0.1µF

8

+

1/2

AD712

–

4

0.1µF

–V

S

2kΩ

100pF

Figure 21. THD Test Circuit

OUT

+V

S

8

1/2

1

5kΩ 5kΩ

V

OUT

10V

IN

20kΩ 2.2kΩ

–

1/2

7

AD712

+

4

–V

S

6

5

Figure 22. Crosstalk Test Circuit

OUTPUT

0823-020

Figure 23. Unity-Gain Follower

100

90

0823-021

10

0%

5V

1µs

00823-024

Figure 24. Unity-Gain Follower Pulse Response (Large Signal)

100

90

0823-022

10

0%

50mV

100ns

00823-025

Figure 25. Unity-Gain Follower Pulse Response (Small Signal)

Rev. H | Page 9 of 20

AD712

V

5kΩ

+V

S

5kΩ

IN

SQUARE
WAVE
INPUT

0.1µF

–

8

1/2

AD712

+

4

0.1µF

–V

S

R
2kΩ

Figure 26. Unity-Gain Inverter

V

OUT

C

L

L

100pF

00823-026

100

90

10

0%

50mV

200ns

Figure 28. Unity-Gain Inverter Pulse Response (Small Signal)

0823-028

100

90

10

0%

5V

1µs

Figure 27. Unity-Gain Inverter Pulse Response (Large Signal)

00823-027

Rev. H | Page 10 of 20

AD712

–10V

F

SETTLING TIME

OPTIMIZING SETTLING TIME

Most bipolar high speed DACs have current outputs; therefore,
for most applications, an external op amp is required for a current­to-voltage conversion. The settling time of the converter/op amp
combination depends on the settling time of the DAC and output
amplifier. A good approximation is

22

()(

+=

The settling time of an op amp DAC buffer varies with the noise
gain of the circuit, the DAC output capacitance, and the amount
of external compensation capacitance across the DAC output
scaling resistor.

Settling time for a bipolar DAC is typically 100 ns to 500 ns.
Previously, conventional op amps have required much longer
settling times than have typical state-of-the-art DACs; therefore,
the amplifier settling time has been the major limitation to a high
speed, voltage output, digital-to-analog function. The introduction
of the AD71x family of op amps with their 1 s (to ±0.01% of
final value) settling time permits the full high speed capabilities
of most modern DACs to be realized.

In addition to a significant improvement in settling time, the
low offset voltage, low offset voltage drift, and high open-loop
gain of the AD71x family assure 12-bit accuracy over the full
operating temperature range.

The excellent high speed performance of the AD712 is shown in
the oscilloscope photos in Figure 29 and Figure 30. Measurements
were taken using a low input capacitance amplifier connected
directly to the summing junction of the AD712, and both figures
show a worst-case situation: full-scale input transition. The 4 kΩ
[10 kΩ||8 kΩ = 4.4 kΩ] output impedance of the DAC, together
with a 10 kΩ feedback resistor, produce an op amp noise gain of

3.25. The current output from the DAC produces a 10 V step at
the op amp output (0 to −10 V shown in Figure 29, and −10 V to
0 V shown in Figure 30).

R2
100Ω

GAIN

ADJUST

REF

IN

REF

GND

SSS

AMPtDACtTotalt

+

–

REF
OUT

19.95kΩ

)

0.1µ

10V

0.5mA
I

REF

20kΩ

V

CC

R1

100Ω

AD565A

BIPOLAR
OFFSET ADJUST

BIPOLAR

9.95kΩ

DAC

I

= 4 ×

OUT

I

× CODE

REF

OFF

Therefore, with an ideal op amp, settling to ±1/2 LSB (±0.01%)
requires that 375 µV or less appears at the summing junction.
This means that the error between the input and output (that
voltage which appears at the AD712 summing junction) must
be less than 375 µV. As shown in Figure 29, the total settling
time for the AD712/AD565A combination is 1.2 microseconds.

5V1mV

100

90

SUMMING
JUNCTION

0V

10

0%

–10V

Figure 29. Settling Characteristics for AD712 with AD565A,

Full-Scale Negative Transition

100

90

SUMMING
JUNCTION

0V

10

0%

OUTPUT

Figure 30. Settling Characteristics for AD712 with AD565A,

Full-Scale Positive Transition

20V
SPAN

5kΩ

10V
SPAN

5kΩ

DAC
OUT

I

8kΩ

O

10pF

+15V

–

1/2

AD712

+

0.1µF

8

4

0.1µF

5V1mV

OUTPUT

OUTPUT
–10V TO +10V

500ns

500ns

0823-030

00823-031

–V

0.1µF

POWER

EE

GND

MSB LSB

Figure 31. ±10 V Voltage Output Bipolar DAC

–15V

0823-029

Rev. H | Page 11 of 20

AD712

OP AMP SETTLING TIME—A MATHEMATICAL MODEL

The design of the AD712 gives careful attention to optimizing
individual circuit components; in addition, a careful trade-off
was made: the gain bandwidth product (4 MHz) and slew rate
(20 V/µs) were chosen to be high enough to provide very fast
settling time but not too high to cause a significant reduction
in phase margin (and therefore, stability). Thus designed, the
AD712 settles to ±0.01%, with a 10 V output step, in under 1 µs,
while retaining the ability to drive a 250 pF load capacitance
when operating as a unity-gain follower.

If an op amp is modeled as an ideal integrator with a unity-gain
crossover frequency of ω
describes the small signal behavior of the circuit of Figure 32,
consisting of an op amp connected as an I-to-V converter at the
output of a bipolar or CMOS DAC. This equation would com­pletely describe the output of the system if not for the finite slew
rate and other nonlinear effects of the op amp.

V

O

=

I

IN

)(

CR

X

ω

O

Where

O

= unity-gain frequency of the op amp.

πω2

= noise gain of circuit

G

N

/2π, then Equation 1 accurately

O

−

R

⎛

G

2

N

⎜

+

+

s

⎜

ω

O

⎝

⎛

R

⎜

1

+

⎜

R

O

⎝

(1)

⎞
⎟

1

+

sRC

f

⎟
⎠

⎞

.

⎟
⎟

⎠

When R
equivalents, the general-purpose inverting amplifier shown in
Figure 33 is created. Note that when using this general model,
Capacitance C
a simple inverting op amp is being simulated, or the combined
capacitance of the DAC output and the op amp input if the
DAC buffer is being modeled.

In either case, Capacitance CX causes the system to go from a
one-pole to a two-pole response; this additional pole increases
settling time by introducing peaking or ringing in the op amp
output. Because the value of C
accuracy, Equation 2 can be used to choose a small capacitor
(C
Figure 34 is a graphical solution of Equation 2 for the AD712
with R = 4 kΩ.

and IO are replaced with their Thevenin VIN and RIN

O

is either the input capacitance of the op amp, if

X

+

1/2

AD712
–

R

IN

V

IN

C

X

RLC

C

F

R

V

OUT

L

00823-033

Figure 33. Simplified Model of the AD712 Used as an Inverter

can be estimated with reasonable

X

) to cancel the input pole and optimize amplifier response.

F

60

50

40

GN= 4.0

This equation can then be solved for C

()

−

G

2

N

=

C

X

2

+

R

ω

O

1

X

O

R

ω

O

In these equations, Capacitance C

f

−+ω

GRC

N

(2)

is the total capacitance

X

appearing at the inverting terminal of the op amp. When
modeling a DAC buffer application, the Norton equivalent
circuit shown in Figure 32 can be used directly; Capacitance C
is the total capacitance of the output of the DAC plus the input
capacitance of the op amp (because the two are in parallel).

+

I

ORO

1/2

AD712

–

C

X

RLC

C

F

R

V

OUT

L

00823-032

Figure 32. Simplified Model of the AD712 Used as a Current-Out DAC Buffer

X

30

C

20

10

0

X

Figure 34. Value of Capacitor C

= 3.0

G

N

100

20 30 40 50

C

F

GN= 2.0

G

= 1.5

N

G

= 1.0

N

vs. Value of CX

F

60

00823-034

Rev. H | Page 12 of 20

AD712

The photos of Figure 35 and Figure 36 show the dynamic
response of the AD712 in the settling test circuit of Figure 37.

5V

100

90

5V

100

90

10
0%

10
0%

5mV

500ns

00823-035

5mV

Figure 36. Settling Characteristics 0 V to −10 V Step
Upper Trace: Output of AD712 Under Test (5 V/Div)

Lower Trace: Amplified Error Voltage (0.01%/Div)

500ns

00823-036

Figure 35. Settling Characteristics 0 V to +10 V Step

Upper Trace: Output of AD712 Under Test (5 V/Div)

Lower Trace: Amplified Error Voltage (0.01%/Div)

The input of the settling time fixture is driven by a flat top pulse
generator. The error signal output from the false summing node
of A1 is clamped, amplified by A2, and then clamped again. The
error signal is thus clamped twice: once to prevent overloading
Amplifier A2 and then a second time to avoid overloading the
oscilloscope preamp. The Tektronix oscilloscope preamp type
7A26 was carefully chosen because it does not overload with
these input levels. Amplifier A2 needs to be a very high speed
FET-input op amp; it provides a gain of 10, amplifying the error
signal output of A1.

DATA

DYNAMICS

5109

(OR EQUIVALENT
FLAT TOP PULSE
GENERATION)

5pF

+

1/2

A

D

7

1

HP2835

0.47µF

200Ω

10kΩ

–

1/2

AD712

+

4.99kΩ

5 TO 18pF

1.1kΩ

5kΩ

0.1µF

4.99kΩ

V

IN

10kΩ

0.1µF

–

–15V +15V

V

OUT

10pF

2

0.47µF

10kΩ

0.2 TO 0.6pF

205Ω

V

ERROR

×

HP2835

TEKTRONIX 7A26
OSCILLOSCOPE
PREAMP

5

INPUT SECTION

1MΩ

20pF

+15V

–15V

Figure 37. Settling Time Test Circuit

Rev. H | Page 13 of 20

0823-037

AD712

V

APPLICATIONS INFORMATION

GUARDING

The low input bias current (15 pA) and low noise characteristics
of the AD712 BiFET op amp make it suitable for electrometer
applications such as photo diode preamplifiers and picoampere
current-to-voltage converters. The use of a guarding technique,
such as that shown in Figure 38, in printed circuit board (PCB)
layout and construction is critical to minimize leakage currents.
The guard ring is connected to a low impedance potential at the
same level as the inputs. High impedance signal lines should
not be extended for any unnecessary length on the PCB.

PDIP (N), CERDIP (Q),

AND SOIC (R) PACKAGES.

4

3
2

1

Figure 38. Board Layout for Guarding Inputs

5

6

7

8

00823-038

DAC CONVERTER APPLICATIONS

The AD712 is an excellent output amplifier for CMOS DACs. It can
be used to perform both 2-quadrant and 4-quadrant operations.
The output impedance of a DAC using an inverted R-2R ladder
approaches R for codes containing many 1s, and 3R for codes
containing a single 1. For codes containing all 0s, the output
impedance is infinite.

For example, the output resistance of the AD7545 modulates
between 11 kΩ and 33 kΩ. Therefore, with an 11 kΩ DAC
internal feedback resistance, the noise gain varies from 2 to 4/3.
This changing noise gain modulates the effect of the input offset
voltage of the amplifier, resulting in nonlinear DAC amplifier
performance.

The AD712K with guaranteed 700 V offset voltage minimizes
this effect to achieve 12-bit performance.

R2*

R

FB

OUT1

AGND

DGND

Figure 40. Bipolar Operation

GAIN

ADJUST

V

IN

*FOR VALUES OF
R1 AND R2 SEE TABLE 3

R1*

V

DD

V

DD

AD7545

V

REF

DB11 TO DB0

12

DATA INPUT

C1
33pF

ANALOG
COMMON

Figure 39 and Figure 40 show the AD712 and AD7545 (12-bit
CMOS DAC) configured for unipolar binary (2-quadrant multi­plication) or bipolar (4-quadrant multiplication) operation.
Capacitor C1 provides phase compensation to reduce overshoot
and ringing.

R

DGND

R

DGND

FB

OUT1

AGND

FB

OUT1

AGND

R2A*

R2B*

C1A
33pF

ANALOG

COMMON

C1B
33pF

ANALOG

COMMON

+15V

–

1/2

AD712

+

–

1/2

AD712

+

–15V

0.1µF

0.1µF

V

IN

*REFER TO
TABLE 3

V

IN

*REFER TO
TABLE 3

GAIN

ADJUST

R1A*

GAIN

ADJUST

R1B*

DD

V

DD

AD7545

V

REF

DB11 TO DB0

V

DD

V

DD

AD7545

V

REF

DB11 TO DB0

Figure 39. Unipolar Binary Operation

R1 and R2 calibrate the zero offset and gain error of the DAC.
Specific values for these resistors depend upon the grade of
AD7545 and are listed in Table 3.

Table 3. Recommended Trim Resistor Values vs. Grades of
the AD7545 for V

= 5 V

DD

Trim
Resistor JN/AQ KN/BQ LN GLN

R1 500 Ω 200 Ω 100 Ω 20 Ω
R2 150 Ω 68 Ω 33 Ω 6.8 Ω

R4

R3

10kΩ 1%

20kΩ 1%

–

AD712

+

R5

20kΩ 1%

1/2

0.1µF

–15V

V

OUT

00823-040

+15V

–

1/2

AD712

+

0.1µF

V

V

OUTA

OUTB

00823-039

Rev. H | Page 14 of 20

AD712

A

Figure 41 and Figure 42 show the settling time characteristics of
the AD712 when used as a DAC output buffer for the AD7545.

1mV

100

90

10

0%

±10V

NALOG

INPUT

+15V

–

1/2

AD712

+

0.1µF

0.1µF

GAIN

ADJUST

R2

100Ω

R1

100Ω

OFFSET
ADJUST

12/8
CS

A

O

R/C
CE

REF IN

REF OUT

BIP OFF

10V

IN

20V

IN

AC DC

AD574A

MIDDLE

STS

HIGH

BITS

BITS

LOW
BITS

+5V
+15V
–15V

5V

500ns

00823-041

Figure 41. Positive Settling Characteristics for AD712 with AD7545

1mV

100

90

10

0%

5V

500ns

00823-042

Figure 42. Negative Settling Characteristics for AD712 with AD7545

NOISE CHARACTERISTICS

The random nature of noise, particularly in the flicker noise
region, makes it difficult to specify in practical terms. At the
same time, designers of precision instrumentation require
certain guaranteed maximum noise levels to realize the full
accuracy of their equipment. All grades of the AD712 are sample
tested on an AQL basis to a limit of 6 µV p-p, 0.1 Hz to 10 Hz.

DRIVING THE ANALOG INPUT OF AN ADC

An op amp driving the analog input of an ADC, such as that
shown in Figure 43, must be capable of maintaining a constant
output voltage under dynamically changing load conditions. In
successive approximation converters, the input current is compared
to a series of switched trial currents. The comparison point is
diode clamped, but can deviate several hundred millivolts resulting
in high frequency modulation of analog-to-digital input current.
The output impedance of a feedback amplifier is made artificially
low by the loop gain. At high frequencies, where the loop gain is
low, the amplifier output impedance can approach its open-loop
value. Most IC amplifiers exhibit a minimum open-loop output
impedance of 25 Ω due to current-limiting resistors.

–15V

ANALOG COM

Figure 43. AD712 as an ADC Unity-Gain Buffer

A few hundred microamps reflected from the change in converter
loading can introduce errors in instantaneous input voltage. If
the analog-to-digital conversion speed is not excessive and the
bandwidth of the amplifier is sufficient, the amplifier output
returns to the nominal value before the converter makes its
comparison. However, many amplifiers have relatively narrow
bandwidth yielding slow recovery from output transients. The
AD712 is ideally suited to drive high speed ADCs because it
offers both wide bandwidth and high open-loop gain.

1mV

100

90

10

0%

500mV

Figure 44. ADC Input Unity Gain Buffer Recovery Times, −10 V ADC IN

1mV

100

90

10
0%

500mV

Figure 45. ADC Input Unity Gain Buffer Recovery Times, −5 V ADC IN

PD711 BUFF

–10V ADC IN

PD711 BUFF

–5V ADC IN

200ns

200ns

00823-044

00823-045

00823-043

Rev. H | Page 15 of 20

AD712

DRIVING A LARGE CAPACITIVE LOAD

The circuit in Figure 46 uses a 100 Ω isolation resistor that enables
the amplifier to drive capacitive loads exceeding 1500 pF; the
resistor effectively isolates the high frequency feedback from
the load and stabilizes the circuit. Low frequency feedback is
returned to the amplifier summing junction via the low-pass filter
formed by the 100 Ω series resistor and the Load Capacitance C
Figure 47 shows a typical transient response for this connection.

4.99kΩ

30pF

+V

IN

0.1µF
+

–

4.99kΩ

INPUT

TYPICAL CAPACITANCE
LIMIT FOR VARIOUS
LOAD RESISTORS

UP TO

C

R

2kΩ 1500pF
10kΩ 1500pF
20Ω 1000pF

1

1

Figure 46. Circuit for Driving a Large Capacitive Load

–

1/2

AD712

+

–V

IN

0.1µF

–

100Ω

C1 R1

+

OUTPUT

.

L

5V

100

90

10

0%

Figure 47. Transient Response R

00823-046

1µs

= 2 kΩ, CL = 500 pF

L

00823-047

Rev. H | Page 16 of 20

AD712

m

FILTERS

R2

20kΩ

C1

560pF

+15V

0.1µF

+

C2

1/2

AD712

–

–15V

AD712

0.1µF

OFFSET .0 Hz

0dB

V

OUT

0823-048

ACTIVE FILTER APPLICATIONS

In active filter applications using op amps, the dc accuracy of
the amplifier is critical to optimal filter performance. The
amplifier offset voltage and bias current contribute to output
error. Offset voltage is passed by the filter and can be amplified
to produce excessive output offset. For low frequency applications
requiring large value input resistors, bias currents flowing
through these resistors also generate an offset voltage.

In addition, at higher frequencies, the op amp dynamics must
be carefully considered. Here, slew rate, bandwidth, and open­loop gain play a major role in op amp selection. The slew rate
must be fast as well as symmetrical to minimize distortion. The
amplifier bandwidth in conjunction with the filter gain dictates
the frequency response of the filter.

The use of a high performance amplifier such as the AD712
minimizes both dc and ac errors in all active filter applications.

SECOND-ORDER LOW-PASS FILTER

Figure 48 depicts the AD712 configured as a second-order,
Butterworth low-pass filter. With the values as shown, the
corner frequency is 20 kHz; however, the wide bandwidth of the
AD712 permits a corner frequency as high as several hundred
kilohertz. Equations for component selection are as follows:

R1 = R2 = A user selected value (10 kΩ to 100 kΩ, typical)

C1 (in farads) =

2RfC

=

707.0

()

()

π

cutoff

414.1

()

()

()

12

cutoff

Rf

π

()

12

R1

20kΩ

V

280pF

IN

Figure 48. Second-Order Low-Pass Filter

An important property of filters is their out-of-band rejection.
The simple 20 kHz low-pass filter shown in Figure 48, can be
used to condition a signal contaminated with clock pulses or
sampling glitches that have considerable energy content at high
frequencies.

The low output impedance and high bandwidth of the AD712
minimize high frequency feedthrough as shown in Figure 49.
The upper trace is that of another low cost BiFET op amp
showing 17 dB more feedthrough at 5 MHz.

REF 20.0 dB
10dB/DIV RANGE 15.0dBm

TYPI CA L BIFET

CENTER 5 000 000.0Hz
RBW 30kHz

Figure 49. High Frequency Feedthrough

VBW 30kHz

SPAN 10 000 000.0Hz

ST .8 SEC

00823-049

Rev. H | Page 17 of 20

AD712

V

V

IN

+15

0.1µF

+

A1

0.001µF

2800Ω 6190Ω 6490Ω 6190Ω 2800Ω

AD711
–

0.1µF

–15V

100kΩ

4.9395E

–15

A

*

5.9276E

SEE TEXT

*

–15

B

*

Figure 50. 9-Pole Chebychev Filter

9-POLE CHEBYCHEV FILTER

Figure 50 and Figure 51 show the AD712 and its dual counterpart,
the AD711, as a 9-pole Chebychev filter using active frequency
dependent negative resistors (FDNRs). With a cutoff frequency
of 50 kHz and better than 90 dB rejection, it can be used as an
antialiasing filter for a 12-bit data acquisition system with
100 kHz throughput.

5.9276E

–15

+15V

0.1µF

+

–15

4.9395E

C

*

D

++++

*

0.001µF

REF 5.0dBm
10dB/DIV RANGE –5.0dBm

124kΩ

A2

AD711

–

–15V

0.1µF

MARKER 96 800.0Hz

V

4.99kΩ

4.99kΩ

OUT

–90dBm

00823-050

As shown in Figure 50, the filter is comprised of four FDNRs
(A, B, C, D) having values of 4.9395 × 10

−15

and 5.9276 × 10

–15

farad-seconds. Each FDNR active network provides a two-pole
response for eight poles. The ninth pole consists of a 0.001 F
capacitor and a 124 kΩ resistor at Pin 3 of Amplifier A2. Figure 51
depicts the circuits for each FDNR with the proper selection of
R. To achieve optimal performance, the 0.001 µF capacitors
must be selected for 1% or better matching and all resistors
should have 1% or better tolerance.

+15V

+

1/2

AD712

–

–15V

0.1µF

0.1µF

–

1/2

AD712

+

R: 24.9kΩ FOR 4.9395E

29.4kΩ FOR 5.9276E

Figure 51. FDNR for 9-Pole Chebychev Filter

–15
–15

+

0.001µF

R

0.001µF

1.0kΩ

4.99kΩ

START.0Hz
RBW 300Hz

STOP 200 000.0Hz

ST 69.6 SECVBW 30Hz

00823-052

Figure 52. High Frequency Response for 9-Pole Chebychev Filter

0823-051

Rev. H | Page 18 of 20

AD712

OUTLINE DIMENSIONS

0.400 (10.16)

0.365 (9.27)

0.355 (9.02)

0.210 (5.33)

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

MAX

8

1

0.100 (2.54)

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

BSC

5

4

0.280 (7.11)

0.250 (6.35)

0.240 (6.10)

0.015
(0.38)
MIN

SEATING
PLANE

0.005 (0.13)
MIN

0.060 (1.52)
MAX

0.015 (0.38)
GAUGE

PLANE

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.430 (10.92)
MAX

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

CONTROLL ING DIMENSIONS ARE IN INCHES; MI LLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ON LY AND ARE NOT AP P RO PRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS W HO LE OR HALF LE ADS.

COMPLIANT TO JEDEC STANDARDS MS-001

070606-A

Figure 53. 8-Lead Plastic Dual In-Line Package [PDIP]

(N-8)

Dimensions shown in inches and (millimeters)

0.005 (0.13)

0.200 (5.08)
MAX

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 54. 8-Lead Ceramic Dual In-Line Package [CERDIP]

Dimensions shown in inches and (millimeters)

0.055 (1.40)

MIN

0.100 (2.54) BSC

0.405 (10.29) MAX

MAX

58

14

0.070 (1.78)

0.030 (0.76)

0.310 (7.87)

0.220 (5.59)

0.060 (1.52)

0.015 (0.38)

0.150 (3.81)
MIN

SEATING
PLANE

(Q-8)

0.320 (8.13)

0.290 (7.37)

15°

0°

0.015 (0.38)

0.008 (0.20)

Rev. H | Page 19 of 20

AD712

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES)ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.

5.00(0.1968)

4.80(0.1890)

85

1

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

BSC

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

8°
0°

1.27 (0.0500)

0.40 (0.0157)

45°

012407-A

Figure 55. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD712AQ −40°C to +85°C 8-Lead CERDIP Q-8
AD712JNZ 0°C to 70°C 8-Lead PDIP N-8
AD712JR 0°C to 70°C 8-Lead SOIC_N R-8
AD712JR-REEL 0°C to 70°C 8-Lead SOIC_N R-8
AD712JR-REEL7 0°C to 70°C 8-Lead SOIC_N R-8
AD712JRZ 0°C to 70°C 8-Lead SOIC_N R-8
AD712JRZ-REEL 0°C to 70°C 8-Lead SOIC_N R-8
AD712JRZ-REEL7 0°C to 70°C 8-Lead SOIC_N R-8
AD712KNZ 0°C to 70°C 8-Lead PDIP N-8
AD712KRZ 0°C to 70°C 8-Lead SOIC_N R-8
AD712KRZ-REEL 0°C to 70°C 8-Lead SOIC_N R-8
AD712KRZ-REEL7 0°C to 70°C 8-Lead SOIC_N R-8
AD712SQ/883B −55°C to +125°C 8-Lead CERDIP Q-8

1

Z = RoHS Compliant Part.

©1986–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00823-0-7/10(H)

Rev. H | Page 20 of 20