Datasheet AD708 Datasheet (ANALOG DEVICES)

Ultralow Offset Voltage

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FEATURES

Very high dc precision

30 μV maximum offset voltage

0.3 μV/°C maximum offset voltage drift

0.35 μV p-p maximum voltage noise (0.1 Hz to 10 Hz)
5 million V/V minimum open-loop gain
130 dB minimum CMRR
120 dB minimum PSRR

Matching characteristics

30 μV maximum offset voltage match

0.3 μV/°C maximum offset voltage drift match
130 dB minimum CMRR match

Available in 8-lead narrow body, PDIP, and

hermetic CERDIP and CERDIP/883B packages

GENERAL DESCRIPTION

The AD708 is a high precision, dual monolithic operational
amplifier. Each amplifier individually offers excellent dc
precision with maximum offset voltage and offset voltage drift
of any dual bipolar op amp.

The matching specifications are among the best available in any
d

ual op amp. In addition, the AD708 provides 5 V/V mini­mum open-loop gain and guaranteed maximum input voltage
noise of 350 nV p-p (0.1 Hz to 10 Hz). All dc specifications
show excellent stability over temperature, with offset voltage
drift typically 0.1 V/°C and input bias current drift of
25 pA/°C maximum.

The AD708 is available in four performance grades. The
AD708J is ra
0°C to 70°C and is available in a narrow body, PDIP. The
AD708A and AD708B are rated over the industrial temperature
range of −40°C to +85°C and are available in a CERDIP.

ted over the commercial temperature range of

Dual Op Amp

AD708

PIN CONFIGURATION

AD708

–IN A

+IN A

–V

S

1

2

3

4

–

A

+

TOP VIEW

(Not to Scale)

+V

8

S

OUTPUT B

7

–IN B

6

–

B

+

+IN B

5

05789-001

V/µV typical open-loop gain and 140 dB

OUTPUT A

Figure 1. PDIP (N) and CERDIP (Q) Packages

The AD708S is rated over the military temperature range of

o +125°C and is available in a CERDIP military version

−55°C t
processed to MIL-STD-883B.

PRODUCT HIGHLIGHTS

1. The combination of outstanding matching and individual

specifications make the AD708 ideal for constructing high
gain, precision instrumentation amplifiers.

2. The lo

3. The AD708 10

w offset voltage drift and low noise of the AD708
allow the designer to amplify very small signals without
sacrificing overall system performance.

common-mode rejection make it ideal for precision
applications.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

AD708

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TABLE OF CONTENTS

Features .............................................................................................. 1

Theory of Operation ...................................................................... 10

Pin Configuration............................................................................. 1

General Description......................................................................... 1

Product Highlights........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Typical Performance Characteristics............................................. 6

Matching Characteristics............................................................. 9

REVISION HISTORY

1/06—Rev. B to Rev. C

Updated Format..................................................................Universal

moved TO-99 Package ..................................................Universal

Re

Deleted AD707 References................................................Universal

Deleted LT1002 Reference............................................................... 1

Deleted Figure 1................................................................................ 1

Deleted Metalization Photograph .................................................. 5

Moved Figure 25, Figure 26, and Figure 27

to Theory of Operation section .................................................... 10

Updated Outline Dimensions....................................................... 13

Changes to Ordering Guide.......................................................... 13

Crosstalk Performance .............................................................. 10

Operation with a Gain of −100................................................. 11

High Precision Programmable Gain Amplifier ..................... 11

Bridge Signal Conditioner......................................................... 12

Precision Absolute Value Circuit ............................................. 12

Selection of Passive Components............................................. 12

Outline Dimensions ....................................................................... 13

Ordering Guide .......................................................................... 13

2/91—Rev. A to Rev. B

Rev. C | Page 2 of 16

AD708

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SPECIFICATIONS

@ 25°C and ±15 V dc, unless otherwise noted.

Table 1.

AD708J/AD708A AD708B AD708S
Parameter Conditions Min1Typ Max1Min1Typ Max1Min1Typ Max1Unit

INPUT OFFSET VOLTAGE
T

Drift 0.3 1.0 0.1 0.4 0.1 0.3 μV/°C

Long Term Stability 0.3 0.3 0.3 μV/month
INPUT BIAS CURRENT 1.0
T

Average Drift 15 40 10 25 10 30 pA/°C
OFFSET CURRENT VCM = 0 V 0.5
T
Average Drift 2 60 1 25 1 25 pA/°C
MATCHING CHARACTERISTICS3

Offset Voltage

T

Offset Voltage Drift 1.0 0.4

Input Bias Current

T

Common-Mode Rejection

T

Power Supply Rejection

T

Channel Separation 135 140 140 dB
INPUT VOLTAGE NOISE 0.1 Hz to 10 Hz 0.23 0.6 0.23 0.6 0.23
f = 10 Hz 10.3 18 10.3 12 10.3 12 nV/√Hz
f = 100 Hz 10.0 13.0 10.0 11.0 10.0 11 nV/√Hz
f = 1 kHz 9.6 11.0 9.6 11.0 9.6 11 nV/√Hz
INPUT CURRENT NOISE 0.1 Hz to 10 Hz 14 35 14 35 14 35 pA p-p
f = 10 Hz 0.32 0.9 0.32 0.8 0.32 0.8 pA/√Hz
f = 100 Hz 0.14 0.27 0.14 0.23 0.14 0.23 pA/√Hz
f = 1 kHz 0.12 0.18 0.12 0.17 0.12 0.17 pA/√Hz
COMMON-MODE REJECTION RATIO VCM = ±13 V

T
OPEN-LOOP GAIN VO = ±10 V
R
T
POWER SUPPLY REJECTION RATIO VS = ±3 V to ±18 V

T
FREQUENCY RESPONSE

Closed-Loop Bandwidth 0.5 0.9 0.5 0.9 0.5 0.9 MHz
Slew Rate 0.15 0.3 0.15 0.3 0.15 0.3 V/μs

INPUT RESISTANCE

Differential 60 200 200 MΩ
Common Mode 200 400 400 GΩ

2

30

MIN

to T

MAX

50 150 15 65 15 50 μV

100

2.5

MIN

to T

MAX

2.0 4.0 1.0

2.0

MIN

to T

MAX

2.0 4.0 0.2 1.5 0.2

80

to T

MIN

150 75

MAX

4.0

MIN

MIN

MIN

MIN

LOAD

MIN

MIN

to T

MAX

to T

MAX

to T

MAX

to T

MAX

≥ 2 kΩ

to T

MAX

to T

MAX

5.0 2.0

120

140

110 130

110

110 120

120

140

120 140 130 140

3

10

3 10 5 10

110

130

110 130 120 130

5

0.5

0.1

50

130

120

130

5

120

50

1.0

2.0

1.0

1.0

140

140

10

130

5

0.5

1.0

0.1

30

1
4

1

1.5

30
50

0.3

1.0

2.0

140 dB

130

dB

130

dB

120

dB

120

0.35

140 dB

130

140 dB

130

10 V/μV

4

7 V/μV

4

130 dB

120

130 dB

120

μV

nA
nA

nA
nA

μV
μV
μV/°C
nA
nA

μV p-p

Rev. C | Page 3 of 16

AD708

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AD708J/AD708A AD708B AD708S
Parameter Conditions Min1Typ Max1Min1Typ Max1Min1Typ Max1Unit

OUTPUT VOLTAGE R
R
R
T
OPEN-LOOP OUTPUT RESISTANCE 60 60 60 Ω
POWER SUPPLY

Quiescent Current 4.5 5.5 4.5 5.5 4.5 5.5 mA
Power Consumption VS = ±15 V 135

V

Operating Range ±3 ±18 ±3 ±18 ±3 ±18 V

1

All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to

calculate outgoing quality levels.

2

Input offset voltage specifications are guaranteed after five minutes of operation at TA = 25°C.

3

Matching is defined as the difference between parameters of the two amplifiers.

≥ 10 kΩ

LOAD

≥ 2 kΩ

LOAD

≥ 1 kΩ

LOAD

to T

MIN

MAX

= ±3 V 12

S

13.5

12.5

12.0

12.0 13.0 12.0 13.0

14

13.0

12.5

165
18

14.0

13.5

13.0

12.5

12.5

12.0

135
12

165
18

14 ±V

13.5

13 ±V

12.5

12.5 ±V

12.0

13 ±V

12.0

135
12

165
18

mW
mW

Rev. C | Page 4 of 16

AD708

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ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage ±22 V
Internal Power Dissipation
Input Voltage
Output Short-Circuit Duration Indefinite
Differential Input Voltage +VS and −V
Storage Temperature Range (Q) −65°C to +150°C
Storage Temperature Range (N) −65°C to +125°C
Lead Temperature (Soldering 60 sec) 300°C

1

Thermal Characteristics

8-lead PDIP: θ
8-lead CERDIP: θJC = 30°C/W, θJA = 110°C/W

2

For supply voltages less than ±22 V, the absolute maximum input voltage is

equal to the supply voltage.

2

= 33°C/W, θJA = 100°C/W

JC

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

1

±V

S

S

Stresses above those listed under Absolute Maximum Ratings
ma

y cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. C | Page 5 of 16

AD708

V

V

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TYPICAL PERFORMANCE CHARACTERISTICS

VS = ±15 V and TA = 25°C, unless otherwise noted.

+

S

–0.5

–1.0

+V

8

7

6

–1.5

1.5

1.0

COMMON-MODE VOLTAGE LIMIT (V)

(REFERRED TO SUPPLY VOLTAGES)

0.5

–V

S

0 5 10 15 20 25

–V

SUPPLY VOLTAGE (±V)

Figure 2. Input Common-Mode Range vs. Supply Voltage

+

S

–0.5

–1.0

–1.5

1.5

1.0

OUTPUT VOLT AGE SWING (±V)

(REFERRED TO SUPPLY VOLTAGES)

0.5

–V

S

0 5 10 15 20 25

+V

OUT

–V

OUT

SUPPLY VOLTAGE (±V)

RL = 10k
RL = 2k

Figure 3. Output Voltage Swing vs. Supply Voltage

35

30

25

20

15

10

OUTPUT VO LTAGE ( V p-p)

5

±15V SUPPLIES

5

4

3

SUPPLY CURRENT (mA)

2

1

05789-002

0

0221181512963

SUPPLY VOLTAGE (±V)

05789-005

4

Figure 5. Supply Current vs. Supply Voltage

100

256 UNITS TESTED
–55°C TO +125°C

90

80

70

60

50

40

NUMBER OF UNITS

30

20

10

05789-003

0
–0.4 0.40.30.20.10–0.1–0.2–0. 3

OFFSET VOLTAGE DRIFT (µV/°C)

05789-006

Figure 6. Typical Distribution of Offset Voltage Drift

100

0.01

OUTPUT IMPEDANCE ()

0.001

0.1

I

= 1mA

O

10

AV = +1000

1

A

= +1

V

0

10 100 1k 10k

LOAD RESIST ANCE ()

Figure 4. Output Voltage Swing vs. Load Resistance

05789-004

0.0001

0.1 100k

Figure 7. Output Impedance vs. Frequency

Rev. C | Page 6 of 16

FREQUENCY (Hz)

10k1k100101

05789-007

AD708

T

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40

16

35

30

25

20

15

BIAS CURRENT (mA)

10

INVERTING OR NONINVERT ING INPU

5

0

0 1 10 100

DIFFERENTIAL VOLTAGE (±V)

Figure 8. Input Bias Current vs. Differential Input Voltage

45

40

35

30

25

20

15

10

INPUT VOLTAGE NO ISE (nV/ Hz)

5

0

0.1 1 10 100

1/F CORNER

0.7Hz

FREQUENCY (Hz)

Figure 9. Input Noise Spectral Density

14

12

10

8

6

OPEN-LOOP GAIN (V/µV)

4

2

05789-008

0

–60 140120100806040200–20–40

TEMPERATURE ( °C)

V

OUT

RL = 10k
RL = 2k

= ±10V

05789-011

Figure 11. Open-Loop Gain vs. Temperature

16

14

12

10

8

6

OPEN-LOOP GAIN (V/µV)

4

2

05789-009

0

022015105

R

= 2k

LOAD

SUPPLY VOLTAGE (V)

05789-012

5

Figure 12. Open-Loop Gain vs. Supply Voltage

1s

VOLTAGE NOISE (100nV/DIV)

TIME (1s/ DIV)

05789-010

Figure 10. 0.1 Hz to 10 Hz Voltage Noise

140

120

100

80

60

40

OPEN-LOOP GAIN (dB)

20

0

–20

Figure 13. Open-Loop Gain and Phase vs. Frequency

Rev. C | Page 7 of 16

FREQUENCY (Hz)

RL = 2k
C

L

PHASE

MARGIN = 43°

GAIN

= 1000pF

0

30

60

90

120

150

PHASE (Degrees)

180

05789-013

10M1M100k10k1k1001010.10.01

AD708

www.BDTIC.com/ADI

160

140

120

100

80

60

40

COMMON-MO DE REJECTIO N (dB)

20

0

35

30

25

20

0.1 1M100k10k1k100101

FREQUENCY (Hz)

Figure 14. Common-Mode Rejection vs. Frequency

F

MAX

= 2.8kHz

RL = 2k

V

25°C
= ±15V

S

2mV/DIV

CH1

05789-014

TIME (2µs/DIV)

05789-017

Figure 17. Small Signal Transient Response; A

2mV/DIV

= +1, RL = 2 kΩ, CL = 50 pF

V

15

10

OUTPUT VO LTAGE ( V p-p)

5

0

1k 1M100k10k

FREQUENCY (Hz)

Figure 15. Large Signal Frequency Response

160

140

120

100

80

60

40

POWER SUPPLY REJECTI ON (dB)

20

0

0.001 0.01 0.1 1 10 100 1k 10k 100k

FREQUENCY (Hz)

Figure 16. Power Supply Rejection vs. Frequency

CH1

05789-015

TIME (2µs/DIV)

05789-018

Figure 18. Small Signal Transient Response; A

= +1, RL = 2 kΩ, CL = 1000 pF

V

05789-016

Rev. C | Page 8 of 16

AD708

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MATCHING CHARACTERISTICS

32

25°C

28

16

14

24

20

16

12

8

PERCENTAGE OF UNITS (%)

4

0

–50 –40 –30 –20 –10 0 10 20 30 40 50

OFFSET VOLTAGE MATCH (µV)

Figure 19. Typical Distribution of Offset Voltage Match

32

–55°C TO +125°C

28

24

20

16

12

8

PERCENTAGE OF UNITS (%)

4

0
–0.5 –0.4 –0.3 –0.2 –0. 1 0 0.1 0.2 0.3 0. 4 0.5

OFFSET DRIFT MATCH (µV/°C)

12

10

8

6

4

PERCENTAGE OF UNITS (%)

2

05789-019

0
–1.0 –0. 8 –0.6 –0.4 –0.2 0 0.2 0. 4 0.6 0.8 1.0

OFFSET CURRENT MATCH (n A)

05789-022

Figure 22. Typical Distribution of Input Offset Current Match

160

140

120

100

80

60

PSRR MATCH (dB)

40

20

05789-020

0

–60 –40 –20 0 20 40 60 80 100 120 140

TEMPERATURE (°C)

05789-023

Figure 20. Typical Distribution of Offset Voltage Drift Match

16

14

12

10

8

6

4

PERCENTAGE OF UNITS (%)

2

0
–1.0 –0. 8 –0.6 –0.4 –0.2 0 0.2 0. 4 0.6 0.8 1.0

INPUT BIAS CURRENT MATCH (nA)

Figure 21. Typical Distribution of Input Bias Current Match

05789-021

Rev. C | Page 9 of 16

Figure 23. PSRR Match vs. Temperature

160

140

120

100

80

60

CMRR MATCH (dB)

40

20

0

–60 –40 –20 0 20 40 60 80 100 120 140

TEMPERATURE (°C)

Figure 24. CMRR Match vs. Temperature

05789-024

AD708

V

V

V

A

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THEORY OF OPERATION

CROSSTALK PERFORMANCE

The AD708 exhibits very low crosstalk as shown in Figure 25,
Figure 26, and Figure 27. Figure 25 shows the offset voltage

uced on Side B of the AD708 when Side A output is moving

ind
slowly (0.2 Hz) from −10 V to +10 V under no load. This is the
least stressful situation to the part because the overall power in
the chip does not change. Only the location of the power in the
output device changes.

nge to Side B when Side A is driving a 2 k load. Here the

cha
power changes in the chip with the maximum power change
occurring at 7.5 V.
s

evere conditions. Side A is connected as a follower with
0 V input, and is forced to sink and source ±5 mA of output
current.

Power = (30 V)(5 mA) = 150 mW

Even this large change in power causes only an 8 V (linear)
c

hange in the input offset voltage of Side B.

Figure 26 shows the input offset voltage

Figure 27 shows crosstalk under the most

VIN= ±10V

10 10

= 1µV/DI

OSB

V

AV

10k

BV

OUTA

2k

OUTB

2V

VIN= ±10V

AV

10k

OUTA

V

OUTA

= 2V/DIV

05789-026

Figure 26. Crosstalk with 2 kΩ Load

BV

10 10

= 1µV/DI

OSB

V

V

= 2V/DIV

OUTA

Figure 25. Crosstalk with No Load

OUTB

I

= ±5m

IN

A

2V

BV

10 10

05789-025

= 2µV/DI

OSB

V

10k

2k

V

2V

IN

OUTB

= ±10V

INA = 1mA/DIV

Figure 27. Crosstalk Under Forced Source and Sink Conditions

Rev. C | Page 10 of 16

05789-027

AD708



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OPERATION WITH A GAIN OF −100

To show the outstanding dc precision of the AD708 in a real
application, Tab l e 3 shows an error budget calculation for a gain

f −100. This configuration is shown in Figure 28.

o

Table 3.

Error Sources

VOS 30 μV/100 mV = 300 ppm
IOS (100 kΩ)(1 nA)/10 V = 10 ppm
Gain (2 kΩ Load) 10 V/(5 × 106)/100 mV = 20 ppm
Noise 0.35 mV/100 mV = 4 ppm
VOS Drift (0.3 mV/°C)/100 mV = 3 ppm/°C

Total Unadjusted

Error @ 25°C = 334 ppm > 11 bits

−55°C to +125°C = 634 ppm > 10 bits

With Offset

Calibrated Out @ 25°C = 34 ppm > 14 bits

−55°C to +125°C = 334 ppm > 11 bits

Maximum Error Contribution
A

= 100 (S Grade)

V

(Full Scale: V

= 10 V, VIN = 100 mV)

OUT

100k

+V

S

0.1µF

1k

V

IN

–

2

7

1/2

AD708

4

3

+

1k

0.1µF

–V

S

Figure 28. Gain of −100 Configuration

6

V

OUT

5789-028

This error budget assumes no error in the resistor ratio and no
error from power supply variation (the 120 dB minimum PSRR
of the AD708S makes this a good assumption). The external
resistors can cause gain error from mismatch and drift over
temperature.

HIGH PRECISION PROGRAMMABLE GAIN AMPLIFIER

The three op amp programmable gain amplifier shown in
Figure 29 takes advantage of the outstanding matching

haracteristics of the AD708 to achieve high dc precision.

c

1/2

V

INA

A0

A1

–V

S

+V

S

V

INB

AD708

OUT

1–4

AD7502

OUT

5–8

AD708

1/2

S1

S2

S3

S4

S8

S7

S6

S5

10k

100

10k

10k

26.1

1k

10k

26.1

10k

10k

10k

9.9k R

10k

10k

26.1

9.9k

R

A

AD707

B

Figure 29. Precision PGA

The gains of the circuit are controlled by the select lines, A0 and
A1, of the AD7502 multiplexer, and are 1, 10, 100, and 1000 in

is design.

th

The input stage attains very high dc precision due to the 30 V

um offset voltage match of the AD708S and the 1 nA

maxim
maximum input bias current match. The accuracy is main­tained over temperature because of the ultralow drift
performance of the AD708.

To achieve 0.1% gain accuracy, along with high common-mode

jection, the circuit should be trimmed.

re

To maximize common-mode rejection

1. S

et the select lines for gain = 1 and ground V

pply a precision dc voltage to V

2. A

V

3. Co

= −V

O

nnect V

to the required precision.

INA

to V

INB

and apply an input voltage equal to

INA

and trim RA until

INA

INB

.

the full-scale common mode expected.

4. Tr

im R

until VB

B

= 0 V.

O

To minimize gain errors

elect gain = 10 with the control lines and apply a

1. S

differential input voltage.

2. A

djust the 100  potentiometer to V

(adjust V

magnitude as necessary).

IN

= 10 VIN

O

05789-029

3. Rep

eat Step 1 and Step 2 for gain = 100 and gain = 1000,

adjusting the 1 k and 10 k potentiometers, respectively.

The design shown in Figure 29 should allow for 0.1% gain
acc

uracy and 0.1 V/V common-mode rejection when ±1%

resistors and ±5% potentiometers are used.

Rev. C | Page 11 of 16

AD708

V

V

()(

)

+

()(

)

+

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BRIDGE SIGNAL CONDITIONER

The AD708 can be used in the circuit shown in Figure 30 to
produce an accurate and inexpensive dynamic bridge condi­tioner. The low offset voltage match and low offset voltage drift
match of the AD708 combine to achieve circuit performance
better than all but the best instrumentation amplifiers. The
outstanding specifications of the AD708, such as open-loop
gain, input offset currents, and low input bias currents, do not
limit circuit accuracy.

As configured, the circuit only requires a gain resistor, R
suitable accuracy and a stable, accurate voltage reference. The
transfer function is

= V

V

[∆R/(R + ∆R)][RG/R]

O

REF

The only significant errors due to the AD708S are

V

= (V

OS_OUT

V

(T) = (V

OS_OUT

To achieve high accuracy, Resistor R

)(2RG/R) = 30 mV

OS_MATCH

OS_DRIFT

)(2RG/R) = 0.3 mV/°C

should be 0.1% or better

G

with a low drift coefficient.

+15

AD580

2.5V

V

REF

R

R = 350

R

R + R

R

G

175k

AD708

1/2

, of

G

V

O

AD708 enab

les this circuit to accurately resolve the input signal.
In addition, the tight offset voltage drift match maintains the
resolution of the circuit over the full military temperature
range. The high dc open-loop gain and exceptional gain
linearity allows the circuit to perform well at both large and
small signal levels.

In this circuit, the only significant dc errors are due to the offset
v

oltage of the two amplifiers, the input offset current match of
the amplifiers, and the mismatch of the resistors. Errors
associated with the AD708S contribute less than 0.001% error
over −55°C to +125°C.

Maximum error at 25°C

nA1k10V30

V10

==

ppm4VV/1040

Maximum error at +125°C or −55°C

Figure 32 shows V

k10nA2V50

V10

vs. VIN for this circuit with a ±3 mV input

OUT

°+=

C125@ppm7

signal at 0.05 Hz. Note that the circuit exhibits very low offset at
the zero crossing. This circuit can also produce V

= −|VIN| by

OUT

reversing the polarity of the two diodes.

1mV1mV

1/2

AD708

887

–15V

Figure 30. Bridge Signal Conditioning Circuit

10k 10k

10k 5k

1

IN459

10k

IN

5k

Figure 31. Precision Absolute Value Circuit

1/2

AD708

NOTE

1

LOW LEAKAGE DIODES

IN459

3.75k

1

1/2

AD708

5789-030

VO = |VIN|

05789-031

PRECISION ABSOLUTE VALUE CIRCUIT

The AD708 is ideally suited to the precision absolute value
circuit shown in Figure 31. The low offset voltage match of the

= 1mV/DI

OUT

V

VIN = 1mV/DIV

Figure 32. Absolute Value Circuit Performance

Signal = 0.05 Hz)

(Input

05789-032

SELECTION OF PASSIVE COMPONENTS

Use high quality passive components to take full advantage of
the high precision and low drift characteristics of the AD708.
Discrete resistors and resistor networks with temperature
coefficients of less than 10 ppm/°C are available from Vishay,
Caddock, Precision Replacement Parts (PRP), and others.

Rev. C | Page 12 of 16

AD708

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

0.400 (10.16)

0.365 (9.27)

0.355 (9.02)

8

5

0.280 (7.11)

4

0.250 (6.35)

0.240 (6.10)

0.015
(0.38)
MIN

SEATING
PLANE

0.005 (0.13)
MIN

0.060 (1.52)
MAX

0.015 (0.38)
GAUGE

PLANE

1

PIN 1

0.100 (2.54)

0.210

(5.33)

MAX

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

BSC

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

COMPLIANT TO JEDEC STANDARDS MS-001-BA

Figure 33. 8-Lead Plastic Dual In-Line Package [PDIP]

row Body

Nar

(N-8)

Dimensions shown in inches and (millimeters)

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.430 (10.92)
MAX

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

0.005 (0.13)

0.200 (5.08)
MAX

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

0.055 (1.40)

MIN

14

0.100 (2.54) BSC

0.405 (10.29) MAX

MAX

0.070 (1.78)

0.030 (0.76)

58

0.310 (7.87)

0.220 (5.59)

0.060 (1.52)

0.015 (0.38)

0.150 (3.81)
MIN

SEATING
PLANE

0.320 (8.13)

0.290 (7.37)

15°

0°

0.015 (0.38)

0.008 (0.20)

Figure 34. 8-Lead Ceramic Dual In-Line Package [CERDIP]

(Q-8)

Dim

ensions shown in inches and (millimeters)

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD708JN 0°C to +70°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
AD708JNZ
AD708AQ −40°C to +85°C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8
AD708BQ −40°C to +85°C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8
AD708SQ/883B −55°C to +125°C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8

1

Z = Pb-free part.

1

0°C to +70°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8

Rev. C | Page 13 of 16

AD708

www.BDTIC.com/ADI

NOTES

Rev. C | Page 14 of 16

AD708

www.BDTIC.com/ADI

NOTES

Rev. C | Page 15 of 16

AD708

www.BDTIC.com/ADI

NOTES

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C05789-0-1/06(C)

Rev. C | Page 16 of 16