ANALOG DEVICES AD6659 Service Manual

A
VDDA
Dual IF Receiver

FEATURES

12-bit, 80 MSPS output data rate per channel
1.8 V analog supply operation (AVDD)
1.8 V to 3.3 V output supply (DRVDD) Integrated noise shaping requantizer (NSR) Integrated quadrature error correction (QEC) Performance with NSR enabled
SNR = 81 dBFS in 16 MHz band up to 30 MHz at 80 MSPS
Performance with NSR disabled
SNR = 72 dBFS up to 70 MHz at 80 MSPS
SFDR = 90 dBc up to 70 MHz input at 80 MSPS Low power: 98 mW per channel at 80 MSPS Differential input with 700 MHz bandwidth On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input Serial port control options
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-6 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data alignment

APPLICATIONS

Communications Diversity radio systems Multimode digital receivers
3G, W-CDMA, LTE, CDMA2000, TD-SCDMA, MC-GSM I/Q demodulation systems Smart antenna systems Battery-powered instruments General-purpose software radios
AD6659

FUNCTIONAL BLOCK DIAGRAM

GND SDIO SCLKCSB
SPI
PROGRAMMI NG DATA
QUADRATURE
VIN+A VIN–A
VREF
SENSE
VCM
RBIAS
VIN+B VIN–B
CLK+ CLK– DCS DFS
16 12
ADC
REF
SELECT
ADC
ERROR AND
DC OFFSET
CORRECTION
QUADRATURE
16 12
ERROR AND
DC OFFSET
CORRECTION
DUTY CYCLE
DIVIDE
STABILIZER
1TO 6
SYNC PDWN OEB
NOISE
SHAPING
REQUANTIZER
AD6659
NOISE
SHAPING
REQUANTIZER
MUX OPTION
MODE
CONTROLS
Figure 1.

PRODUCT HIGHLIGHTS

1. The AD6659 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.
2. SPI-selectable noise shaping requantizer (NSR) function
that allows for improved SNR within a reduced bandwidth of up to 70 MHz at 80 MSPS.
3. SPI-selectable dc correction and quadrature error
correction (QEC) that corrects for dc offset, gain, and phase mismatches between the two channels.
4. A standard serial port interface supports various product
features and functions, such as data output formatting, internal clock divider, power-down, DCO/data timing, offset adjustments, and voltage reference modes.
5. The AD6659 is packaged in a 64-lead RoHS-compliant
LFCSP that is pin compatible with the AD9269 16-bit ADC, the AD9268 16-bit ADC, the AD9258 14-bit ADC, the AD9251 14-bit ADC, the AD9231 12-bit ADC, and the
AD9204 10-bit ADC, enabling a simple migration path
between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.
ORA D11A (MSB)
D0A (LSB) DCOA
CMOS OUT P UT BUFFER
DRVDD
ORB D11B (MSB)
D0B (LSB) DCOB
CMOS OUT P UT BUFFER
08701-001
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.
AD6659

TABLE OF CONTENTS

Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications ..................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications .......................................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
Timing Specifications .................................................................. 8
Absolute Maximum Ratings ............................................................ 9
Thermal Characteristics .............................................................. 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 12
Equivalent Circuits ......................................................................... 14
Theory of Operation ...................................................................... 16
ADC Architecture ...................................................................... 16
Analog Input Considerations .................................................... 16
Voltage Reference ....................................................................... 19
Clock Input Considerations ...................................................... 20
Power Dissipation and Standby Mode ..................................... 21
Digital Outputs ........................................................................... 22
Timing ......................................................................................... 22
Built-In Self-Test and Output Test ............................................... 24
BIST .............................................................................................. 24
Output Test Modes ..................................................................... 24
Channel/Chip Synchronization .................................................... 25
Noise Shaping Requantizer (NSR) ............................................... 26
20% BW NSR Mode (16 MHz BW at 80 MSPS) .................... 26
DC and Quadrature Error Correction (QEC) ............................ 27
Serial Port Interface (SPI) .............................................................. 29
Configuration Using the SPI ..................................................... 29
Hardware Interface ..................................................................... 30
Configuration Without the SPI ................................................ 30
SPI Accessible Features .............................................................. 30
Memory Map .................................................................................. 31
Reading the Memory Map Register Table ............................... 31
Open Locations .......................................................................... 31
Default Values ............................................................................. 31
Memory Map Register Table ..................................................... 32
Memory Map Register Descriptions ........................................ 35
Applications Information .............................................................. 37
Design Guidelines ...................................................................... 37
Outline Dimensions ....................................................................... 38
Ordering Guide .......................................................................... 38

REVISION HISTORY

2/10Rev. 0 to Rev. A
Changes to Title ................................................................................ 1
Changes to Features Section............................................................ 1
Changes to General Description Section ...................................... 3
1/10—Revision 0: Initial Version
Rev. A | Page 2 of 40
AD6659

GENERAL DESCRIPTION

The AD6659 is a mixed-signal, dual-channel IF receiver support­ing radio topologies requiring two receiver signal paths, such as in main/diversity or direct conversion. This communications systems processor consists of two high performance analog-to­digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. It is designed to support various communications applications where high dynamic range performance and small size are desired.
The high dynamic range ADC core features a multistage differen­tial pipelined architecture with integrated output error correction logic. Each ADC features a wide bandwidth switch capacitor sampling network within the first stage of the differential pipe­line. An integrated voltage reference eases design considerations.
Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist region. The device supports two different output modes selectable via the serial port interface (SPI).
With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6659 supports enhanced SNR performance within a limited region of the Nyquist bandwidth while maintaining a 12-bit output resolution. The NSR block is programmed to provide a bandwidth of 20% of the sample clock. For example, with a sample clock rate of 80 MSPS, the AD6659 can achieve up to 81.5 dBFS SNR for a 16 MHz bandwidth at 9.7 MHz AIN.
With the NSR block disabled, the ADC data is provided directly to the output with an output resolution of 12 bits. The AD6659 can achieve up to 72 dBFS SNR for the entire Nyquist bandwidth when operated in this mode.
After digital processing, output data is routed into two 12-bit output ports that support 1.8 V or 3.3 V CMOS levels.
The AD6659 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of the main and diversity channel. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods.
The AD6659 also incorporates an optional integrated dc offset correction and quadrature error correction (QEC) block that corrects for gain and phase mismatch between the two channels. This functional block proves invaluable in complex signal processing applications such as direct conversion receivers.
The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).
A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.
The digital output data is presented in offset binary, gray code, or twos complement format. A data clock output (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported, and output data can be multiplexed onto a single output bus.
The AD6659 is available in a 64-lead, RoHS-compliant LFCSP, and it is specified over the industrial temperature range (−40°C to +85°C).
Rev. A | Page 3 of 40
AD6659

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted.
Table 1.
Parameter Temp Min Typ Max Unit
RESOLUTION Full 12 Bits ACCURACY
No Missing Codes Full Guaranteed Offset Error Full ±0.05 ±0.5 % FSR Gain Error1 Full −1.9 % FSR Differential Nonlinearity (DNL)2 Full ±0.30 LSB 25°C ±0.13 LSB Integral Nonlinearity (INL)2 Full ±0.40 LSB 25°C ±0.17 LSB
MATCHING CHARACTERISTICS
Offset Error 25°C ±0.0 ±0.65 % FSR Gain Error1 25°C 0.4 % FSR
TEMPERATURE DRIFT
Offset Error Full ±2 ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode) Full 0.981 0.993 1.005 V Load Regulation Error at 1.0 mA Full 2 mV
INPUT REFERRED NOISE
VREF = 1.0 V 25°C 0.25 LSB rms
ANALOG INPUT
Input Span, VREF = 1.0 V Full 2 V p-p Input Capacitance3 Full 6.5 pF Input Common-Mode Voltage Full 0.9 V
Input Common-Mode Range Full 0.5 1.3 V REFERENCE INPUT RESISTANCE Full 7.5 kΩ POWER SUPPLIES
Supply Voltage
AVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 3.6 V
Supply Current
IAVDD2 Full 113 119 mA IDRVDD2 (1.8 V) Full 9.3 mA IDRVDD2 (3.3 V) Full 18.5 mA
POWER CONSUMPTION
DC Input Full 196 mW
Sine Wave Input2 (DRVDD = 1.8 V) Full 220 240 mW
Sine Wave Input2 (DRVDD = 3.3 V) Full 264 mW
Standby Power4 Full 37 mW
Power-Down Power Full 1.0 mW
1
Measured with 1.0 V external reference.
2
Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
4
Standby power is measured with a dc input and the CLK active.
Rev. " | Page 4 of 40
AD6659

AC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted.
Table 2.
Parameter1 Temp Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR)—NSR DISABLED
fIN = 9.7 MHz 25°C 72.4 dBFS fIN = 30.5 MHz 25°C 72.3 dBFS fIN = 70 MHz 25°C 72.0 dBFS Full 71.4 dBFS
SIGNAL-TO-NOISE RATIO (SNR)—NSR ENABLED
20% Bandwidth (16 MHz @ 80 MSPS) fIN = 9.7 MHz 25°C 81.5 dBFS fIN = 30.5 MHz 25°C 81.2 dBFS fIN = 70 MHz 25°C 80.3 dBFS
SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)
fIN = 9.7 MHz 25°C 72.4 dBFS fIN = 30.5 MHz 25°C 72.2 dBFS fIN = 70 MHz 25°C 71.9 dBFS Full 71.5 dBFS
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 9.7 MHz 25°C 11.7 Bits fIN = 30.5 MHz 25°C 11.7 Bits fIN = 70 MHz 25°C 11.7 Bits
WORST SECOND OR THIRD HARMONIC
fIN = 9.7 MHz 25°C −93 dBc fIN = 30.5 MHz 25°C −92 dBc fIN = 70 MHz 25°C −90 dBc Full −80 dBc
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 9.7 MHz 25°C 93 dBc fIN = 30.5 MHz 25°C 92 dBc fIN = 70 MHz 25°C 90 dBc Full 80 dBc
WORST OTHER (HARMONIC OR SPUR)
fIN = 9.7 MHz 25°C −99 dBc fIN = 30.5 MHz 25°C −99 dBc fIN = 70 MHz 25°C −98 dBc Full −91 dBc
TWO-TONE SFDR
fIN = 28.3 MHz (−7 dBFS), 30.6 MHz (−7 dBFS) 25°C 90 dBc CROSSTALK2 Full −110 dBc ANALOG INPUT BANDWIDTH 25°C 700 MHz
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2
Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.
Rev. " | Page 5 of 40
AD6659

DIGITAL SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted.
Table 3.
Parameter Temp Min Typ Max Unit
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.2 3.6 V p-p Input Voltage Range Full GND − 0.3 AVDD + 0.2 V High Level Input Current Full −10 +10 µA Low Level Input Current Full −10 +10 µA Input Resistance Full 8 10 12 k Input Capacitance Full 4 pF
LOGIC INPUTS (SCLK/DFS, SYNC, PDWN)1
High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −50 −75 µA Low Level Input Current Full −10 +10 µA Input Resistance Full 30 k Input Capacitance Full 2 pF
LOGIC INPUTS (CSB)2
High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 µA Low Level Input Current Full 40 135 µA Input Resistance Full 26 k Input Capacitance Full 2 pF
LOGIC INPUTS (SDIO1/DCS2)
High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 µA Low Level Input Current Full 40 130 µA Input Resistance Full 26 k Input Capacitance Full 5 pF
DIGITAL OUTPUTS
DRVDD = 3.3 V
High Level Output Voltage, IOH = 50 µA Full 3.29 V High Level Output Voltage, IOH = 0.5 mA Full 3.25 V Low Level Output Voltage, IOL = 1.6 mA Full 0.2 V Low Level Output Voltage, IOL = 50 µA Full 0.05 V
DRVDD = 1.8 V
High Level Output Voltage, IOH = 50 µA Full 1.79 V High Level Output Voltage, IOH = 0.5 mA Full 1.75 V Low Level Output Voltage, IOL = 1.6 mA Full 0.2 V Low Level Output Voltage, IOL = 50 µA Full 0.05 V
1
Internal 30 kΩ pull-down.
2
Internal 30 kΩ pull-up.
Rev. " | Page 6 of 40
AD6659

SWITCHING SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted.
Table 4.
Parameter Temp Min Typ Max Unit CLOCK INPUT PARAMETERS
Input Clock Rate Full 480 MHz
Conversion Rate1 Full 3 80 MSPS
CLK Period—Divide-by-1 Mode (t
CLK Pulse Width High (tCH) Full 6.25 ns
Aperture Delay (tA) Full 1.0 ns
Aperture Uncertainty (Jitter, tJ) Full 0.1 ps rms DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD) Full 3 ns
DCO Propagation Delay (t
DCO to Data Skew (t
DCO
) Full 0.1 ns
SKEW
Pipeline Delay (Latency) Full 9 Cycles
With NSR Enabled Full 10 Cycles
With QEC Enabled Full 11 Cycles Wake-Up Time2 Full 350 µs Standby Full 260 ns
OUT-OF-RANGE RECOVERY TIME Full 2 Cycles
1
Conversion rate is the clock rate after the CLK divider.
2
Wake-up time is dependent on the value of the decoupling capacitors.
VIN
CLK+ CLK–
DCOA/DCOB
CH A/CH B DATA
) Full 12.5 ns
CLK
) Full 3 ns
N – 1
t
A
N
N + 1
t
CH
t
CLK
t
DCO
t
SKEW
N – 9
t
PD
N + 2
N 8N 7N 6N 5
N + 3
Figure 2. CMOS Output Data Timing
N + 4
N + 5
08701-002
Rev. " | Page 7 of 40
AD6659
VIN
CLK+ CLK–
DCOA/DCOB
CH A/CH B DATA
N – 1
CH A N – 6
N + 4
CH B N – 6
CH A N – 5
N + 5
08701-003
t
A
N
N + 1
t
CH
t
CLK
t
DCO
t
SKEW
CH A
CH B
N – 9
N – 9
t
PD
CH A N – 8
N + 2
CH B N – 8
CH A N – 7
N + 3
CH B N – 7
Figure 3. CMOS Interleaved Output Timing

TIMING SPECIFICATIONS

Table 5.
Parameter Test Conditions/Comments Min Typ Max Unit
SYNC TIMING REQUIREMENTS
t
SYNC to rising edge of CLK setup time (see Figure 4) 0.24 ns
SSYNC
t
SYNC to rising edge of CLK hold time (see Figure 4) 0.40 ns
HSYNC
SPI TIMING REQUIREMENTS
tDS Setup time between the data and the rising edge of SCLK (see Figure 50) 2 ns tDH Hold time between the data and the rising edge of SCLK (see Figure 50) 2 ns t
Period of the SCLK (see Figure 50) 40 ns
CLK
tS Setup time between CSB and SCLK (see Figure 50) 2 ns tH Hold time between CSB and SCLK (see Figure 50) 2 ns t
SCLK pulse width high (see Figure 50) 10 ns
HIGH
t
SCLK pulse width low (see Figure 50) 10 ns
LOW
t
Time required for the SDIO pin to switch from an input to an output relative
EN_SDIO
to the SCLK falling edge
t
Time required for the SDIO pin to switch from an output to an input relative
DIS_SDIO
to the SCLK rising edge
10 ns
10 ns

Timing Diagram

CLK+
SYNC
t
SSYNC
t
HSYNC
Figure 4. SYNC Input Timing Requirements
Rev. " | Page 8 of 40
08701-004
AD6659

ABSOLUTE MAXIMUM RATINGS

Table 6.
Parameter Rating
AVDD to AGND −0.3 V to +2.0 V DRVDD to AGND −0.3 V to +3.9 V VIN+A, VIN+B, VIN−A, VIN−B to AGND −0.3 V to AVDD + 0.2 V CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V SYNC to AGND −0.3 V to DRVDD + 0.3 V VREF to AGND −0.3 V to AVDD + 0.2 V SENSE to AGND −0.3 V to AVDD + 0.2 V VCM to AGND −0.3 V to AVDD + 0.2 V RBIAS to AGND −0.3 V to AVDD + 0.2 V CSB to AGND −0.3 V to DRVDD + 0.3 V SCLK/DFS to AGND −0.3 V to DRVDD + 0.3 V SDIO/DCS to AGND −0.3 V to DRVDD + 0.3 V OEB to AGND −0.3 V to DRVDD + 0.3 V PDWN to AGND −0.3 V to DRVDD + 0.3 V D0x through D11x to AGND DCOx to AGND Operating Temperature Range
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−40°C to +85°C
(Ambient)
Maximum Junction Temperature
150°C
Under Bias
Storage Temperature Range
−65°C to +150°C
(Ambient)

THERMAL CHARACTERISTICS

The exposed paddle is the only ground connection for the chip. The exposed paddle must be soldered to the AGND plane of the user’s circuit board. Soldering the exposed paddle to the user’s board also increases the reliability of the solder joints and maximizes the thermal capability of the package.
Typical θ
is specified for a 4-layer PCB with a solid ground
JA
plane. As listed in Tabl e 7, airflow improves heat dissipation, which reduces θ
. In addition, metal in direct contact with the
JA
package leads from metal traces, through holes, ground, and power planes, reduces the θ
.
JA
Table 7. Thermal Resistance
Airflow Veloc ity
Packa ge Type
(m/sec) θ
64-Lead LFCSP
9 mm × 9 mm (CP-64-4)
1
Per JEDEC 51-7, plus JED
2
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (m
3
Per MIL-STD 883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
1.0 2°C/W 20°C/W 1
2.5 18°C/W
EC 25-5 2S2P test board.
1, 2
JA
/W C/W 0 23°C 2.0°
1, 3
θ θ
JC
oving air).
1, 4
JB

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. " | Page 9 of 40
AD6659

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AVDD
AVDD
VIN+B
VIN–B
AVDD
AVDD
RBIAS
VCM
SENSE
VREF
AVDD
AVDD
VIN–A
VIN+A
646362616059585756555453525150
AVDD
AVDD 49
CLK+ CLK–
SYNC
NC NC NC NC
(LSB) D0B
D1B
DRVDD
10
D2B
11
D3B
12
D4B
13
D5B
14
D6B
15
D7B
16
NOTES
1. NC = NO CONNEC T.
2. THE EXPOSED PADDLE MUST BE SOLDEREDTO THE PCB GROUND TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND ME CHANICAL STRENGTH BENEFITS.
PIN 1
1
INDICATOR
2 3 4 5 6 7 8 9
171819202122232425262728293031
D8B
D9B
D10B
DRVDD
AD6659
TOP VIEW
(Not to Scale)
NCNCNC
ORB
DCOA
DCOB
(MSB) D11B
NC
D1A
DRVDD
(LSB) D0A
48
PDWN
47
OEB
46
CSB
45
SCLK/DFS
44
SDIO/DCS
43
ORA
42
D11A (MSB)
41
D10A
40
D9A
39
D8A
38
D7A
37
DRVDD
36
D6A
35
D5A
34
D4A
33
D3A
32
D2A
08701-005
Figure 5. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
0, EP AGND Exposed paddle is the only ground connection for the chip. It must be connected to
the printed circuit board (PCB) AGND. 1, 2 CLK+, CLK− Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs. 3 SYNC Digital Input. SYNC input to clock divider. 30 k internal pull-down. 4 to 7, 25 to 27, 29 NC Do Not Connect. 8, 9, 11 to 18, 20, 21 D0B to D11B Channel B Digital Outputs. D11B is the MSB and D0B is the LSB. 10, 19, 28, 37 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V). 22 ORB Channel B Out-of-Range Digital Output. 23 DCOB Channel B Data Clock Digital Output. 24 DCOA Channel A Data Clock Digital Output. 30 to 36, 38 to 42 D0A to D11A Channel A Digital Outputs. D11A is the MSB and D0A is the LSB. 43 ORA Channel A Out-of-Range Digital Output. 44 SDIO/DCS SPI Data Input/Output (SDIO). The SDIO function provides bidirectional SPI data I/O in
SPI mode with a 30 k internal pull-down in SPI mode. The duty cycle stabilizer (DCS pin
function) is the static enable input for the duty cycle stabilizer in non-SPI mode with a
30 k internal pull-up in non-SPI (DCS) mode. 45 SCLK/DFS SPI Clock (SCLK) Input in SPI Mode/Data Format Select (DFS). 30 k internal pull-down for both
SCLK and DFS. The DFS function provides static control of data output format in non-SPI mode.
When DFS is high, it equals twos complement output. When DFS is low, it equals offset binary
output. 46 CSB SPI Chip Select. Active low enable; 30 k internal pull-up. 47 OEB Digital Input. When OEB is low, it enables the Channel A and Channel B digital outputs; when
OEB is high, the outputs are tristated. 30 k internal pull-down. 48 PDWN Digital Input. 30 k internal pull-down. When PDWN is high, it powers down the device.
When PDWN is low, the device runs in normal operation.
Rev. " | Page 10 of 40
AD6659
Pin No. Mnemonic Description
49, 50, 53, 54, 59, 60, 63, 64 AVDD 1.8 V Analog Supply Pins. 51, 52 VIN+A, VIN−A Channel A Analog Inputs. 55 VREF Voltage Reference Input/Output. 56 SENSE Reference Mode Selection. 57 VCM Analog output voltage at midsupply to set common mode of the analog inputs. 58 RBIAS Sets Analog Current Bias. Connect to a 10 k (1% tolerance) resistor to ground. 61, 62 VIN−B, VIN+B Channel B Analog Inputs.
Rev. " | Page 11 of 40
AD6659

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted.
0
0
–20
–40
–60
–80
AMPLITUDE (dBFS)
–100
–120
–140
Figure 6. Single-Tone FFT with fIN = 9.7 MHz
0
80MSPS
–20
30.6MHz @ –1dBFS SNR = 71.4 dB (72.4dBFS) SFDR = 94.4dBc
–40
–60
–80
AMPLITUDE (dBFS)
–100
–120
–140
Figure 7. Single-Tone FFT with fIN = 30.6 MHz
0
–20
–40
–60
–80
AMPLITUDE (dBFS)
–100
–120
–140
Figure 8. Single-Tone FFT with fIN = 69 MHz
80MSPS
9.7MHz @ –1dBF S SNR = 70.2dB (71.2dBFS) SFDR = 93.6dBc
50 10152025303540
FREQUENCY (MHz )
08701-054
50 10152025303540
FREQUENCY (MHz )
08701-055
80MSPS 69MHz @ –1dBFS SNR = 70dB (71d BFS) SFDR = 88.9dBc
50 10152025303540
FREQUENCY (MHz )
08701-056
Rev. " | Page 12 of 40
0
80MSPS
–15
100.3MHz @ –1dBF S SNR = 70.5dB (71.5dBFS)
–30
SFDR = 83.5dBc
–45
–60
–75
–90
AMPLITUDE (dBFS)
–105
–120
–135
40 8 12 16 20 24 28 32 36 40
FREQUENCY (MHz )
Figure 9. Single-Tone FFT with fIN = 100.3 MHz
0
80MSPS
–15
28.3MHz @ –7dBF S
30.6MHz @ –7dBF S
–30
SFDR = 87.9dBc
–45
–60
–75
–90
AMPLI TUDE (dBFS)
F2 – F1 2F2 – F1
–105
–120
–135
2F1 + F2
40 8 12 16 20 24 28 32 36 40
Figure 10. Two-Tone FFT with f
F1 + F2
2F2 – F1 2F1 – F2
FREQUENCY (MHz)
= 28.3 MHz and f
IN1
= 30.6 MHz
IN2
0
–20
SFDR (dBc)
–40
IMD3 (dBc)
–60
–80
SFDR/IMD3 ( dBc AND dBFS)
SFDR (dBFS)
–100
IMD3 (dBFS)
–120
–70 –60 –50 –40
INPUT AMPLITUDE (dBF S )
–30 –20 –10
Figure 11. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
f
= 28.3 MHz and f
IN1
= 30.6 MHz
IN2
08701-057
08701-059
08701-060
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