ANALOG DEVICES AD6657A Service Manual
Quad IF Receiver
AD6657A
Rev. 0
Trademarks and registered trademarks are the prop erty of their respective owner s.
Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
VIN+A
DO±AB
D10±AB
VIN–A
PIPELINE
ADC
NOISE SHAPING
REQUANTIZER
VIN+B
VIN–B
PIPELINE
ADC
VIN+C
VIN–C
PIPELINE
ADC
VIN+D
VIN–D
PIPELINE
ADC
SERIAL PO RT
REFERENCE
14
11
NOISE SHAPING
REQUANTIZER
PORT A
AD6657A
PORT B
DATA MULTIPLEXER
AND LVDS DRIVERS
14
11
NOISE SHAPING
REQUANTIZER
14
11
NOISE SHAPING
REQUANTIZER
CLOCK
DIVIDER
09684-001
14
11
VCMA
VCMB
VCMC
VCMD
SCLK SDIO CSB CLK+
AVDD
AGND
DRVDD
DRGND
CLK–
DO±CD
DCO±AB
DCO±CD
D10±CD
MODE
SYNC
PDWN
Data Sheet
FEATURES
11-bit, 200 MSPS output data rate per channel
Integrated noise shaping requantizer
Performance with NSR enabled
SNR: 76.0 dBFS in 40 MHz band to 70 MHz at 185 MSPS
SNR: 73.6 dBFS in 60 MHz band to 70 MHz at 185 MSPS
SNR: 72.8 dBFS in 65 MHz band to 70 MHz at 185 MSPS
Performance with NSR disabled
SNR: 66.5 dBFS to 70 MHz at 185 MSPS
SFDR: 88 dBc to 70 MHz at 185 MSPS
Low power: 1.2 W at 185 MSPS
1.8 V analog supply operation
1.8 V LVDS (ANSI-644 levels) output
1-to-8 integer clock divider
Internal ADC voltage reference
1.75 V p-p analog input range (programmable to 2.0 V p-p)
Differential analog inputs with 800 MHz bandwidth
95 dB channel isolation/crosstalk
Serial port control
User-configurable built-in self test (BIST) capability
Energy saving power-down modes
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
APPLICATIONS
Communications
Diversity radio and smart antenna (MIMO) systems
Multimode digital receivers (3G)
WCDMA, LTE, CDMA2000
WiMAX, TD-SCDMA
I/Q demodulation systems
General-purpose software radios
GENERAL DESCRIPTION
The AD6657A is an 11-bit, 200 MSPS, quad channel intermediate
frequency (IF) receiver specifically designed to support multiple
antenna systems in telecommunication applications where high
dynamic range performance, low power, and small size are desired.
The device consists of four high performance ADCs and NSR
digital blocks. Each ADC consists of a multistage, differential
pipelined architecture with integrated output error correction
logic. The ADC features a wide bandwidth switched capacitor
sampling network within the first stage of the differential pipeline.
An integrated voltage reference eases design considerations. A
duty cycle stabilizer (DCS) compensates for variations in the
ADC clock duty cycle, allowing the converters to maintain
excellent performance.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Each ADC output is connected internally to an NSR block. The
integrated NSR circuitry allows for improved SNR performance
in a smaller frequency band within the Nyquist bandwidth. The
device supports two different output modes selectable via the
external MODE pin or the serial port interface (SPI).
With the NSR feature enabled, the outputs of the ADCs are
processed such that the AD6657A supports enhanced SNR performance within a limited portion of the Nyquist bandwidth
while maintaining an 11-bit output resolution. The NSR block
can be programmed to provide a bandwidth of either 22%, 33%,
or 36% of the sample clock. For example, with a sample clock
rate of 185 MSPS, the AD6657A can achieve up to 76.0 dBFS
SNR for a 40 MHz bandwidth in the 22% mode, up to 73.6 dBFS
SNR for a 60 MHz bandwidth in the 33% mode, or up to 72.8 dBFS
SNR for a 65 MHz bandwidth in the 36% mode.
(General Description continued on Page 3)
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Tel: 781.329.4700 www.analog.com
AD6657A Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Product Highlights ........................................................................... 3
Specifications ..................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications .......................................................................... 5
Digital Specifications ................................................................... 7
Switching Specifications .............................................................. 9
Timing Specifications ................................................................ 10
Absolute Maximum Ratings ..................................................... 11
Thermal Characteristics ............................................................ 11
ESD Caution ................................................................................ 11
Pin Configuration and Function Descriptions ........................... 12
Typical Performance Characteristics ........................................... 14
Equivalent Circuits ......................................................................... 18
Theory of Operation ...................................................................... 19
ADC Architecture ...................................................................... 19
Analog Input Considerations .................................................... 19
Clock Input Considerations ...................................................... 21
Power Dissipation and Standby Mode ..................................... 23
Channel/Chip Synchronization ................................................ 23
Digital Outputs ........................................................................... 24
Timing ......................................................................................... 24
Noise Shaping Requantizer ........................................................... 25
22% BW Mode (>40 MHz at 184.32 MSPS) ........................... 25
33% BW Mode (>60 MHz at 184.32 MSPS) ........................... 26
36% BW Mode (>65 MHz at 184.32 MSPS) ........................... 27
MODE Pin ................................................................................... 27
Built-In Self Test (BIST) and Output Test ................................... 28
BIST .............................................................................................. 28
Output Test Modes ..................................................................... 28
Serial Port Interface (SPI) .............................................................. 29
Configuration Using the SPI ..................................................... 29
Hardware Interface ..................................................................... 29
Memory Map .................................................................................. 30
Reading the Memory Map Register Table ............................... 30
Memory Map Register Table ..................................................... 31
Memory Map Register Descriptions ........................................ 33
Applications Information .............................................................. 35
Design Guidelines ...................................................................... 35
Packaging and Ordering Information ......................................... 36
Outline Dimensions ................................................................... 36
Ordering Guide .......................................................................... 36
REVISION HISTORY
10/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 36
Data Sheet AD6657A
With the NSR block disabled, the ADC data is provided directly to
the output with a resolution of 11 bits. The AD6657A can achieve
up to 66.5 dBFS SNR for the entire Nyquist bandwidth when
operated in this mode. This allows the AD6657A to be used in
telecommunication applications such as a digital predistortion
observation path where wider bandwidths are used.
After digital signal processing, multiplexed output data is
routed into two 11-bit output ports such that the maximum
digital data rate (DDR) is 400 Mbps. These outputs are set at
1.8 V LVDS and support ANSI-644 levels.
The AD6657A receiver digitizes a wide spectrum of IF frequencies.
Each receiver is designed for simultaneous reception of a separate
antenna. This IF sampling architecture greatly reduces component
cost and complexity compared with traditional analog techniques
or less integrated digital methods.
Flexible power-down options allow significant power savings.
Programming for device setup and control is accomplished
using a 3-wire SPI-compatible serial interface with numerous
modes to support board level system testing.
The AD6657A is available in a Pb-free, RoHS compliant,
144-ball, 10 mm × 10 mm chip scale package ball grid array
(CSP_BGA) that is specified over the industrial temperature
range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Four analog-to-digital converters (ADCs) are contained in
a small, space-saving, 10 mm × 10 mm × 1.4 mm, 144-ball
CSP_BGA package.
2. Pin selectable noise shaping requantizer (NSR) function
that allows for improved SNR within a reduced bandwidth
of up to 65 MHz at 185 MSPS.
3. LVDS digital output interface configured for low cost
FPGA families.
4. 230 mW per ADC core power consumption.
5. Operation from a single 1.8 V supply.
6. Standard SPI that supports various product features and
functions, such as data formatting (offset binary or twos
complement), NSR, power-down, test modes, and voltage
reference mode.
7. On-chip integer 1-to-8 input clock divider and multichip
sync function to support a wide range of clocking schemes
and multichannel subsystems.
Rev. 0 | Page 3 of 36
AD6657A Data Sheet
Differential Nonlinearity (DNL)1
Full
−0.4
±0.1
+0.4
LSB
Offset Error
Full
−5
+3
+11
mV
TEMPERATURE DRIFT
ANALOG INPUT
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.
Table 1.
Parameter Temperature Min Typ Max Unit
RESOLUTION Full 11 Bits
ACCURACY
No Missing Codes Full Guaranteed
Offset Error Full −0.9 +0.1 +0.9 mV
Gain Error Full +4 +11 +18 % FSR
Integral Nonlinearity (INL)
1
Full −
0.55 ±0.17 +0.55 LSB
MATCHING CHARACTERISTIC
Gain Error Full 0 +2.1 +8 % FSR
Offset Error Full 2 ppm/°C
Gain Error Full 40 ppm/°C
Input Range Full 1.4 1.75 2.0 V p-p
Input Common-Mode Voltage Full 0.95 V
Input Resistance (Differential) Full 20 kΩ
Input Capacitance2 Full 5 pF
POWER SUPPLIES
Supply Voltage
AVDD Full 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 V
Supply Current
1
Full 466 510 mA
I
AVDD
1
(1.8 V LVDS) Full 170 183 mA
I
DRVDD
POWER CONSUMPTION
Sine Wave Input1 Full 1145 1247 mW
Standby Power3 Full 129 mW
Power-Down Power Full 3.8 10 mW
1
Measured with a 10 MHz, 0 dBFS sine wave, with 100 Ω termination on each LVDS output pair.
2
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
3
Standby power is measured with a dc input and the CLKx pins inactive (set to AVDD or AGND).
Rev. 0 | Page 4 of 36
Data Sheet AD6657A
fIN = 170 MHz
25°C 66.3 dBFS
SIGNAL-TO-NOISE-RATIO (SNR)—NSR ENABLED
fIN = 70 MHz
25°C 73.3 dBFS
fIN = 50 MHz
25°C 72.6 dBFS
fIN = 70 MHz
25°C 65.5 dBFS
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.
Table 2.
Parameter1 Temperature Min Typ Max Unit
SIGNAL-TO-NOISE-RATIO (SNR)—NSR DISABLED
fIN = 10 MHz 25°C 66.6 dBFS
fIN = 50 MHz 25°C 66.5 dBFS
fIN = 70 MHz 25°C 66.5 dBFS
Full 65.6 dBFS
fIN = 250 MHz 25°C 65.9 dBFS
22% BW Mode
fIN = 10 MHz 25°C 76.0 dBFS
fIN = 50 MHz 25°C 75.7 dBFS
fIN = 70 MHz 25°C 75.7 dBFS
fIN = 170 MHz 25°C 74.3 dBFS
Full 72.9 dBFS
fIN = 250 MHz 25°C 72.8 dBFS
33% BW Mode
fIN = 10 MHz 25°C 73.6 dBFS
fIN = 50 MHz 25°C 73.6 dBFS
fIN = 170 MHz 25°C 72.5 dBFS
Full 71.3 dBFS
fIN = 230 MHz 25°C 71.2 dBFS
36% BW Mode
fIN = 10 MHz 25°C 72.8 dBFS
fIN = 70 MHz 25°C 72.6 dBFS
fIN = 170 MHz 25°C 71.8 dBFS
Full 70.7 dBFS
fIN = 250 MHz 25°C 70.8 dBFS
SIGNAL-TO-NOISE-AND DISTORTION (SINAD)
fIN = 10 MHz 25°C 65.5 dBFS
fIN = 50 MHz 25°C 65.5 dBFS
fIN = 170 MHz 25°C 65.3 dBFS
Full 64.6 dBFS
fIN = 250 MHz 25°C 64.8 dBFS
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz 25°C 10.6 Bits
fIN = 50 MHz 25°C 10.6 Bits
fIN = 70 MHz 25°C 10.6 Bits
fIN = 170 MHz 25°C 10.6 Bits
fIN = 250 MHz 25°C 10.5 Bits
Rev. 0 | Page 5 of 36
AD6657A Data Sheet
fIN = 170 MHz
25°C −90 dBc
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 250 MHz
25°C 83 dBc
ANALOG INPUT BANDWIDTH
25°C 800 MHz
Parameter1 Temperature Min Typ Max Unit
WORST SECOND OR THIRD HARMONIC
fIN = 10 MHz 25°C −94 dBc
fIN = 50 MHz 25°C −91 dBc
fIN = 70 MHz 25°C −88 dBc
Full −80 dBc
fIN = 250 MHz 25°C −83 dBc
fIN = 10 MHz 25°C 94 dBc
fIN = 50 MHz 25°C 91 dBc
fIN = 70 MHz 25°C 88 dBc
fIN = 170 MHz 25°C 90 dBc
Full 80 dBc
WORST OTHER HARMONIC (FOURTH THROUGH EIGHTH)
fIN = 10 MHz 25°C −94 dBc
fIN = 50 MHz 25°C −95 dBc
fIN = 70 MHz 25°C −94 dBc
fIN = 170 MHz 25°C −94 dBc
Full −80 dBc
fIN = 250 MHz 25°C −90 dBc
TWO TONE SFDR (−7 dBFS)
f
= 169 MHz, f
IN1
CROSSTALK2 Full 95 dB
= 172 MHz 25°C 89 dBc
IN2
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2
Crosstalk is measured at 155 MHz with −1 dBFS on one channel and no input on the alternate channel.
Rev. 0 | Page 6 of 36
Data Sheet AD6657A
Input Voltage Range
Full
AGND − 0.3
AVDD + 0.2
V
Input Capacitance
Full 4 pF
Low Level Input Current
Full
−100
+100
µA
LOGIC INPUT (CSB)1
High Level Input Current
Full
−10 +10
µA
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.
Table 3.
Parameter Temperature Min Typ Max Unit
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL
Internal Common-Mode Bias Full 0.9 V
Differential Input Voltage Full 0.2 3.6 V p-p
High Level Input Voltage Full 1.2 2.0 V
Low Level Input Voltage Full 0 0.8 V
High Level Input Current Full −10 +10 µA
Low Level Input Current Full −10 +10 µA
Input Resistance Full 8 10 12 kΩ
SYNC INPUT
Logic Compliance CMOS
Internal Bias Full 0.9 V
Input Voltage Range Full AGND AVDD V
High Level Input Voltage Full 1.2 AVDD V
Low Level Input Voltage Full AGND 0.6 V
High Level Input Current Full −100 +100 µA
Input Resistance Full 12 16 20 kΩ
Input Capacitance Full 1 pF
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full −10 +10 µA
Low Level Input Current Full 40 132 µA
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF
LOGIC INPUT (SCLK)2
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full −92 −135 µA
Low Level Input Current Full −10 +10 µA
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF
LOGIC INPUT/OUTPUT (SDIO)
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
Low Level Input Current Full 38 128 µA
Input Resistance Full 26 kΩ
Input Capacitance Full 5 pF
2
Rev. 0 | Page 7 of 36
AD6657A Data Sheet
Parameter Temperature Min Typ Max Unit
LOGIC INPUT (MODE)1
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full −10 +10 μA
Low Level Input Current Full 40 132 μA
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF
LOGIC INPUT (PDWN)2
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full −90 −134 μA
Low Level Input Current Full −10 +10 μA
Input Resistance Full 26 kΩ
Input Capacitance Full 5 pF
DIGITAL OUTPUTS (LVDS)
Differential Output Voltage (VOD) Full 247 454 mV
Output Offset Voltage (VOS) Full 1.125 1.375 V
1
Pull up.
2
Pull down.
Rev. 0 | Page 8 of 36
Data Sheet AD6657A
Aperture Delay (tA)2
Full 1.3 ns
Data Propagation Delay (tPD)2
Full
3.0
4.0
4.9
ns
N – 1
N + 1
N + 2
N + 3
N + 4
N + 5
N
CLK+
CLK–
DCO+
DCO–
D10+AB (MSB)
D10–AB (MSB)
D0+AB (LSB)
D0–AB (LSB)
VIN
t
A
t
CH
t
DCO
t
CL
t
PD
t
SKEW
1/
f
S
D10A D10B D10A D10B D10A D10B D10A D10B D10A D10B D10A D10B
D0A D0B
D10A D10B
D0A D0B D0A D0B D0A D0B D0A D0B D0A D0B D0A D0B
09684-002
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.
Table 4.
Parameter Temperature Min Typ Max Unit
CLOCK INPUT PARAMETERS
Input Clock Rate Full 625 MHz
Conversion Rate1 Full 40 185 200 MSPS
CLK Pulse Width High (tCH)2 Full 2.7 ns
Aperture Uncertainty (Jitter, tJ) Full 0.13 ps rms
DATA OUTPUT PARAMETERS
DCO Propagation Delay (t
DCO to Data Skew (t
SKEW
)2 Full 3.1
DCO
)2 Full −41 +6.1 +33 ns
4.0
4.9 ns
Pipeline Delay (Latency) Full 9 Cycles
With NSR Enabled Full 12 Cycles
Wake-Up Time (from Standby)3 Full 0.5 µs
Wake-Up Time (from Power Down)3 Full 310 µs
OUT-OF-RANGE RECOVERY TIME Full 2 Cycles
1
Conversion rate is the clock rate after the divider.
2
See Figure 2 for details.
3
Wake-up time is dependent on the value of the decoupling capacitors.
Data Output Timing Diagram
Figure 2. Data Output Timing (Timing for Channel C and Channel D Is Identical to Timing for Channel A and Channel B)
Rev. 0 | Page 9 of 36
AD6657A Data Sheet
tDH
Hold time between the data and the rising edge of SCLK
2
ns
t
10
ns
SYNC
CLK+
t
HSYNC
t
SSYNC
09684-003
TIMING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.
Table 5.
Parameter Description Min Typ Max Unit
SYNC TIMING REQUIREMENTS See Figure 3 for details
t
SYNC to rising edge of CLK setup time 0.24 ns
SSYNC
t
SYNC to rising edge of CLK hold time 0.40 ns
HSYNC
SPI TIMING REQUIREMENTS See Figure 60 for details, except where noted
tDS Setup time between the data and the rising edge of SCLK 2 ns
t
Period of the SCLK 40 ns
CLK
tS Setup time between CSB and SCLK 2 ns
tH Hold time between CSB and SCLK 2 ns
t
SCLK pulse width high 10 ns
HIGH
t
SCLK pulse width low 10 ns
LOW
EN_SDIO
t
DIS_SDIO
Time required for the SDIO pin to switch from an input to
an output relative to the SCLK falling edge (not pictured in
Figure 60)
Time required for the SDIO pin to switch from an output to
an input relative to the SCLK rising edge (not pictured in
Figure 60)
10 ns
Sync Input Timing Diagram
Figure 3. SYNC Input Timing Requirements
Rev. 0 | Page 10 of 36
Data Sheet AD6657A
v
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
AVDD to AGND −0.3 V to +2.0 V
DRVDD to AGND −0.3 V to +2.0 V
VIN+x, VIN−x to AGND −0.3 V to AVDD + 0.2 V
CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V
SYNC to AGND −0.3 V to AVDD + 0.2 V
VCMx to AGND −0.3 V to AVDD + 0.2 V
CSB to AGND −0.3 V to DRVDD + 0.2 V
SCLK to AGND −0.3 V to DRVDD + 0.2 V
SDIO to AGND −0.3 V to DRVDD + 0.2 V
PDWN to AGND −0.3 V to DRVDD + 0.2 V
MODE to AGND −0.3 V to DRVDD + 0.2 V
Digital Outputs to AGND −0.3 V to DRVDD + 0.2 V
DCO+AB, DCO−AB, DCO+CD,
−0.3 V to DRVDD + 0.2 V
DCO−CD to AGND
Operating Temperature Range
−40°C to +85°C
(Ambient)
Maximum Junction Temperature
150°C
Under Bias
Storage Temperature Range
−65°C to +150°C
(Ambient)
Stresses abovethose listedunderAbsoluteMaximumRatings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximumratingconditionsfor extendedperiodsmayaffect
de
ice reliability.
THERMAL CHARACTERISTICS
The values in Table 7 are per JEDEC JESD51-7 and JEDEC
JESD25-5 for a 2S2P test board. Typical θ
4-layer printed circuit board (PCB) with a solid ground plane.
As shown in Table 7, airflow improves heat dissipation, which
reduces θ
. In addition, metal in direct contact with the
JA
package leads from metal traces, through holes, ground, and
power planes reduces θ
.
JA
Table 7.
Airflow
Package Type
Velocity θ
144-Ball CSP_BGA 0 m/s 26.9 8.9 6.6 °C/W
1 m/s 24.2 °C/W
2.5 m/s 23.0 °C/W
1
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
2
Per MIL-STD 883, Method 1012.1.
3
Per JEDEC JESD51-8 (still air).
The values in Table 8 are from simulations. The PCB is a JEDEC
multilayer board. Thermal performance for actual applications
requires careful inspection of the conditions in the application
to determine whether they are similar to those assumed in these
calculations.
Table 8.
Airflow
Package Type
Veloc ity
144-Ball CSP_BGA 0 m/s 14.4 0.23 °C/W
1 m/s 14.0 0.50 °C/W
2.5 m/s 13.9 0.53 °C/W
is specified for a
JA
1
JA
2
θ
JC
JB
3
θ
JB
JT
Unit
Unit
ESD CAUTION
Rev. 0 | Page 11 of 36
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