ANALOG DEVICES AD6653 Service Manual

A

www.BDTIC.com/ADI

IF Diversity Receiver

FEATURES

SNR = 70.8 dBc (71.8 dBFS) in a 32.7 MHz BW at

70 MHz @ 150 MSPS

SFDR = 83 dBc to 70 MHz @ 150 MSPS

1.8 V analog supply operation

1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS ou

tput supply Integer 1-to-8 input clock divider Integrated dual-channel ADC

Sample rates up to 150 MSPS

IF sampling frequencies to 450 MHz Internal ADC voltage reference Integrated ADC sample-and-hold inputs Flexible analog input range: 1 V p-p to 2 V p-p ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk

Integrated wideband digital downconverter (DDC)

32-bit, complex, numerically controlled oscillator (NCO) Decimating half-band filter and FIR filter Supports real and complex output modes Fast attack/threshold detect bits

Composite signal monitor Energy-saving power-down modes

FUNCTIONAL BLOCK DIAGRAM

AVDD FD[0:3]

AD6653

APPLICATIONS

Communications Diversity radio systems Multimode digital receivers (3G)

TD-SCDMA, WiMax, WCDMA,

CDMA20 I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications

PRODUCT HIGHLIGHTS

1. Integrated dual, 12-bit, 125 MSPS/150 MSPS ADC.

2. I

3. F

4. P

5. F

6. S

7. 3

00, GSM, EDGE, LTE

ntegrated wideband decimation filter and 32-bit

complex NCO.

ast overrange detect and signal monitor with serial output. roprietary differential input maintains excellent SNR

performance for input frequencies up to 450 MHz.

lexible output modes, including independent CMOS,

interleaved CMOS, IQ mode CMOS, and interleaved LVDS.

YNC input allows synchronization of multiple devices.

-bit SPI port for register programming and register readback.

DVDD DRVDD

FD BITS/T HRESHOLD

DETECT

VIN+A

VIN–A

VREF

SENSE

CML

RBIAS

VIN–B

VIN+B

NOTES

1. PIN NAMES ARE FOR THE CMO S PIN CONF IGURATIO N ONLY; SEE FIGURE 10 FOR LVDS PIN NAMES.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

SHA

REF

SELECT

SHA ADC

MULTI-CHI P

AGND

SYNC

SYNC FD[0:3]B SMI

ADC

SIGNAL

MONITOR

FD BITS/THRESHOLD

DETECT

32-BIT

TUNING

NCO

SIGNAL MONITOR

DATA

I

DECIMATING

HB FILTER +

Q

DECIMATING

HB FILTER +

I

Figure 1.

AD6653

LP/HP

FIR

DIVIDE 1

f

/8

ADC

NCO

LP/HP

FIR

SIGNAL MO NITOR

INTERFACE

SMI SCLK/ PDWN

SMI

SDO/

OEB

SDFS

TO 8

DUTY

CYCLE

STABILIZER

PROGRAMMING DATA

SDIO/

DCS

SPI

SCLK/

DFS

GENERATION

CSB DRGND

CMOS/LV DS

DCO

CMOS

D11A

D0A

OUTPUT BUFFER

CLK+

CLK–

DCOA

DCOB

D11B

D0B

OUTPUT BUFFER

6708-001

AD6653

www.BDTIC.com/ADI

REVISION HISTORY

11/07—Revision 0: Initial Version

Rev. 0 | Page 3 of 80

AD6653

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GENERAL DESCRIPTION

The AD6653 is a mixed-signal intermediate frequency (IF) receiver consisting of dual, 12-bit, 125 MSPS/150 MSPS ADCs and a wideband digital downconverter (DDC). The AD6653 is designed to support communications applications where low cost, small size, and versatility are desired.

The dual ADC core features a multistage, differential pipelined a

rchitecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

ADC data outputs are internally connected directly to the

tal downconverter (DDC) of the receiver, simplifying layout

digi and reducing interconnection parasitics. The digital receiver has two channels and provides processing flexibility. Each receive channel has four cascaded signal processing stages: a 32-bit frequency translator (numerically controlled oscillator (NCO)), a decimating half-band filter, a fixed FIR filter, and an f fixed-frequency NCO.

In addition to the receiver, DDC, the AD6653 has several functions tha

t simplify the automatic gain control (AGC) function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with short latency.

ADC

/8

In addition, the programmable threshold detector allows

itoring of the incoming signal power using the four fast

mon detect bits of the ADC with low latency. If the input signal level exceeds the programmable threshold, the coarse upper threshold indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition.

The second AGC-related function is the signal monitor. This block

lows the user to monitor the composite magnitude of the

al incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system.

After digital processing, data can be routed directly to the two e

xternal 12-bit output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or as 1.8 V LVDS. The CMOS data can also be output in an interleaved configuration at a double data rate, using only Port A.

The AD6653 receiver digitizes a wide spectrum of IF frequencies.

ach receiver is designed for simultaneous reception of the main

E channel and the diversity channel. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods. Flexible power-down options allow significant power savings, when desired.

Programming for setup and control is accomplished using a 3-bit

PI-compatible serial interface.

S

The AD6653 is available in a 64-lead LFCSP and is specified over t

he industrial temperature range of −40°C to +85°C.

Rev. 0 | Page 4 of 80

AD6653

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SPECIFICATIONS

ADC DC SPECIFICATIONS

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted.

Table 1.

AD6653BCPZ-125 AD6653BCPZ-150

Parameter Temperature

Min Typ Max Min Typ Max

RESOLUTION Full 12 12 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±0.3 ±0.6 ±0.2 ±0.6 % FSR Gain Error Full −3.9 −2.7 −0.7 −5.2 −3.2 −0.9 % FSR

MATCHING CHARACTERISTIC

Offset Error 25°C ±0.3 ±0.6 ±0.2 ±0.7 % FSR Gain Error 25°C ±0.1 ±0.7 ±0.2 ±0.7 % FSR

TEMPERATURE DRIFT

Offset Error Full ±19 ±17 ppm/°C Gain Error Full ±38 ±49 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode) Full ±5 ±18 ±5 ±18 mV Load Regulation @ 1.0 mA Full 7 7 mV

INPUT-REFERRED NOISE

VREF = 1.0 V 25°C 0.21 0.21 LSB rms

ANALOG INPUT

Input Span, VREF = 1.0 V Full 2 2 V p-p Input Capacitance

1

Full 8 8 pF VREF INPUT RESISTANCE Full 6 6 kΩ POWER SUPPLIES

Supply Voltage

AVDD, DVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD (CMOS Mode) Full 1.7 3.3 3.6 1.7 3.3 3.6 V DRVDD (LVDS Mode) Full 1.7 1.8 1.9 1.7 1.8 1.9 V

Supply Current

2, 3

I

AVDD

2, 3

I

DVDD

2

I

(3.3 V CMOS) Full 20 24 mA

DRVDD

2

I

(1.8 V CMOS) Full 12 15 mA

DRVDD

2

I

(1.8 V LVDS) Full 57 57 mA

DRVDD

Full 390 440 mA

Full 270

689

320

785

POWER CONSUMPTION

DC Input Full 770 800 870 905 mW Sine Wave Input2 (DRVDD = 1.8 V) Full 1215 1395 mW Sine Wave Input2 (DRVDD = 3.3 V) Full 1275 1450 mW Standby Power

4

Full 77 77 mW

Power-Down Power Full 2.5 8 2.5 8 mW

1

Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 11 for the equivalent analog input structure.

2

Measured with a 9.7 MHz, full-scale sine wave input, NCO enabled with a frequency of 13 MHz, FIR filter enabled and the fS/8 output mix enabled with approximately

5 pF loading on each output bit.

3

The maximum limit applies to the combination of I

4

Standby power is measured with a dc input and with the CLK pin inactive (set to AVDD or AGND).

AVDD

and I

DVDD

currents.

Unit

mA

Rev. 0 | Page 5 of 80

AD6653

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ADC AC SPECIFICATIONS

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, NCO enabled, half-band filter enabled, FIR filter enabled, unless otherwise noted.

Table 2.

Parameter

SIGNAL-TO-NOISE-RATIO (SNR)

fIN = 2.4 MHz 25°C 71.0 70.9 dB fIN = 70 MHz 25°C 70.8 70.8 dB Full 69.8 69.4 dB fIN = 140 MHz 25°C 70.6 70.6 dB fIN = 220 MHz 25°C 70.2 70.0 dB

WORST SECOND OR THIRD HARMONIC

fIN = 2.4 MHz 25°C −85 −84 dBc fIN = 70 MHz 25°C −84 −83 dBc Full −74 −73 dBc fIN = 140 MHz 25°C −83 −82 dBc fIN = 220 MHz 25°C −81 −77 dBc

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 2.4 MHz 25°C 85 84 dBc fIN = 70 MHz 25°C 84 83 dBc Full 74 73 dBc fIN = 140 MHz 25°C 83 82 dBc fIN = 220 MHz 25°C 81 77 dBc

WORST OTHER HARMONIC OR SPUR

fIN = 2.4 MHz 25°C −92 −90 dBc fIN = 70 MHz 25°C −90 −87 dBc Full −82 −80 dBc fIN = 140 MHz 25°C −88 −83 dBc fIN = 220 MHz 25°C −84 −78 dBc

TWO-TONE SFDR

fIN = 29.12 MHz, 32.12 MHz (−7 dBFS) 25°C 85 85 dBc

fIN = 169.12 MHz, 172.12 MHz (−7 dBFS) 25°C 81 81 dBc CROSSTALK ANALOG INPUT BANDWIDTH 25°C 650 650 MHz

1

See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

2

See the Applications Information section for more information about the worst other specifications for the AD6653.

3

Crosstalk is measured at 100 MHz with −1 dBFS on one channel and with no input on the alternate channel.

1

2

3

Temperature

Full 95 95 dB

AD6653BCPZ-125 AD6653BCPZ-150

Min Typ Max Min Typ Max

Unit

Rev. 0 | Page 6 of 80

AD6653

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DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted.

Table 3.

AD6653BCPZ-125 AD6653BCPZ-150

Parameter Temp

DIFFERENTIAL CLOCK INPUTS

(CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 1.2 1.2 V Differential Input Voltage Full 0.2 6 0.2 6 V p-p Input Voltage Range Full AVDD − 0.3 AVDD + 1.6 AVDD − 0.3 AVDD + 1.6 V Input Common-Mode Range Full 1.1 V AVDD 1.1 V AVDD V High Level Input Voltage Full 1.2 3.6 1.2 3.6 V Low Level Input Voltage Full 0 0.8 0 0.8 V High Level Input Current Full −10 +10 −10 +10 μA Low Level Input Current Full −10 +10 −10 +10 μA Input Capacitance Full 4 4 pF Input Resistance Full 8 10 12 8 10 12 kΩ

SYNC INPUT

Logic Compliance CMOS CMOS Internal Bias Full 1.2 1.2 V Input Voltage Range Full AVDD − 0.3 AVDD + 1.6 AVDD − 0.3 AVDD + 1.6 V High Level Input Voltage Full 1.2 3.6 1.2 3.6 V Low Level Input Voltage Full 0 0.8 0 0.8 V High Level Input Current Full −10 +10 −10 +10 μA Low Level Input Current Full −10 +10 −10 +10 μA Input Capacitance Full 4 4 pF Input Resistance Full 8 10 12 8 10 12 kΩ

LOGIC INPUT (CSB)

High Level Input Voltage Full 1.22 3.6 1.22 3.6 V Low Level Input Voltage Full 0 0.6 0 0.6 V High Level Input Current Full −10 +10 −10 +10 μA Low Level Input Current Full 40 132 40 132 μA Input Resistance Full 26 26 kΩ Input Capacitance Full 2 2 pF

LOGIC INPUT (SCLK/DFS)

High Level Input Voltage Full 1.22 3.6 1.22 3.6 V Low Level Input Voltage Full 0 0.6 0 0.6 V High Level Input Current Full −92 −135 −92 −135 μA Low Level Input Current Full −10 +10 −10 +10 μA Input Resistance Full 26 26 kΩ Input Capacitance Full 2 2 pF

LOGIC INPUTS (SDIO/DCS, SMI SDFS)

High Level Input Voltage Full 1.22 3.6 1.22 3.6 V Low Level Input Voltage Full 0 0.6 0 0.6 V High Level Input Current Full −10 +10 −10 +10 μA Low Level Input Current Full 38 128 38 128 μA Input Resistance Full 26 26 kΩ Input Capacitance Full 5 5 pF

1

2

1

Min Typ Max Min Typ Max

Unit

Rev. 0 | Page 7 of 80

AD6653

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AD6653BCPZ-125 AD6653BCPZ-150

Parameter Temp

LOGIC INPUTS (SMI SDO/OEB, SMI SCLK/PDWN)

High Level Input Voltage Full 1.22 3.6 1.22 3.6 V

Low Level Input Voltage Full 0 0.6 0 0.6 V

High Level Input Current Full −90 −134 −90 −134 μA

Low Level Input Current Full −10 +10 −10 +10 μA

Input Resistance Full 26 26 kΩ

Input Capacitance Full 5 5 pF DIGITAL OUTPUTS

CMOS Mode—DRVDD = 3.3 V

High Level Output Voltage

IOH = 50 μA Full 3.29 3.29 V IOH = 0.5 mA Full 3.25 3.25 V

Low Level Output Voltage

IOL = 1.6 mA Full 0.2 0.2 V IOL = 50 μA Full 0.05 0.05 V

CMOS Mode—DRVDD = 1.8 V

High Level Output Voltage

IOH = 50 μA Full 1.79 1.79 V IOH = 0.5 mA Full 1.75 1.75 V

Low Level Output Voltage

IOL = 1.6 mA Full 0.2 0.2 V IOL = 50 μA Full 0.05 0.05 V

LVDS Mode—DRVDD = 1.8 V

Differential Output Voltage (VOD),

ANSI Mode Output Offset Voltage (VOS), ANSI Mode Full 1.15 1.25 1.35 1.15 1.25 1.35 V Differential Output Voltage (VOD),

Reduced Swing Mode Output Offset Voltage (VOS),

Reduced Swing Mode

1

Pull up.

2

Pull down.

2

Full 250 350 450 250 350 450 mV

Full 150 200 280 150 200 280 mV

Full 1.15 1.25 1.35 1.15 1.25 1.35 V

Min Typ Max Min Typ Max

Unit

Rev. 0 | Page 8 of 80

AD6653

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SWITCHING SPECIFICATIONS

Table 4.

AD6653BCPZ-125 AD6653BCPZ-150

Parameter Temperature

CLOCK INPUT PARAMETERS

Input Clock Rate Full 625 625 MHz Conversion Rate1

DCS Enabled Full 20 125 20 150 MSPS

DCS Disabled Full 10 125 10 150 MSPS CLK Period—Divide-by-1 Mode (t CLK Pulse Width High (t

Divide-by-1 Mode, DCS Enabled Full 2.4 4 5.6 2.0 3.33 4.66 ns

Divide-by-1 Mode, DCS Disabled Full 3.6 4 4.4 3.0 3.33 3.66 ns

Divide-by-2 Mode, DCS Enabled Full 1.6 1.6 ns

Divide-by-3 Through Divide-by-8 Modes,

DCS Enabled

DATA OUTPUT PARAMETERS (DATA, FD)

CMOS Noninterleaved Mode—DRVDD = 1.8 V

Data Propagation Delay (tPD)2 Full 1.6 3.9 6.2 1.6 3.9 6.2 ns

DCO Propagation Delay (t

Setup Time (tS) Full 9.5 8.16 ns

Hold Time (tH) Full 6.5 5.16 ns CMOS Noninterleaved Mode—DRVDD = 3.3 V

Data Propagation Delay (tPD)2 Full 1.9 4.1 6.4 1.9 4.1 6.4 ns

DCO Propagation Delay (t

Setup Time (tS) Full 9.7 8.36 ns

Hold Time (tH) Full 6.3 4.96 ns CMOS Interleaved and IQ Mode—DRVDD = 1.8 V

Data Propagation Delay (tPD)2 Full 1.6 3.9 6.2 1.6 3.9 6.2 ns

DCO Propagation Delay (t

Setup Time (tS) Full 4.9 4.23 ns

Hold Time (tH) Full 3.1 2.43 ns CMOS Interleaved and IQ Mode—DRVDD = 3.3 V

Data Propagation Delay (tPD) 2 Full 1.9 4.1 6.4 1.9 4.1 6.4 ns

DCO Propagation Delay (t

Setup Time (tS) Full 5.1 4.43 ns

Hold Time (tH) Full 2.9 2.23 ns LVDS Mode—DRVDD = 1.8 V

Data Propagation Delay (tPD)2 Full 2.5 4.8 7.0 2.5 4.8 7.0 ns

DCO Propagation Delay (t Pipeline Delay (Latency) NCO, FIR, fS/8 Mix Disabled Full 38 38 Cycles Pipeline Delay (Latency) NCO Enabled; FIR and fS/8

Mix Disabled (Complex Output Mode) Pipeline Delay (Latency) NCO, FIR Filter, and fS/8 Mix

Enabled

Aperture Delay (tA) Full 1.0 1.0 ns

Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 ps rms

Wake-Up Time3 Full 350 350 μs

OUT-OF-RANGE RECOVERY TIME Full 44 44 Cycles

1

Conversion rate is the clock rate after the divider.

2

Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with a 5 pF load.

3

Wake-up time is dependent on the value of the decoupling capacitors.

)

CLKH

) Full 8 6.66 ns

CLK

Full 0.8 0.8 ns

) Full 4.0 5.4 7.3 4.0 5.4 7.3 ns

DCO

) Full 4.4 5.8 7.7 4.4 5.8 7.7 ns

DCO

) Full 3.4 4.8 6.7 3.4 4.8 6.7 ns

DCO

) Full 3.8 5.2 7.1 3.8 5.2 7.1 ns

DCO

) Full 3.7 5.3 7.3 3.7 5.3 7.3 ns

DCO

Full 38 38 Cycles

Full 109 109 Cycles

Min Typ Max Min Typ Max

Unit

Rev. 0 | Page 9 of 80

AD6653

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TIMING SPECIFICATIONS

Table 5.

Parameter Conditions Min Typ Max Unit

SYNC TIMING REQUIREMENTS

t

SYNC to the rising edge of CLK setup time 0.24 ns

SSYNC

t

SYNC to the rising edge of CLK hold time 0.4 ns

HSYNC

SPI TIMING REQUIREMENTS

tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns t

Period of the SCLK 40 ns

CLK

tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns t

Minimum period that SCLK should be in a logic high state 10 ns

HIGH

t

Minimum period that SCLK should be in a logic low state 10 ns

LOW

t

EN_SDIO

Time required for the SDIO pin to swit

ch from an input to an output

relative to the SCLK falling edge

t

DIS_SDIO

Time required for the SDIO pin to switch from an output to an input

elative to the SCLK rising edge

r

SPORT TIMING REQUIREMENTS

t

Delay from rising edge of CLK+ to rising edge of SMI SCLK 3.2 4.5 6.2 ns

CSSCLK

t

Delay from rising edge of SMI SCLK to SMI SDO −0.4 0 +0.4 ns

SSLKSDO

t

Delay from rising edge of SMI SCLK to SMI SDFS −0.4 0 +0.4 ns

SSCLKSDFS

Timing Diagrams

10 ns

CLK+

t

PD

FD BITS

t

CHANNEL A/B

DATA BITS

S

DECIMATED CMOS DAT A

DECIMATED

FD DATA

DECIMATED

DCOA/DCOB

CHANNEL A/B

FD BITS

CHANNEL A/B

Figure 2. Decimated Noninterleaved CMOS Mode D

CLK+

t

PD

DECIMATED

CMOS DATA

DECIMATED

FD DATA

DECIMATED

DCOA/DCOB

Figure 3. Decimated Noninterleaved CMOS Mode Data and Fast Detect Out

CHANNEL A/B

t

S

DATA BITS

FD BITS

t

DCO

CHANNEL A/B

FD BITS

t

H

CHANNEL A/B

FD BITS

DATA BIT S

CHANNEL A/B

FD BITS

CHANNEL A/B

FD BITS

DATA BIT S

ata and Fast Detect Output Timing (Fast Detect Mode Select Bits = 000)

t

DCO

CHANNEL A/B

DATA BITS

CHANNEL A/B

FD BITS

t

H

CHANNEL A/B

DATA BITS

CHANNEL A/B

FD BITS

put Timing (Fast Detect Mode Select Bits = 001 Through Fast Detect Mode Select Bits = 100)

06708-109

06708-002

Rev. 0 | Page 10 of 80

AD6653

www.BDTIC.com/ADI

CLK+

t

PD

t

DCO

OUTPUT DATA

DECIMATED

INTERLEAVED

CMOS DATA

DECIMATED

INTERLEAVED

FD DATA

DECIMATED

DCO

CLK+

DECIMAT ED

CMOS IQ

CMOS FD

DATA

DECIMAT ED

DCOA/DCOB

CLK–

CHANNEL A:

DATA

CHANNEL A:

FD BITS

CHANNEL A/B:

Q DATA

CHANNEL A/B:

FD BITS

CHANNEL B:

DATA

CHANNEL B:

FD BITS

Figure 4. Decimated Interleaved CMO

t

PD

CHANNEL A/B:

I DATA

CHANNEL A/B:

FD BITS

t

S

t

H

CHANNEL A:

DATA

CHANNEL A:

FD BITS

t

S

CHANNEL A/B:

Q DATA

CHANNEL A/B:

FD BITS

CHANNEL B:

DATA

CHANNEL B:

FD BITS

t

H

S Mode Data and Fast Detect Output Timing

t

DCO

CHANNEL A/B:

I DATA

CHANNEL A/B:

FD BITS

Figure 5. Decimated IQ Mode CMOS Data and Fast Detect Output Timing

CHANNEL A:

DATA

CHANNEL A:

FD BITS

CHANNEL A/B:

Q DATA

CHANNEL A/B:

FD BITS

CHANNEL B:

DATA

CHANNEL B:

FD BITS

CHANNEL A/ B:

I DATA

CHANNEL A/ B:

FD BITS

06708-003

06708-004

CLK+

LVDS

DATA

LVDS

FAST DET

DCO–

DCO+

t

PD

CHANNEL A:

DATA

CHANNEL A:

FD

Figure 6. Decimated Interleaved

CHANNEL B:

DATA

CHANNEL B:

FD

CHANNEL A:

DATA

CHANNEL A:

FD

t

DCO

CHANNEL B:

DATA

CHANNEL B:

FD

LVDS Mode Data and Fast Detect Output Timing

CHANNEL A:

DATA

CHANNEL A:

FD

06708-005

CLK+

SYNC

t

SSYNC

t

HSYNC

06708-006

Figure 7. SYNC Timing Inputs

Rev. 0 | Page 11 of 80

AD6653

S

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CLK+

CLK–

MI SCLK

SMI SDFS

SMI SDO

t

CSSCLK

t

SSCLKSDFS

Figure 8. Signal Monitor SPORT

t

SSCLKSDFS

Output Timing

DATA DATA

06708-007

Rev. 0 | Page 12 of 80

AD6653

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ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

ELECTRICAL

AVDD, DVDD to AGND −0.3 V to +2.0 V DRVDD to DRGND −0.3 V to +3.9 V AGND to DRGND −0.3 V to +0.3 V VIN+A/VIN+B, VIN−A/VIN−B to AGND −0.3 V to AVDD + 0.2 V CLK+, CLK− to AGND −0.3 V to +3.9 V SYNC to AGND −0.3 V to +3.9 V VREF to AGND −0.3 V to AVDD + 0.2 V SENSE to AGND −0.3 V to AVDD + 0.2 V CML to AGND −0.3 V to AVDD + 0.2 V RBIAS to AGND −0.3 V to AVDD + 0.2 V CSB to AGND −0.3 V to +3.9 V SCLK/DFS to DRGND −0.3 V to +3.9 V SDIO/DCS to DRGND −0.3 V to DRVDD + 0.3 V SMI SDO/OEB to DRGND −0.3 V to DRVDD + 0.3 V SMI SCLK/PDWN to DRGND −0.3 V to DRVDD + 0.3 V SMI SDFS to DRGND −0.3 V to DRVDD + 0.3 V D0A/D0B through D11A/D11B

to DRGND FD0A/FD0B through FD3A/FD3B

to DRGND DCOA/DCOB to DRGND −0.3 V to DRVDD + 0.3 V

ENVIRONMENTAL

Operating Temperature Range

(Ambient)

Maximum Junction Temperature

Under Bias

Storage Temperature Range

(Ambient)

−0.3 V to DRVDD + 0.3 V

−40°C to +85°C

150°C

−65°C to +125°C

Stresses above those listed under Absolute Maximum Ratings

y cause permanent damage to the device. This is a stress

ma rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints and maximizes the thermal capability of the package.

Table 7. Thermal Resistance

Airflow Package Typ e

64-Lead LFCSP

9 mm × 9 mm (CP-64-3)

1

Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.

2

Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

3

Per MIL-Std 883, Method 1012.1.

4

Per JEDEC JESD51-8 (still air).

Ve

lo city

(m/s) θ

0 18.8 0.6 6.0 °C/W

1.0 16.5 °C/W

2.0 15.8 °C/W

1, 2

JA

1, 3

θ

JC

1, 4

θ

Unit

JB

Typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown, airflow increases heat dissipation, which reduces θ

. In addition, metal in direct contact with the

JA

package leads from metal traces, through holes, ground, and power planes, reduces the θ

.

JA

ESD CAUTION

Rev. 0 | Page 13 of 80

AD6653

www.BDTIC.com/ADI

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

DRGND

D3B

D2B

D1B

D0B (LSB)

DNC

DVDD

FD3B

FD2B

FD1B

FD0B

SYNC

CSB

CLK–

CLK+

49

48

SCLK/DFS

47

SDIO/DCS

46

AVDD

45

AVDD

44

VIN+B

43

VIN–B

42

RBIAS

41

CML

40

SENSE

39

VREF

38

VIN–A

37

VIN+A

36

AVDD

35

SMI SDFS

34

SMI SCLK/PDWN

33

SMI SDO/OEB

DRVDD

D4B D5B D6B D7B D8B D9B

D10B

D11B (MSB)

DCOB DCOA

DNC DNC

D0A (LSB)

D1A D2A

646362616059585756555453525150

PIN 1

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

INDICAT OR

EXPOSED PADDLE, PIN 0 (BOTTO M OF PACKAGE)

AD6653

PARALLEL CMO S

TOP VIEW

(Not to Scale)

DNC = DO NOT CONNECT

171819202122232425262728293031

D3A

D4A

D5A

D6A

D7A

D8A

D9A

D10A

FD0A

DRGND

DVDD

DRVDD

FD1A

D11A (MSB)

32

FD2A

FD3A

06708-008

Figure 9. LFCSP Parallel CMOS Pin Configuration (Top View)

Table 8. Pin Function Descriptions (Parallel CMOS Mode)

Pin No. Mnemonic Type Description

ADC Power Supplies 20, 64 DRGND Ground Digital Output Ground. 1, 21 DRVDD Supply Digital Output Driver Supply (1.8 V to 3.3 V). 24, 57 DVDD Supply Digital Power Supply (1.8 V Nominal). 36, 45, 46 AVDD Supply Analog Power Supply (1.8 V Nominal). 0 AGND Ground Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package. 12, 13, 58, 59 DNC Do Not Connect. ADC Analog 37 VIN+A Input Differential Analog Input Pin (+) for Channel A. 38 VIN−A Input Differential Analog Input Pin (−) for Channel A. 44 VIN+B Input Differential Analog Input Pin (+) for Channel B. 43 VIN−B Input Differential Analog Input Pin (−) for Channel B. 39 VREF Input/Output Voltage Reference Input/Output. 40 SENSE Input Voltage Reference Mode Select. See Table 11 for details. 42 RBIAS Input/Output External Reference Bias Resistor. 41 CML Output Common-Mode Level Bias Output for Analog Inputs. 49 CLK+ Input ADC Clock Input—True. 50 CLK− Input ADC Clock Input—Complement. ADC Fast Detect Outputs 29 FD0A Output Channel A Fast Detect Indicator. See Ta ble 17 for details. 30 FD1A Output Channel A Fast Detect Indicator. See Ta ble 17 for details. 31 FD2A Output Channel A Fast Detect Indicator. See Ta ble 17 for details. 32 FD3A Output Channel A Fast Detect Indicator. See Ta ble 17 for details. 53 FD0B Output Channel B Fast Detect Indicator. See Table 17 for details. 54 FD1B Output Channel B Fast Detect Indicator. See Table 17 for details. 55 FD2B Output Channel B Fast Detect Indicator. See Table 17 for details. 56 FD3B Output Channel B Fast Detect Indicator. See Table 17 for details.

Rev. 0 | Page 14 of 80

AD6653

www.BDTIC.com/ADI

Pin No. Mnemonic Type Description

Digital Inputs 52 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 14 D0A (LSB) Output Channel A CMOS Output Data. 15 D1A Output Channel A CMOS Output Data. 16 D2A Output Channel A CMOS Output Data. 17 D3A Output Channel A CMOS Output Data. 18 D4A Output Channel A CMOS Output Data. 19 D5A Output Channel A CMOS Output Data. 22 D6A Output Channel A CMOS Output Data. 23 D7A Output Channel A CMOS Output Data. 25 D8A Output Channel A CMOS Output Data. 26 D9A Output Channel A CMOS Output Data. 27 D10A Output Channel A CMOS Output Data. 28 D11A (MSB) Output Channel A CMOS Output Data. 60 D0B (LSB) Output Channel B CMOS Output Data. 61 D1B Output Channel B CMOS Output Data. 62 D2B Output Channel B CMOS Output Data. 63 D3B Output Channel B CMOS Output Data. 2 D4B Output Channel B CMOS Output Data. 3 D5B Output Channel B CMOS Output Data. 4 D6B Output Channel B CMOS Output Data. 5 D7B Output Channel B CMOS Output Data. 6 D8B Output Channel B CMOS Output Data. 7 D9B Output Channel B CMOS Output Data. 8 D10B Output Channel B CMOS Output Data. 9 D11B (MSB) Output Channel B CMOS Output Data. 11 DCOA Output Channel A Data Clock Output. 10 DCOB Output Channel B Data Clock Output. SPI Control 48 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 47 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. 51 CSB Input SPI Chip Select. Active low. Signal Monitor Port 33 SMI SDO/OEB Input/Output Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode.

35 SMI SDFS Output Signal Monitor Serial Data Frame Sync. 34 SMI SCLK/PDWN Input/Output Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode.

Rev. 0 | Page 15 of 80

AD6653

www.BDTIC.com/ADI

DRGND

DNC

FD3+

FD3–

FD2+

FD2–

DVDD

FD1+

FD1–

FD0+

FD0–

SYNC

CSB

CLK–

CLK+

49

48

SCLK/DFS

47

SDIO/DCS

46

AVDD

45

AVDD

44

VIN+B

43

VIN–B

42

RBIAS

41

CML

40

SENSE

39

VREF

38

VIN–A

37

VIN+A

36

AVDD

35

SMI SDFS

34

SMI SCLK/PDWN

33

SMI SDO/OEB

DRVDD

DNC

DNC D0– (LSB) D0+ (LSB )

D1– D1+ D2– D2+

DCO–

DCO+

D3– D3+ D4– D4+ D5–

646362616059585756555453525150

PIN 1

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

INDICATO R

EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE)

AD6653

PARALLEL L VDS

TOP VIEW

(Not to Scale)

DNC = DO NOT CONNECT

171819202122232425262728293031

D6–

D7–

D8–

D5+

D6+

DRGND

DRVDD

D7+

DVDD

D8+

D9–

D9+

D10–

D10+

32

D11– (MSB)

D11+ (MSB)

06708-009

Figure 10. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)

Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)

Pin No. Mnemonic Type Description

ADC Power Supplies 20, 64 DRGND Ground Digital Output Ground. 1, 21 DRVDD Supply Digital Output Driver Supply (1.8 V to 3.3 V). 24, 57 DVDD Supply Digital Power Supply (1.8 V Nominal). 36, 45, 46 AVDD Supply Analog Power Supply (1.8 V Nominal). 0 AGND Ground Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package. 2, 3, 62, 63 DNC Do Not Connect. ADC Analog 37 VIN+A Input Differential Analog Input Pin (+) for Channel A. 38 VIN−A Input Differential Analog Input Pin (−) for Channel A. 44 VIN+B Input Differential Analog Input Pin (+) for Channel B. 43 VIN−B Input Differential Analog Input Pin (−) for Channel B. 39 VREF Input/Output Voltage Reference Input/Output. 40 SENSE Input Voltage Reference Mode Select. See Table 1 1 for details. 42 RBIAS Input/Output External Reference Bias Resistor. 41 CML Output Common-Mode Level Bias Output for Analog Inputs. 49 CLK+ Input ADC Clock Input—True. 50 CLK− Input ADC Clock Input—Complement. ADC Fast Detect Outputs 54 FD0+ Output Channel A/Channel B LVDS Fast Detect Indicator 0—True. See Table 17 for details. 53 FD0− Output

Channel A/Channel B LVDS Fast Detect Indicator 0—Complement. See Table 1 7

r details.

fo 56 FD1+ Output Channel A/Channel B LVDS Fast Detect Indicator 1—True. See Table 17 for details. 55 FD1− Output

Channel A/Channel B LVDS Fast Detect Indicator 1—Complement. See Table 1 7

r details.

fo 59 FD2+ Output Channel A/Channel B LVDS Fast Detect Indicator 2—True. See Table 17 for details. 58 FD2− Output

Channel A/Channel B LVDS Fast Detect Indicator 2—Complement. See Table 1 7

r details.

fo 61 FD3+ Output Channel A/Channel B LVDS Fast Detect Indicator 3—True. See Table 17 for details. 60 FD3− Output

Channel A/Channel B LVDS Fast Detect Indicator 3—Complement. See Table 1 7

r details.

fo

Rev. 0 | Page 16 of 80

AD6653

www.BDTIC.com/ADI

Pin No. Mnemonic Type Description

Digital Inputs 52 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 5 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0—True. 4 D0− (LSB) Output Channel A/Channel B LVDS Output Data 0—Complement. 7 D1+ Output Channel A/Channel B LVDS Output Data 1—True. 6 D1− Output Channel A/Channel B LVDS Output Data 1—Complement. 9 D2+ Output Channel A/Channel B LVDS Output Data 2—True. 8 D2− Output Channel A/Channel B LVDS Output Data 2—Complement. 13 D3+ Output Channel A/Channel B LVDS Output Data 3—True. 12 D3− Output Channel A/Channel B LVDS Output Data 3—Complement. 15 D4+ Output Channel A/Channel B LVDS Output Data 4 —True. 14 D4− Output Channel A/Channel B LVDS Output Data 4—Complement. 17 D5+ Output Channel A/Channel B LVDS Output Data 5—True. 16 D5− Output Channel A/Channel B LVDS Output Data 5—Complement. 19 D6+ Output Channel A/Channel B LVDS Output Data 6—True. 18 D6− Output Channel A/Channel B LVDS Output Data 6—Complement. 23 D7+ Output Channel A/Channel B LVDS Output Data 7—True. 22 D7− Output Channel A/Channel B LVDS Output Data 7—Complement. 26 D8+ Output Channel A/Channel B LVDS Output Data 8—True. 25 D8− Output Channel A/Channel B LVDS Output Data 8—Complement. 28 D9+ Output Channel A/Channel B LVDS Output Data 9—True. 27 D9− Output Channel A/Channel B LVDS Output Data 9—Complement. 30 D10+ Output Channel A/Channel B LVDS Output Data 10—True. 29 D10− Output Channel A/Channel B LVDS Output Data 10—Complement. 32 D11+ (MSB) Output Channel A/Channel B LVDS Output Data 11—True. 31 D11− (MSB) Output Channel A/Channel B LVDS Output Data 11—Complement. 11 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 10 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control

48 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 47 SDIO/DCS Input/Output SPI Serial Data Input/Output/Duty Cycle Stabilizer in External Pin Mode. 51 CSB Input SPI Chip Select. Active low.

Signal Monitor Port

33 SMI SDO/OEB Input/Output

35 SMI SDFS Output Signal Monitor Serial Data Frame Sync. 34 SMI SCLK/PDWN Input/Output

Signal Monitor Serial Data O Pin Mode.

Signal Monitor Serial Clock Output/Power-D Pin Mode.

utput/Output Enable Input (Active Low) in External

own Input (Active High) in External

Rev. 0 | Page 17 of 80

AD6653

V

C

S

A

V

www.BDTIC.com/ADI

EQUIVALENT CIRCUITS

LK+

IN

06708-010

Figure 11. Equivalent Analog Input Circuit

AVDD

1.2V

10kΩ 10kΩ

Figure 12. Equivalent Clock lnp

DRVDD

ut Circuit

CLK–

SCLK/DFS

Figure 15. Equivalent SCLK

SENSE

06708-011

1kΩ

26kΩ

/DFS Input Circuit

1kΩ

06708-014

06708-015

Figure 16. Equivalent SENSE Circuit

DRGND

6708-012

Figure 13. Equivalent Digital Output Circuit

DRVDD

26kΩ

DIO/DCS

1kΩ

06708-013

Figure 14. Equivalent SDIO/DCS Circuit or SMI SDFS Circuit

VDD

26kΩ

CSB

1kΩ

06708-016

Figure 17. Equivalent CSB Input Circuit

AVDD

REF

6kΩ

06708-017

Figure 18. Equivalent VREF Circuit

Rev. 0 | Page 18 of 80

AD6653

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 150 MSPS, DCS enabled, 1.0 V internal reference, 2 V p-p differential input, VIN = −1.0 dBFS, 64k sample, T the location of the second and third harmonics is noted when they fall in the pass band of the filter.

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

SECOND HARMONIC

THIRD HARMONIC

= 25°C, NCO enabled, FIR filter enabled, unless otherwise noted. In the FFT plots that follow,

A

150MSPS

2.4MHz @ –1dBF S SNR = 70.9dBc (71. 9dBFS) SFDR = 83.2dBc

f

= 18.75MHz

NCO

0

150MSPS

140.1MHz @ –1dBF S SNR = 70.6dBc (71.6dBFS)

–20

SFDR = 82.9dBc

f

= 126MHz

NCO

–40

–60

–80

AMPLITUDE ( dBFS)

–100

THIRD HARMONIC

SECOND HARMONIC

–120

–140

03

FREQUENCY (MHz)

Figure 19. AD6653-150 Single-Tone FFT with f

0

150MSPS

30.3MHz @ –1dBF S SNR = 71.0dBc (72.0dBFS)

–20

SFDR = 92.3dBc

f

= 24MHz

NCO

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

–140

03

FREQUENCY (MHz)

Figure 20. AD6653-150 Single-Tone FFT with f

0

150MSPS

70.1MHz @ –1dBF S SNR = 70.8dBc (71.8dBFS)

–20

SFDR = 82.9dBc

f

= 56MHz

NCO

–40

= 2.4 MHz, f

IN

= 30.3 MHz, f

IN

–120

5

30252015105

06708-018

= 18.75 MHz

NCO

5

30252015105

06708-019

= 24 MHz

NCO

–140

Figure 22. AD6653-150 Single-Tone FFT with f

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

–140

Figure 23. AD6653-150 Single-Tone FFT with f

–20

–40

035

0

150MSPS

220.1MHz @ –1dBF S SNR = 70.0dBc (71.0dBFS) SFDR = 80.9dBc

f

= 205MHz

NCO

03530252015105

0

150MSPS

332.1MHz @ –1dBF S SNR = 69.4dBc (70.4dBFS) SFDR = 91.2dBc

f

= 321.5MHz

NCO

FREQUENCY (MHz)

IN

THIRD HARMONIC

FREQUENCY (MHz)

IN

30252015105

= 140.1 MHz, f

= 220.1 MHz, f

= 126 MHz

NCO

= 205 MHz

NCO

06708-021

06708-022

–60

–80

AMPLITUDE ( dBFS)

–100

–120

–140

03

THIRD HARMONIC

FREQUENCY (MHz)

Figure 21. AD6653-150 Single-Tone FFT with f

= 70.1 MHz, f

IN

5

30252015105

06708-020

= 56 MHz

NCO

–60

–80

AMPLITUDE ( dBFS)

–100

–120

–140

03530252015105

Figure 24. AD6653-150 Single-Tone FFT with f

Rev. 0 | Page 19 of 80

FREQUENCY (MHz)

f

= 321.5 MHz

NCO

= 332.1 MHz,

IN

06708-023

AD6653

www.BDTIC.com/ADI

0

150MSPS

445.1MHz @ –1dBF S SNR = 69.1dBc (70.1dBFS)

–20

SFDR = 73.7dBc

f

= 429MHz

NCO

–40

–60

–80

AMPLITUDE ( dBFS)

100

–

SECOND HARMONIC

THIRD HARMONIC

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

125MSPS

70.3MHz @ –1dBFS SNR = 70.9dBc (71. 9dBFS) SFDR = 85.9dBc

f

= 78MHz

NCO

THIRD HARMONIC

–120

–140

03

FREQUENCY (MHz)

Figure 25. AD6653-150 Single-Tone FFT with f

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

–140

SECOND HARMONIC

THIRD HARMONIC

03

FREQUENCY (MHz)

Figure 26. AD6653-125 Single-Tone FFT with f

0

125MSPS

30.3MHz @ –1dBF S SNR = 70.9dBc (71.9dBFS)

–20

SFDR = 90.7dBc

f

= 21MHz

NCO

–40

30252015105

= 445.1 MHz, f

IN

125MSPS

2.4MHz @ –1dBF S SNR = 71.0dBc (72. 0dBFS) SFDR = 84.6dBc

f

= 15.75MHz

NCO

= 2.4 MHz, f

IN

252015105

NCO

= 429 MHz

NCO

= 15.75 MHz

–120

–140

5

06708-024

030252015105

Figure 28. AD6653-125 Single-Tone FFT with f

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

–140

0

06708-025

030252015105

Figure 29. AD6653-125 Single-Tone FFT with f

0

–20

–40

FREQUENCY (MHz)

IN

125MSPS

140.1MHz @ –1dBF S SNR = 70.6dBc (71. 6dBFS) SFDR = 86.1dBc

f

NCO

FREQUENCY (MHz)

= 140.1 MHz, f

IN

125MSPS

220.1MHz @ –1dBF S SNR = 70.2dBc (71. 2dBFS) SFDR = 87.9dBc

f

NCO

= 70.3 MHz, f

= 142MHz

THIRD HARMONIC

= 231MHz

= 78 MHz

NCO

= 142 MHz

NCO

06708-027

06708-028

–60

–80

AMPLITUDE ( dBFS)

–100

–120

–140

03

FREQUENCY (MHz)

Figure 27. AD6653-125 Single-Tone FFT with f

252015105

= 30.3 MHz, f

IN

THIRD

HARMONIC

0

06708-026

= 21 MHz

NCO

–60

–80

AMPLITUDE ( dBFS)

–100

–120

–140

030252015105

Figure 30. AD6653-125 Single-Tone FFT with f

Rev. 0 | Page 20 of 80

FREQUENCY (MHz)

= 220.1 MHz, f

IN

= 231 MHz

NCO

06708-029

AD6653

–

www.BDTIC.com/ADI

120

95

SNR/SFDR (dBc AND dBFS)

100

80

60

40

20

0

–90 0–10–20–30–40–50–60–70–80

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

SNR (dBc)

INPUT AMPLITUDE (dBFS)

Figure 31. AD6653-150 Single-Tone S

= 2.4 MHz, f

f

IN

120

SFDR (dBFS)

SNR (dBc)

INPUT AMPLITUDE (dBFS)

SNR/SFDR (dBc AND dBFS)

100

80

60

40

20

0

–90 0–10–20–30–40–50–60–70–80

SNR (dBFS)

SFDR (dBc)

Figure 32. AD6653-150 Single-Tone S

= 98.12 MHz, f

f

IN

85dB REFERENCE LI NE

NR/SFDR vs. Input Amplitude (A

= 18.75 MHz

NCO

85dB REFERENCE LI NE

NR/SFDR vs. Input Amplitude (A

= 100.49 MHz

NCO

) with

IN

) with

IN

90

85

80

75

SNR/SFDR (dBc)

70

65

60

0440035030025020015010050

06708-030

SFDR = –40°C

Figure 34. AD6653-125 Single-Tone SNR/SFDR vs. Input Frequency (f

SFDR = +85°C

SNR = +25°C SNR = +85°C SNR = –40°C

INPUT FREQ UENCY (MHz)

SFDR = +25°C

50

06708-033

) and

IN

Temperature with DRVDD = 3.3 V

1.5

–2.0

OFFSET

–2.5

–3.0

GAIN ERROR (%F SR)

–3.5

–4.0

–40 806040200–20

06708-031

GAIN

TEMPERATURE (° C)

0.5

0.4

0.3

0.2

0.1

0

OFFSET ERROR (%FSR)

06708-034

Figure 35. AD6653-150 Gain and Offset vs. Temperature

95

90

SFDR = +85°C

85

80

75

SNR/SFDR (dBc)

70

65

60

04

SFDR = –40°C

SNR = +25°C SNR = +85°C SNR = –40°C

INPUT FREQ UENCY (MHz)

25020015010050

SFDR = +25°C

Figure 33. AD6653-125 Single-Tone SNR/SFDR vs. Input Frequency (f

Temperature with DRVDD = 1.8 V

50400350300

06708-032

) and

IN

Rev. 0 | Page 21 of 80

0

–20

SFDR (dBc)

–40

–60

–80

SFDR/IMD3 (dBc AND dBFS )

–100

–120

–90 –78 –66 –54 –42 –30 –18 –6

IMD3 (d Bc)

SFDR (dBFS)

IMD3 (dBFS)

INPUT AMPLITUDE (dBFS )

Figure 36. AD6653-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (A

= 29.12 MHz, f

f

IN1

= 32.12 MHz, fS = 150 MSPS, f

IN2

= 22 MHz

NCO

) with

IN

06708-035

AD6653

www.BDTIC.com/ADI

0

–20

SFDR (dBc)

–40

IMD3 (d Bc)

–60

–80

SFDR/IMD3 (dBc AND dBFS )

SFDR (dBFS)

–100

IMD3 (dBFS)

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

150MSPS

169.12MHz @ –7dBF S

172.12MHz @ –7dBF S SFDR = 83.6dBc (90.6dBFS )

f

= 177MHz

NCO

–120

–90 –78 –66 –54 –42 –30 –18 –6

INPUT AMPLITUDE (dBFS )

Figure 37. AD6653-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (A

= 169.12 MHz, f

f

IN1

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

–140

0 5 10 15 20 25 30

Figure 38. AD6653-125, Two 64k WCDMA Carriers with f

0

150MSPS

29.12MHz @ –7dBF S

32.12MHz @ –7dBF S

–20

SFDR = 91.1dBc (98.1dBFS)

f

NCO

–40

= 172.12 MHz, fS = 150 MSPS, f

IN2

FREQUENCY ( MHz)

= 122.88 MHz, f

f

S

= 22MHz

= 168.96 MHz

NCO

= 177 MHz

NCO

= 170 MHz,

IN

) with

IN

–140

0330252015105

06708-036

Figure 40. AD6653-150 Two-Tone FFT with f

= 172.12 MHz, fS = 150 MSPS, f

f

IN2

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

06708-037

–120

0 37.530.022.515.07. 5

FREQUENCY (MHz)

FREQUENCY (MHz )

= 169.12 MHz,

IN1

= 177 MHz

NCO

NPR = 61.9dBc NOTCH @ 18.5MHz NOTCH WIDT H = 3MHz

5

06708-039

06708-040

Figure 41. AD6653-150 Noise Power Ratio (NPR)

95

90

85

SFDR

–60

–80

AMPLITUDE ( dBFS)

–100

–120

–140

03

FREQUENCY (MHz)

Figure 39. AD6653-150 Two-Tone FFT with f

= 150 MSPS, f

f

S

NCO

= 29.12 MHz, f

IN1

= 22 MHz

30252015105

5

06708-038

= 32.12 MHz,

IN2

80

75

SNR/SFDR (dBc)

70

65

60

0 150125100755025

SAMPLE RATE (MSPS)

Figure 42. AD6653-150 Single-Tone SNR/SFDR vs. Sample Rate (f

f

Rev. 0 | Page 22 of 80

= 2.3 MHz

IN

SNR

) with

S

06708-041

AD6653

www.BDTIC.com/ADI

12

0.21 LSB rms

90

10

8

6

4

NUMBER OF HIT S (1M)

2

0

N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3

OUTPUT CODE

Figure 43. AD6653 Grounded Input Histogram

90

85

SFDR DCS ON

80

SFDR DCS OFF

SNR DCS OFF

SNR/SFDR (dBc)

75

SNR DCS ON

70

85

SFDR

80

75

SNR/SFDR (dBc)

SNR

70

65

0.2 0.4 0. 6 0. 8 1. 0 1.2 1.4 1.6

06708-042

INPUT COMMON-MODE VOLTAGE (V)

06708-044

Figure 45. AD6653-150 SNR/SFDR vs. Input Common Mode (VCM) with

= 30.3 MHz, f

f

IN

= 45 MHz

NCO

65

20 30 40 50 60 70 80

DUTY CYCLE (%)

Figure 44. AD6653-150 SNR/SFDR vs. Duty Cycle with f

= 45 MHz

f

NCO

= 30.3 MHz,

IN

06708-043

Rev. 0 | Page 23 of 80

AD6653

www.BDTIC.com/ADI

THEORY OF OPERATION

The AD6653 has two analog input channels, two decimating channels, and two digital output channels. The intermediate frequency (IF) input signal passes through several stages before appearing at the output port(s) as a filtered, decimated digital signal.

The dual ADC design can be used for diversity reception of signals,

here the ADCs operate identically on the same carrier but from

w two separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample any f

/2 frequency

S

segment from dc to 150 MHz, using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance. Operation to 450 MHz analog input is permitted but occurs at the expense of increased ADC noise and distortion.

In nondiversity applications, the AD6653 can be used as a b

aseband receiver, where one ADC is used for I input data,

and the other is used for Q input data.

Synchronization capability is provided to allow synchronized timin

g between multiple channels or multiple devices. The NCO phase can be set to produce a known offset relative to another channel or device.

Programming and control of the AD6653 are accomplished usin

g a 3-bit SPI-compatible serial interface.

ADC ARCHITECTURE

AD6653 architecture consists of a front-end sample-and-hold amplifier (SHA), followed by a pipelined switched-capacitor ADC. The quantized outputs from each stage are combined into a final 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low

esolution flash ADC connected to a switched-capacitor digital-

r to-analog converter (DAC) and an interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC.

The input stage of each channel contains a differential SHA that ca

n be ac- or dc-coupled in differential or single-ended modes. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD6653 is a differential switchedcapacitor SHA that has been designed for optimum performance while processing a differential input signal.

The clock signal alternatively switches the SHA between sample mode and hold mode (see Figure 46). When the SHA is switched in

to sample mode, the signal source must be capable of charging

the sample capacitors and settling within 1/2 of a clock cycle.

A small resistor in series with each input can help reduce the

eak transient current required from the output stage of the

p driving source. A shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC input; therefore, the precise values are dependent on the application.

In IF undersampling applications, any shunt capacitors should b

e reduced. In combination with the driving source impedance, the shunt capacitors limit input bandwidth. Refer to Application Note AN-742, Frequency Domain Response of Switched-

Capacitor ADCs; Application Note AN-827, A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs; and the Analog Dialogue article, “

Wi

deband A/D Converters,” for more information on this subject

(see www.analog.com).

Transformer-Coupled Front-End for

In general, the precise values are

dependent on the application.

S

C

H

C

H

S

06708-048

VIN+

VIN–

C

PIN, PAR

C

PIN, PAR

Figure 46. Switched-Capac

S

C

S

H

C

S

itor SHA Input

For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC.

An internal differential reference buffer creates positive and n

egative reference voltages that define the input span of the ADC core. The output common mode of the reference buffer is set to VCMREF (approximately 1.6 V).

Input Common Mode

The analog inputs of the AD6653 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that V

= 0.55 × AVDD is

CM

recommended for optimum performance, but the device functions over a wider range with reasonable performance (see Figure 45). An o

n-board common-mode voltage reference is included in the design and is available from the CML pin. Optimum performance is achieved when the common-mode voltage of the analog input is set by the CML pin voltage (typically 0.55 × AVDD).

Rev. 0 | Page 24 of 80

ANALOG DEVICES AD6653 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

SPECIFICATIONS

ADC DC SPECIFICATIONS

ADC AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING SPECIFICATIONS

Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

EQUIVALENT CIRCUITS

TYPICAL PERFORMANCE CHARACTERISTICS

THEORY OF OPERATION

ADC ARCHITECTURE

ANALOG INPUT CONSIDERATIONS

Input Common Mode