ANALOG DEVICES AD6650 Service Manual

AD6650 Diversity IF-to-Baseband

K

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FEATURES

116 dB dynamic range Digital VGA I/Q demodulators Active low-pass filters Dual wideband ADC Programmable decimation and channel filters VCO and phase-locked loop circuitry Serial data output ports Intermediate frequencies of 70 MHz to 260 MHz 10 dB noise figure +43 dBm input IP2 at 70 MHz IF

−9.5 dBm input IP3 at 70 MHz IF

3.3 V I/O and CMOS core Microprocessor interface JTAG boundary scan

APPLICATIONS

PHS or GSM/EDGE single carrier, diversity receivers Microcell and picocell systems Wireless local loop

GSM/EDGE Narrow-Band Receiver

AD6650

Smart antenna systems Software radios In-building wireless telephony

PRODUCT DESCRIPTION

The AD6650 is a diversity intermediate frequency-to-baseband (IF-to-baseband) receiver for GSM/EDGE. This narrow-band receiver consists of an integrated DVGA, IF-to-baseband I/Q demodulators, low-pass filtering, and a dual wideband ADC. The chip can accommodate IF input from 70 MHz to 260 MHz. The receiver architecture is designed such that only one external surface acoustic wave (SAW) filter for main and one for diversity are required in the entire receive signal path to meet GSM/EDGE blocking requirements.

Digital decimation and filtering circuitry provided on-chip remove unwanted signals and noise outside the channel of interest. Programmable RAM coefficient filters allow antialiasing, matched filtering, and static equalization functions to be combined in a single cost-effective filter. The output of the channel filters is provided to the user via serial output I/Q data streams.

AIN AIN

CPOUT

VLDO

BIN

FUNCTIONAL BLOCK DIAGRAM

TWEAK GAIN

DAC

I

LPF

12-BIT

REF/4

12-BIT

SYNC

LPF

TDI

MUX

Q

MUX

I

DAC

TWEAK GAIN

TDO

TMS

VGA

PLL/

LF

VCO

VGA

0

90

JTAG

TRST

TCLK

ADC

CLK

DIVIDER

CLK

COARSE

CLK

DCC

AGC

RELIN

CTRL

AGC

RELIN

CTRL

DVDD

AVDD

DGND

AGND

TH

4

ORDER

CIC

TH

4

ORDER

CIC

LP

FILTER

LP

FILTER

TH

7

ORDER

IIR

TH

7

ORDER

IIR

RESET

Figure 1.

AD6650 GSM/

EDGE IF RECEIVER

CS

PROG.

(RCF)

PROG.

(RCF)

R/W

FIR

MICRO

DS

FINE DCC

A[2:0]

MODE [2:0]

BIST

SCL

SERIAL

PORT

BIST

D[7:0]

DTACK

SDFS SDO0 SDO1 DR

03683-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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REVISION HISTORY

1/07—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Changes to Specifications................................................................ 3

Changes to Figure 18...................................................................... 13

Changes to Power Supplies Section.............................................. 27

Changes to Ordering Guide.......................................................... 44

3/06—Revision 0: Initial Version

Rev. A | Page 2 of 44

AD6650

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SPECIFICATIONS

EXPLANATION OF TEST LEVELS

I. 100% production tested.

II. 100% p III. S IV. P

V. P VI. 100% p

VII. 100% p

C

= 40 pF on all outputs, unless otherwise specified. All timing specifications valid over VDD range of 3.0 V to 3.45 V and VDDIO

LOAD

range of 3.0 V to 3.45 V.

AC SPECIFICATIONS

AVDD and DVDD = 3.3 V, CLK = 52 MSPS (driven differentially), 50% duty cycle, unless otherwise noted. All minimum ac specifications are guaranteed from −25°C to +85°C. AC minimum specifications degrade slightly from −25°C to −40°C.

Table 1.

Parameter Temp Test Level Min Typ Max Unit

OVERALL FUNCTION

Frequency Range Full V 70 260 MHz

GAIN CONTROL

Gain Step Size 25°C V 0.094 dB

Gain Step Accuracy 25°C V ±0.047 dB

AGC Range 25°C V 36 dB

BASEBAND FILTERS

Bandwidth Full IV 3.36 3.5 3.64 MHz

Alias Rejection at 25.9 MHz 25°C V 77 dB

LO PHASE NOISE

At 10 kHz Offset 25°C V −79 dBc/Hz

At 20 kHz Offset 25°C V −87 dBc/Hz

At 50 kHz Offset 25°C V −103 dBc/Hz

At 100 kHz Offset 25°C V −112 dBc/Hz

At 200 kHz Offset 25°C V −119 dBc/Hz

At 400 kHz Offset 25°C V −125 dBc/Hz

At 600 kHz Offset 25°C V −130 dBc/Hz

At 800 kHz Offset 25°C V −133 dBc/Hz

At 1600 kHz Offset 25°C V −138 dBc/Hz

At 3000 kHz Offset 25°C V −143 dBc/Hz

GAIN ERROR 25°C V −0.7 dB PSRR (AVDD with 20 mV RMS Ripple)

At 5 kHz 25°C V −13.4 dBc

At 10 kHz 25°C V −17 dBc

At 50 kHz 25°C V −34 dBc

At 100 kHz 25°C V −39.8 dBc

At 150 kHz 25°C V −45.7 dBc

f = 70 MHz

Coarse DC Correction V −70 dB

Noise Figure2 V 10 dB

Input IP2

Input IP3

Image Rejection Full IV −49 −33 dBc

Full-Scale Input Power V 4 dBm

Input Impedance V 189.6 − j33.6 Ω

roduction tested at 25°C; sample tested at specified temperatures.

ample tested only.

arameter guaranteed by design and analysis. arameter is typical value only.

roduction tested at 25°C; sample tested at temperature extreme. roduction tested at +85°C.

1

2

Full IV 24 43 dBm Full IV −15 −9.5 dBm

Rev. A | Page 3 of 44

AD6650

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Parameter Temp Test Level Min Typ Max Unit

f = 150 MHz

Coarse DC Correction V −70 dB Noise Figure2 V 10 dB Input IP22 Full IV 24 37 dBm Input IP32 Full IV −15 −11.5 dBm Image Rejection Full IV −46.5 −33 dBc Full-Scale Input Power V 4 dBm Input Impedance V 169.3 − j59.2 Ω

f = 200 MHz

Coarse DC Correction V −70 dB Noise Figure2 V 10 dB Input IP22 Full IV 24 35 dBm Input IP32 Full IV −16 −12 dBm Image Rejection Full IV −46.5 −33 dBc Full-Scale Input Power V 4 dBm Input Impedance V 159.3 − j66.9 Ω

f = 250 MHz

Coarse DC Correction V −70 dB Noise Figure2 V 10 dB Input IP22 Full VII 24 33 dBm Input IP32 Full VII −16 −13 dBm Image Rejection Full VII −45 −33 dBc Full-Scale Input Power V 4 dBm Input Impedance V 137.1 − j72.7 Ω

1

See Figure 40 and Figure 41 for additional PSRR specifications.

2

This measurement applies for maximum gain (36 dB).

DIGITAL SPECIFICATIONS

AVDD and DVDD = 3.3 V, CLK = 52 MSPS, unless otherwise noted.

Table 2.

Parameter Temp Test Level Min Typ Max Unit

DVDD Full IV 3.0 3.3 3.45 V AVDD Full IV 3.0 3.3 3.45 V

1

T

IV −25 +25 +85 °C

AMBIENT

1

The AD6650 is guaranteed fully functional from −40°C to +85°C. All ac minimum specifications are guaranteed from −25°C to +85°C, but degrade slightly from −25°C

to −40°C.

Rev. A | Page 4 of 44

AD6650

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ELECTRICAL CHARACTERISTICS

Table 3.

Parameter (Conditions) Temp Test Level Min Typ Max Unit

LOGIC INPUTS

Logic Compatibility Full IV 3.3 V CMOS

Digital Logic

Logic 1 Voltage Full IV 2.0 VDD V Logic 0 Voltage Full IV 0 0.8 V Logic 1 Current 25°C V 60 μA Logic 0 Current 25°C V 7 μA

Input Capacitance 25°C V 5 pF

CLOCK INPUTS

Differential Input Voltage

Common-Mode Input Voltage 25°C V DVDD/2 V

Differential Input Resistance 25°C V 7.5 kΩ

Differential Input Capacitance 25°C V 5 pF

LOGIC OUTPUTS

Logic Compatibility Full 3.3 V CMOS/TTL

Logic 1 Voltage (IOH = 0.25 mA) Full IV 2.4 VDD − 0.2 V

Logic 0 Voltage (IOL = 0.25 mA) Full IV 0.2 0.8 V

IDD SUPPLY CURRENT

CLK = 52 MHz (GSM Example)

I

Full VII 155 mA

DVDD

I

Full VII 360 mA

AVDD

POWER DISSIPATION

CLK = 52 MHz (GSM/EDGE Example) Full VII 1.7 2.1 W

1

All ac specifications are tested by driving CLK and

GENERAL TIMING CHARACTERISTICS

Table 4.

Parameter (Conditions) Symbol Temp Test Level Min Typ Max Unit

CLK TIMING REQUIREMENTS

CLK Period

CLK Width Low t

CLK Width High t

RESET TIMING REQUIREMENTS

RESET Width Low

PIN_SYNC TIMING REQUIREMENTS

SYNC to ↑ CLK Setup Time

SYNC to ↑ CLK Hold Time

SERIAL PORT TIMING REQUIREMENTS: SWITCHING CHARACTERISTICS

↑ CLK to ↑ SCLK Delay (Divide-by-1)

↑ CLK to ↑ SCLK Delay (For Any Other Divisor)

↑ CLK to ↓ SCLK Delay (Divide-by-2 or Even Number)

↓ CLK to ↓ SCLK Delay (Divide-by-3 or Odd Number)

↑ SCLK to SDFS Delay

↑ SCLK to SDO0 Delay

↑ SCLK to SDO1 Delay

↑ SCLK to DR Delay

1

Minimum specification is based on a 104 MSPS clock rate (an internal divide-by-2 must be used with a 104 MSPS clock rate); maximum specification is based on a

52 MSPS clock rate. This device is optimized to operate at a clock rate of 52 MSPS or 104 MSPS.

2

The timing parameters for SCLK, SDFS, SDO0, SDO1, and DR apply to both Channel 0 and Channel 1.

1

CLK

differentially.

25°C V 0.4 3.6 V p-p

t

Full I 9.6 19.2 ns

CLK

Full IV 0.5 × t

CLKL

Full IV 0.5 × t

CLKH

ns

CLK

ns

CLK

t

Full IV 30 ns

SSF

Full IV −3 ns

t

SS

tHS Full IV 6 ns

2

t

Full IV 3.2 12.5 ns

DSCLK1

t

Full IV 4.4 16 ns

DSCLKH

t

Full IV 4.7 16 ns

DSCLKL

Full IV 4 14 ns

t

DSCLKLL

Full IV 1 2.6 ns

t

DSDFS

Full IV 0.5 3.5 ns

t

DSDO0

t

Full IV 0.5 3.5 ns

DSDO1

t

Full IV 1 3.5 ns

DSDR

Rev. A | Page 5 of 44

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MICROPROCESSOR PORT TIMING CHARACTERISTICS

All timing specifications valid over VDD range of 3.0 V to 3.45 V and VDDIO range of 3.0 V to 3.45 V.

Table 5. Microprocessor Port, Mode INM (MODE = 0); Asynchronous Operation

Parameter Symbol Temp Test Level Min Typ Max Unit

WRITE TIMING

WR (R/W) to RDY (DTACK) Hold Time Address/Data to WR (R/W) Setup Time Address/Data to RDY (DTACK) Hold Time WR (R/W) to RDY (DTACK) Delay WR (R/W) to RDY (DTACK) High Delay

READ TIMING

Address to RD (DS) Setup Time Address to Data Hold Time Data Three-state Delay RDY (DTACK) to Data Delay

1

RD (DS) to RDY (DTACK) Delay RD (DS) to RDY (DTACK) High Delay

1

Timing is guaranteed by design.

2

Specification pertains to control signals R/W, WR, DS, RD, and CS such that the minimum specification is valid after the last control signal has reached a valid logic level.

1

t

Full IV 0.0 ns

HWR

t

Full IV 0.0 ns

SAM

t

Full IV 0.0 ns

HAM

2

t t

DRDY

ACC

SAM

HAM

Full IV 9.0 15.0 ns

Full IV 4 × t

13 × t

CLK

ns

CLK

Full IV 0.0 ns

Full IV 0.0 ns tZD Full V 12 ns tDD Full IV 0.0 ns

2

t

1

t

DRDY

ACC

Full IV 9.0 15.0 ns

Full IV 4 × t

13 × t

CLK

ns

Table 6. Microprocessor Port, Mode MNM (MODE = 1)

Parameter Symbol Temp Test Level Min Typ Max Unit

WRITE TIMING

t

DS (RD) to DTACK (RDY) Hold Time R/W (WR) to DTACK (RDY) Hold Time Address/Data to R/W (WR) Setup Time Address/Data to R/W (WR) Hold Time DS (RD) to DTACK (RDY) Delay

2

R/W (WR) to DTACK (RDY) Low Delay

1

Full IV 15.0 ns

HDS

t

Full IV 15.0 ns

HRW

t

Full IV 0.0 ns

SAM

t

Full IV 0.0 ns

HAM

t

Full V 16 ns

DDTACK

t

Full IV 4 × t

ACC

13 × t

CLK

ns

CLK

READ TIMING

t

DS (RD) to DTACK (RDY) Hold Time Address to DS (RD) Setup Time Address to Data Hold Time

1

Full IV 15.0 ns

HDS

t

Full IV 0.0 ns

SAM

t

Full IV 0.0 ns

HAM

Data Three-State Delay tZD Full V 13 ns DTACK (RDY) to Data Delay DS (RD) to DTACK (RDY) Delay DS (RD) to DTACK (RDY) Low Delay

1

Timing is guaranteed by design.

2

DTACK

is an open-drain device and must be pulled up with a 1 kΩ resistor.

1

2

1

tDD Full IV 0.0 ns t

Full V 16 ns

DDTACK

t

Full IV 4 × t

ACC

13 × t

CLK

ns

CLK

Rev. A | Page 6 of 44

AD6650

SCLK

S

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TIMING DIAGRAMS

RESET

t

SSF

RESET

Figure 2.

Timing Requirements

CLK

t

DSCLKH

Figure 3. SCLK Switching Characteristics (Divide-by-1)

CLK

t

DSCLKH

t

DSCLKL

03683-002

03683-003

CLK

03683-004

Figure 4. SCLK Switching Characteristics (Divide-by-2 or Even Integer)

CLK

t

DSCLKH

t

DSCLKL L

03683-005

Figure 5. SCLK Switching Characteristics (Divide-by-3 or Odd Integer)

CLK

t

DSDR

DR

03683-006

Figure 6. SCLK, DR Switching Characteristics

CLK

t

DSDFS

SDFS

03683-007

Figure 7. SCLK, SDFS Switching Characteristics

SCLK

t

DSD0/tDSD1

DO0/SDO1

Figure 8. SCLK, SDO0/SDO1 Switching Characteristics

Rev. A | Page 7 of 44

03683-008

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CLK

t

HS

03683-009

SYNC

t

SS

Figure 9. SYNC Timing Inputs

RD (DS)

t

HWR

R (R/W)

CS

t

HAM

03683-010

A[2:0]

D[7:0]

RDY

(DTACK)

t

SAM

VALID ADDRESS

t

SAM

VALID DATA

t

DRDY

t

ACC

NOTES

1.

t

ACCESS TIME DEPENDS ON THE ADDRESS ACCESS ED. ACCESS TI ME IS MEASURED

ACC

FROM FALLING EDGE OF WRTO RISING EDGE OF RDY.

2.

t

REQUIRES A MAXIMUM OF NINE CLK PERI ODS.

ACC

Figure 10. INM Microport Write Timing Requirements

RD (DS)

R (R/W)

CS

t

SAM

t

ACC

VALID ADDRESS

A[2:0]

t

ZD

D[7:0]

t

DRDY

RDY

(DTACK)

NOTES

1.

t

ACCESS TIME DE PENDS ON THE ADDRESS ACCESSED. ACCESS TI ME IS MEASURED

ACC

FROM FALLING EDGE OF RD TO RISING EDGE OF RDY.

2.

t

REQUIRES A MAXIMUM OF 13 CLK PERIODS.

ACC

Figure 11. INM Microport Read Timing Requirements

t

DD

Rev. A | Page 8 of 44

VALID DATA

t

HAM

t

ZD

03683-011

AD6650

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t

HDS

DS (RD)

t

HRW

R/W (W R)

CS

t

ACC

t

HAM

t

DDTACK

03683-012

t

SAM

A[2:0]

D[7:0]

DTACK

(RDY)

NOTES

1.

t

ACCESS TIME DEPENDS ON THE ADDRESS ACCESSE D. ACCESS TIM E IS MEASURED

ACC

FROM FALLING EDG E OF DS TO FALLING EDGE OF DTACK.

2.

t

REQUIRES A MAXIMUM OF NINE CLK PERI ODS.

ACC

VALID ADDRESS

t

SAM

VALID DATA

Figure 12. MNM Microport Write Timing Requirements

t

HDS

DS (RD)

R/W (WR)

CS

t

SAM

A[2:0]

D[7:0]

DTACK

(RDY)

t

ZD

t

ACC

NOTES

1.

t

ACCESS TIME DEPENDS ON THE ADDRESS ACCESS ED. ACCESS TI ME IS MEASURED

ACC

FROM FALLING EDGE OF DSTO THE FALLING EDGE OF DTACK.

2.

t

REQUIRES A MAXIMUM O F 13 CLK PERIODS.

ACC

VALID ADDRESS

t

DD

t

DDTACK

VALID DATA

t

HAM

t

ZD

03683-013

Figure 13. MNM Microport Read Timing Requirements

Rev. A | Page 9 of 44

AD6650

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ABSOLUTE MAXIMUM RATINGS

Table 7.

Parameter Rating

Supply Voltage −0.3 V to +3.6 V Input Voltage −0.3 V to +3.6 V Output Voltage Swing −0.3 V to VDDIO + 0.3 V Load Capacitance 200 pF Junction Temperature Under Bias 125°C Storage Temperature Range −65°C to +150°C Lead Temperature (5 sec) 280°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

121-lead chip scale package ball grid array:

= 22.8°C/W, no airflow, measurements made in the

θ

JA

horizontal position on a 4-layer board.

= 20.2°C/W, 200 LFPM airflow, measurements made in the

θ

JA

horizontal position on a 4-layer board.

= 20.7°C/W, no airflow, soldered on an 8-layer board with

θ

JA

two layers dedicated as ground planes.

ESD CAUTION

Rev. A | Page 10 of 44

AD6650

A

R

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1 CORNE

INDEX AREA

6

3

245

1

AD6650

TOP VIEW

(Not to Scale)

Figure 14. Pin Configuration

Table 8. Pin Configuration

1 2 3 4 5 6 7 8 9 10 11

DGND TDI TMS

A

SDFS SCLK TDO TCLK SYNC DNC AVDD AVDD AGND AGND

B

SDO1 SDO0 DVDD DVDD DVDD DVDD AVDD AVDD AGND AGND BIN

C

D7 DR DVDD DGND DGND DGND AVDD AVDD AGND AGND AGND

D

D5 D6 DVDD DGND DGND DGND AVDD AVDD AGND AGND LF

E

D3 D4 DVDD DGND DGND DGND AVDD AVDD AGND DNC VLDO

F

D1 D2 DVDD DGND DGND DGND AVDD AVDD AGND AGND CPOUT

G

(RD)

DS

H

(WR) DTACK (RDY)

R/W

J

A2 A1

K

DGND A0 MODE2 MODE0 CHIP_ID0 DNC AVDD VREF REFB AGND AGND

L

1 2 3 4 5 6 7 8 9 10 11

D0 DVDD DGND DGND DGND AVDD AVDD AGND AGND AGND

DVDD DVDD DVDD DVDD AVDD AVDD AGND AGND AIN CS

TRST

MODE1 CHIP_ID1 DNC AVDD REFGND REFT AGND

RESET

9

7

11

10

8

B C

D

E F G

H J

K L

03683-042

DNC AVDD CLK

CLK

AGND AGND

BIN

AIN

A

B

C D E F G H

J

K

L

Table 9. Pin Function Descriptions

Mnemonic Type Description No. of Pins

POWER SUPPLY

DVDD Power 3.3 V Digital Supply. 13 AVDD Power 3.3 V Analog Supply. 19 DGND Ground Digital Ground. 17 AGND Ground Analog Ground. 22

DIGITAL INPUTS

RESET

Input Active Low Reset Pin. 1

SYNC Input Synchronizes Digital Filters. 1 CHIP_ID[1:0] Input Chip ID. 2

SERIAL DATA PORT

SCLK Bidirectional Serial Clock. 1 SDFS Bidirectional Serial Data Frame Sync. 1 SDO[1:0] Output Serial Data Outputs. Three-stated when inactive. 2 DR Output Output Data Ready Indicator. 1

MICROPORTCONTROL

D[7:0] Bidirectional Microport Data. 8 A[2:0] Input Microport Address Bits. 3 CS

DS (RD)

Input Chip Select. 1 Input Active Low Data Strobe (Active Low Read). 1

Rev. A | Page 11 of 44

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Mnemonic Type Description No. of Pins

DTACK (RDY)

R/W (WR) MODE [2:0] Input Selects Control Port Mode. 3

JTAG

TRST TCLK Input Test Clock Input. 1 TMS Input Test Mode Select Input. 1 TDO Output Test Data Output. Three-stated when JTAG is in reset. 1 TDI Input Test Data input. 1

ANALOG INPUTS

AIN Input Main Analog Input. 1 AIN BIN Input Diversity Analog Input. 1 BIN

PLL INPUTS

CPOUT Output Charge-Pump Output. 1 LF Input Loop Filter. 1 VLDO Output

REFT Output

REFB Output

VREF Output

REFGND Ground ADC Ground Reference. See Figure 39 for recommended connection. 1

CLOCK INPUTS

CLK Input Encode Input. Conversion initiated on rising edge. 1 CLK DNC Do Not Connect. 5

Output

Input Read Write (Active Low Write). 1

Input Test Reset Pin. 1

Input Complement of AIN. Differential analog input. 1

Input Complement of BIN. Differential analog input. 1

Input Complement of Encode. 1

Active Low Data Acknowledge (Microport Status Bit). Open-drain output, requires external pull-up resistor of 1 kΩ.

Compensation for Internal Low Dropout Regulator. Bypass to ground with a 220 nF chip ca

Internal ADC Voltage Reference. Bypass to ground with capacitors. See Figure 39

or recommended connection.

f Internal ADC Voltage Reference. Bypass to ground with capacitors. See Figure 39

or recommended connection.

f Internal ADC Voltage Reference. Bypass to ground with capacitors. See Figure 39

or recommended connection.

f

pacitor.

1

Rev. A | Page 12 of 44

AD6650

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TYPICAL PERFORMANCE CHARACTERISTICS

44

42

40

38

IIP2 (dBm)

36

34

32

30

–25°C

70 90 110 130 150 170 190 210 230 250

+25°C

+85°C

IF FREQUENCY ( MHz)

Figure 15. Input IP2 vs. Frequency

6

–7

–8

–9

–10

–11

IIP3 (dBm)

–25°C

–12

–13

–14

–15

70 90 110 130 150 170 190 210 230 250

+25°C

+85°C

IF FREQUENCY ( MHz)

Figure 16. Input IP3 vs. Frequency

44

–45

–46

–47

–48

IMAGE (d Bc)

–49

–50

03683-016

–51

70 90 110 130 150 170 190 210 230 250

IF FREQUENCY ( MHz)

+25°C

–25°C

+85°C

03683-018

Figure 17. Image vs. Frequency

0.2

0

–0.2

–0.4

–0.6

–0.8

GAIN ERROR (dB)

–1.0

–1.2

03683-017

–1.4

70 90 110 130 150 170 190 210 230 250

–25°C

+25°C

+85°C

IF FREQUENCY ( MHz)

03683-019

Figure 18. Gain Error vs. Frequency

Rev. A | Page 13 of 44

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TERMINOLOGY

Analog Bandwidth

The analog input frequency at which the spectral power of the f

undamental frequency (as determined by the FFT analysis) is

reduced by 3 dB.

Noise Figure (NF)

The degradation in SNR performance (in dB) of an IF input sig

nal after it passes through a component or system.

The AD6650 noise figure is determined by the equation

NF

⎛ ⎜

=

⎜ ⎝

2

⎛

rms

⎜

log10

⎜ ⎝

⎞

ZV

in

⎟

−

⎟

001.0

⎠

SNR

⎞ ⎟

−

FS

⎟ ⎠

kTB

⎞

⎛

log10

⎜ ⎝

(1)

⎟

001.0

⎠

where:

−23

k is the B

oltzmann constant = 1.38 × 10

.

T is the temperature in kelvin. B is the channel bandwidth in hertz (200 kHz typical).

2

V

is the full-scale input voltage.

rms

Z

is the input impedance.

in

is the computed signal-to-noise ratio referred to full scale

SNR

FS

with a small input signal and the AD6650 in maximum gain.

Input Second-Order Intercept (IIP2)

A figure of merit used to determine a component’s or system’s su

sceptibility to intermodulation distortion (IMD) from its second-order nonlinearities. Two unmodulated carriers at a specified frequency relationship (f1 and f2) are injected into a nonlinear system exhibiting second-order nonlinearities producing IMD components at f1 − f2 and f2 − f1. IIP2 graphically represents the extrapolated intersection of the carrier’s input power with the second-order IMD component when plotted in decibels.

Input Third-Order Intercept (IIP3)

A figure of merit used to determine a component’s or system’s su

sceptibility to intermodulation distortion (IMD) from its third-order nonlinearities. Two unmodulated carriers at a specified frequency relationship (f1 and f2) are injected into a nonlinear system exhibiting third-order nonlinearities producing IMD components at (2 × f1) – f2 and (2 × f2) – f1. IIP3 graphically represents the extrapolated intersection of the carrier’s input power with the third-order IMD component when plotted in decibels.

Image

The AD6650 incorporates a quadrature demodulator that mixes t

he IF frequency to a baseband frequency. The phase and amplitude imbalance of this quadrature demodulator is observed in a complex FFT as an image of the fundamental frequency. The term image arises from the mirror-like symmetry of signal and image frequencies about the beating-oscillator frequency (in this case, this is dc).

Differential Analog Input Resistance, Differential Analog

Capacitance, and Differential Analog Input Impedance

Input

The real and complex impedances measured at each analog

put port. The resistance is measured statically, and the

in capacitance and differential input impedances are measured with a network analyzer.

Differential Analog Input Voltage Range

The peak-to-peak differential voltage that must be applied to t

he converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180° out of phase. The peak-to-peak differential voltage is computed by rotating the phases of the inputs 180° and taking the peak measurement again. Then the difference is computed between both peak measurements.

Full-Scale Input Power

Expressed in dBm. It is computed using the following equation:

Power

where Z

⎛ ⎜

=

scaleFull

⎜

log10

⎜ ⎜ ⎜

⎝

is the input impedance.

Input

2

V

Z

scaleFull

Input

001.0

⎞

rms

⎟ ⎟

(2)

⎟ ⎟ ⎟

⎠

Noise

The noise, including both thermal and quantization noise, for a

ny range within the ADC is computed as

−−

SignalSNRFS

⎛ ⎜

⎜ ⎝

××=

ZV (3)

noise

10001.0

10

⎞

dBFSdBcdBm

⎟

⎟ ⎠

where:

Z is t

he input impedance. is the full scale of the device for the frequency in question.

FS

dBm

SNR

is the value for the particular input level.

dBc

Signal

is the signal level within the ADC reported in decibels

dBFS

below full scale.

Rev. A | Page 14 of 44

ANALOG DEVICES AD6650 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

PRODUCT DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

EXPLANATION OF TEST LEVELS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

GENERAL TIMING CHARACTERISTICS

MICROPROCESSOR PORT TIMING CHARACTERISTICS

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY