Datasheet AD6645 Datasheet (ANALOG DEVICES)

14-Bit, 80 MSPS/105 MSPS

FEATURES

SNR = 75 dB, fIN 15 MHz, up to 105 MSPS SNR = 72 dB, f SFDR = 89 dBc, f 100 dBFS multitone SFDR IF sampling to 200 MHz Sampling jitter: 0.1 ps

1.5 W power dissipation Differential analog inputs Pin compatible to AD6644 Twos complement digital output format

3.3 V CMOS compatible Data-ready for output latching

APPLICATIONS

Multichannel, multimode receivers Base station infrastructures AMPS, IS-136, CDMA, GSM, W-CDMA Single channel digital receivers Antenna array processing Communications instrumentation Radars, infrared imaging Instrumentation

GENERAL DESCRIPTION

The AD6645 is a high speed, high performance, monolithic 14-bit analog-to-digital converter (ADC). All necessary functions, including track-and-hold (T/H) and reference, are included on the chip to provide a complete conversion solution. The AD6645 provides CMOS-compatible digital outputs. It is the fourth

200 MHz, up to 105 MSPS

IN

70 MHz, up to 105 MSPS

IN

A/D Converter

AD6645

generation in a wideband ADC family, preceded by the AD9042 (12-bit, 41 MSPS), the AD6640 (12-bit, 65 MSPS, IF sampling), and the AD6644 (14-bit, 40 MSPS/65 MSPS).

Designed for multichannel, multimode receivers, the AD6645 is part of the Analog Devices, Inc., SoftCell® transceiver chipset. The AD6645 maintains 100 dB multitone, spurious-free dynamic range (SFDR) through the second Nyquist band. This breakthrough performance eases the burden placed on multimode digital receivers (software radios) that are typically limited by the ADC. Noise performance is exceptional; typical signal-to-noise ratio (SNR) is 74.5 dB through the first Nyquist band.

The AD6645 is built on the Analog Devices extra fast complementary bipolar (XFCB) process and uses an innovative, multipass circuit architecture. Units are available in thermally enhanced 52-lead PowerQuad 4 (LQFP_PQ4) and 52-lead exposed pad (TQFP_EP) packages specified from −40°C to +85°C at 80 MSPS and −10°C to +85°C at 105 MSPS.

PRODUCT HIGHLIGHTS

1. IF Sampling. The AD6645 maintains outstanding ac

performance up to input frequencies of 200 MHz, suitable for multicarrier 3G wideband cellular IF sampling receivers.

2. Pin Compatibility. The ADC has the same footprint and

pin layout as the AD6644 14-bit, 40 MSPS/65 MSPS ADC.

3. SFDR Performance and Oversampling. Multitone SFDR

performance of 100 dBFS can reduce the requirements of high end RF components and allows the use of receive signal processors, such as the AD6620, AD6624/AD6624A, or AD6636.

FUNCTIONAL BLOCK DIAGRAM

DV

AV

AIN

VREF

ENCODE

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

2.4V

INTERNAL

TIMING

GND DMID OVR DRY D13

CC

ADC1

TH2

DAC1

5

D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

MSB

TH1A1

AD6645

TH3A2

DAC2ADC2

5

DIGITAL ERROR CORRECTI ON LOGIC

Figure 1.

ADC3TH5TH4

6

LSB

02647-001

AD6645

REVISION HISTORY

10/08—Rev. C to Rev. D

Added TQFP_EP Package ............................................ Throughout

Renamed Thermal Characteristics Section Thermal Resistance

Section ................................................................................................ 7

Added Table 6; Renumbered Sequentially .................................... 7

Moved Equivalent Circuits Section .............................................. 14

Moved Terminology Section ......................................................... 15

Changes to Table 9 .......................................................................... 20

Updated Outline Dimensions ....................................................... 24

Changes to Ordering Guide .......................................................... 24

12/06—Rev. B to Rev. C

Updated Format .................................................................. Universal

Changes to Specifications ................................................................ 3

Changes to Jitter Considerations Section .................................... 19

Changes to Table 8, Bill of Materials ............................................ 20

Changes to Figure 43, Evaluation Board Schematic .................. 21

Changes to Figure 44 and Figure 46 ............................................. 22

Updated Outline Dimensions ....................................................... 23

Changes to Ordering Guide .......................................................... 23

Explanation of Test Levels ............................................................7

ESD Caution...................................................................................7

Pin Configuration and Function Descriptions ..............................8

Typical Performance Characteristics ..............................................9

Equivalent Circuits ......................................................................... 14

Terminology .................................................................................... 15

Theory of Operation ...................................................................... 17

Applying the AD6645 ................................................................ 17

Layout Information ........................................................................ 19

Jitter Considerations .................................................................. 19

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 24

7/03—Rev. A to Rev. B.

Changes to Title ................................................................................ 1

Changes to Features .......................................................................... 1

Changes to Product Description ..................................................... 1

Changes to Specifications ................................................................. 3

Changes to Absolute Maximum Ratings ........................................ 7

Changes to Ordering Guide .......................................................... 24

Updated Outline Dimensions ....................................................... 20

6/02—Rev. 0 to Rev. A.

Change to DC Specifications ........................................................... 3

Rev. D | Page 2 of 24

AD6645

SPECIFICATIONS

DC SPECIFICATIONS

AVCC = 5 V, DVCC = 3.3 V; T

Table 1.

AD6645ASQ-80/AD6645ASV-80 AD6645ASQ-105/AD6645ASV-105 Parameter Temp Test Level Min Typ Max Min Typ Max Unit

RESOLUTION 14 14 Bits ACCURACY

No Missing Codes Full II Guaranteed Guaranteed Offset Error Full II −10 +1.2 +10 −10 +1.2 +10 mV Gain Error Full II −10 0 +10 −10 0 +10 % FS Differential Nonlinearity (DNL) Full II −1.0 ±0.25 +1.5 −1.0 ±0.5 +1.5 LSB Integral Nonlinearity (INL) Full V ±0.5 ±1.5 LSB

TEMPERATURE DRIFT

Offset Error Full V 1.5 1.5 ppm/°C Gain Error Full V 48 48 ppm/°C

POWER SUPPLY REJECTION RATIO

(PSRR) REFERENCE OUT (VREF) ANALOG INPUTS (AIN, AIN)

Differential Input Voltage Range Full V 2.2 2.2 V p-p

Differential Input Resistance Full V 1 1 kΩ

Differential Input Capacitance 25°C 1.5 1.5 pF POWER SUPPLY

Supply Voltages

AVCC Full II 4.75 5.0 5.25 4.75 5.0 5.25 V DVCC Full II 3.0 3.3 3.6 3.0 3.3 3.6 V

Supply Current

IAVCC (AVCC = 5.0 V) Full II 275 320 275 320 mA IDVCC (DVCC = 3.3 V) Full II 32 45 32 45 mA

Rise Time

2

AVCC Full IV 250 5.0 250 ms

POWER CONSUMPTION Full II 1.5 1.75 1.5 1.75 W

1

VREF is provided for setting the common-mode offset of a differential amplifier, such as the AD8138, when a dc-coupled analog input is required. VREF should be

buffered if used to drive additional circuit functions.

2

Specified for dc supplies with linear rise time characteristics.

MIN

and T

at rated speed grade, unless otherwise noted.

MAX

25°C V ±1.0 ±1.0 mV/V

1

Full V 2.4 2.4 V

Rev. D | Page 3 of 24

AD6645

DIGITAL SPECIFICATIONS

AVCC = 5 V, DVCC = 3.3 V; T

Table 2.

Test AD6645ASQ-80/AD6645ASV-80 AD6645ASQ-105/AD6645ASV-105 Parameter Temp Level Min Typ Max Min Typ Max Unit

ENCODE INPUTS (ENCODE, ENCODE)

Differential Input Voltage Differential Input Resistance 25°C V 10 10 kΩ Differential Input Capacitance 25°C V 2.5 2.5 pF

LOGIC OUTPUTS (D13 to D0, DRY, OVR)

Logic Compatibility CMOS CMOS Logic 1 Voltage (DVCC = 3.3 V) Logic 0 Voltage (DVCC = 3.3 V) Output Coding Twos complement Twos complement DMID Full V DVCC/2 DVCC/2 V

1

All ac specifications tested by driving ENCODE and

2

Digital output logic levels: DVCC = 3.3 V, C

AC SPECIFICATIONS

All ac specifications tested by driving ENCODE and T

at rated speed grade, unless otherwise noted.

MAX

MIN

and T

at rated speed grade, unless otherwise noted.

MAX

1

2

Full II 0.2 0.5 0.2 0.5 V

Full IV 0.4 0.4 V p-p

Full II 2.85 DVCC − 2 2.85 DVCC − 2 V

ENCODE

= 10 pF. Capacitive loads >10 pF degrades performance.

LOAD

differentially.

ENCODE

differentially. AVCC = 5 V, DVCC = 3.3 V; ENCODE,

ENCODE

, T

MIN

and

Table 3.

AD6645ASQ-80/

Test

AD6645ASV-80

AD6645ASQ-105/

AD6645ASV-105

Parameter Temp Level Min Typ Max Min Typ Max Unit Conditions

SNR

Analog Input @ −1 dBFS 25°C V 75.0 75.0 dB At 15.5 MHz Full II 72.5 74.5 dB At 30.5 MHz 25°C I 72.5 74.5 dB At 37.7 MHz Full II 72.0 73.5 72.0 73.5 dB At 70.0 MHz 25°C V 73.0 73.0 dB At 150.0 MHz 25°C V 72.0 72.0 dB At 200.0 MHz SINAD

Analog Input @ −1 dBFS 25°C V 75.0 75.0 dB At 15.5 MHz Full II 72.5 74.5 dB At 30.5 MHz 25°C I 72.5 74.5 dB At 37.7 MHz Full V 73.0 73.0 dB At 70.0 MHz 25°C V 68.5 67.5 dB At 150.0 MHz 25°C V 62.5 62.5 dB At 200.0 MHz WORST HARMONIC (SECOND OR THIRD)

Analog Input @ −1 dBFS 25°C V 93.0 93.1 dBc At 15.5 MHz Full II 85.0 93.0 dBc At 30.5 MHz 25°C I 85.0 93.0 dBc At 37.7 MHz Full V 89.0 87.0 dBc At 70.0 MHz 25°C V 70.0 70.0 dBc At 150.0 MHz 25°C V 63.5 63.5 dBc At 200.0 MHz

Rev. D | Page 4 of 24

AD6645

AD6645ASQ-80/

Test

AD6645ASV-80

Parameter Temp Level Min Typ Max Min Typ Max Unit Conditions

WORST HARMONIC (FOURTH OR HIGHER)

Analog Input @ −1 dBFS 25°C V 96.0 96.0 dBc At 15.5 MHz Full II 85.0 95.0 dBc At 30.5 MHz 25°C I 86.0 95.0 dBc At 37.7 MHz Full V 90.0 90.0 dBc At 70.0 MHz 25°C V 90.0 90.0 dBc At 150.0 MHz 25°C V 88.0 88.0 dBc At 200.0 MHz TWO-TONE SFDR 25°C V 100 98.0 dBFS At 30.5 MHz 25°C V 100 98.0 dBFS At 55.0 MHz 25°C V 98.0 dBFS At 70.0 MHz

2, 3

TWO-TONE IMD REJECTION

F1, F2 @ −7 dBFS 25°C V 90 90 dBc ANALOG INPUT BANDWIDTH 25°C V 270 270 MHz

1

Analog input signal power swept from −10 dBFS to −100 dBFS.

2

F1 = 30.5 MHz, F2 = 31.5 MHz.

3

F1 = 55.25 MHz, F2 = 56.25 MHz.

4

F1 = 69.1 MHz, F2 = 71.1 MHz.

SWITCHING SPECIFICATIONS

AVCC = 5 V, DVCC = 3.3 V; ENCODE,

ENCODE

, T

MIN

and T

at rated speed grade, unless otherwise noted.

MAX

AD6645ASQ-105/

AD6645ASV-105

1, 2

1, 3

1, 4

Table 4.

AD6645ASQ-80/

Test

AD6645ASV-80

AD6645ASQ-105/

AD6645ASV-105

Parameter Symbol Temp Level Min Typ Max Min Typ Max Unit

ENCODE INPUT PARAMETERS

1

Maximum Conversion Rate Full II 80 105 MSPS

Minimum Conversion Rate Full IV 30 30 MSPS

ENCODE Pulse Width High, t

ENCH

2

Full IV 5.625 4.286 ns Full V 6.25 4.75 ns ENCODE Pulse Width Low, t

2

Full IV 5.625 4.286 ns

ENCL

Full V 6.25 4.75 ns ENCODE Period

1

t

Full V 12.5 9.5 ns

ENC

ENCODE/DATA-READY

ENCODE Rising to Data-Ready Falling tDR Full V 1.0 2.0 3.1 1.0 2.0 3.1 ns ENCODE Rising to Data-Ready Rising t

Full V t

E_DR

+ tDR t

ENCH

+ tDR ns

ENCH

50% Duty Cycle Full V 7.3 8.3 9.4 5.7 6.75 7.9 ns

ENCODE/DATA (D13:0), OVR

ENCODE to DATA Falling Low t ENCODE to DATA Rising Low

3

ENCODE to DATA Delay3 (Hold Time) t ENCODE to DATA Delay (Setup Time) t

Full V 2.4 4.7 7.0 2.4 4.7 7.0 ns

E_FL

t

Full V 1.4 3.0 4.7 1.4 3.0 4.7 ns

E_RL

Full V 1.4 3.0 4.7 1.4 3.0 4.7 ns

H_E

Full V

S_E

t

ENC

t

E_FL(max)

−

t

ENC

t

E_FL(typ)

−

t

ENC

t

E_FL(max)

−

t

ENC

t

E_FL(min)

ns

t

ENC

t

E_FL(typ)

−

ns

−

t

ENC

t

E_FL(min)

ns

50% Duty Cycle Full V 5.3 7.6 10.0 2.3 4.8 7.0 ns

Rev. D | Page 5 of 24

AD6645

AD6645ASQ-80/

Test

AD6645ASV-80

Parameter Symbol Temp Level Min Typ Max Min Typ Max Unit

DATA-READY (DRY4)/DATA(D13:0),, OVR

Data-Ready to DATA Delay (Hold Time) t

Full V Note 5

H_DR

5

Note 5

50% Duty Cycle Full V 6.6 7.2 7.9 5.1 5.7 6.4 ns

Data-Ready to DATA Delay (Setup Time) t

Full V Note 5

S_DR

5

Note 5

50% Duty Cycle Full V 2.1 3.6 5.1 0.6 2.1 3.5 ns APERTURE DELAY tA 25°C V −500 −500 ps APERTURE UNCERTAINTY (JITTER) tJ 25°C V 0.1 0.1 ps rms

1

Several timing parameters are a function of t

2

Several timing parameters are a function of t

3

ENCODE TO DATA Delay (Hold Time) is the absolute minimum propagation delay through the ADC, t

4

DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock will correspondingly change the duty cycle of DRY.

5

Data-ready to DATA Delay (t

H_DR

and t

S_DR

and t

ENCH

.

E_RL

ENC

ENCL

) is calculated relative to rated speed grade and is dependent on t

= t

.

H_E

and duty cycle.

ENC

t

A

N

N + 3

AD6645ASQ-105/

AD6645ASV-105

5

AIN

ENCODE, ENCODE

D[13:0], OV R

DRY

t

E_RL

t

ENC

t

E_FL

N + 1

t

ENCHtENCL

N – 2

N + 2

N + 4

N + 4N + 3N + 2N + 1N

t

E_DR

t

S_DR

t

DR

t

H_DR

t

S_E

t

H_E

NN – 1N – 3

2647-002

Figure 2. Timing Diagram

Rev. D | Page 6 of 24

AD6645

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Electrical

AV

Voltage 0 V to 7 V

CC

DV

Voltage 0 V to 7 V

CC

Analog Input Voltage 0 V to AVCC Analog Input Current 25 mA Digital Input Voltage 0 V to AVCC Digital Output Current 4 mA

Environmental

Operating Temperature Range (Ambient)

AD6645-80 −40°C to +85°C

AD6645-105 −10°C to +85°C Maximum Junction Temperature 150°C Lead Temperature (Soldering, 10 sec) 300°C Storage Temperature Range (Ambient) −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Val u es o f θJA are provided for package comparison and PCB design considerations. θ approximation of T

= TA + (θJA × PD)

T

J

can be used for a first-order

JA

by the equation

J

where:

T

is the ambient temperature (°C).

A

PD is the power dissipation (W).

EXPLANATION OF TEST LEVELS

I. 100% production tested.

II. 100% production tested at 25°C and guaranteed by design

and characterization at temperature extremes.

III. Sample tested only.

IV. Parameter is guaranteed by design and characterization

testing.

V. Parameter is a typical value only.

ESD CAUTION

THERMAL RESISTANCE

The heat sink of the AD6645ASVZ, 52-lead TQFP_EP (SV-52-1) package must be soldered to the PCB GND plane to meet thermal specifications.

Table 6. Thermal Characteristics

Package Type Rating

52-Lead TQFP_EP

θJA (0 m/sec airflow) θ

(1.0 m/sec airflow)

JMA

6, 7

θ

2°C/W, soldered heat sink

JC

52-Lead LQFP_PQ4

θJA (0 m/sec airflow) θ

(1.0 m/sec airflow)

JMA

θJA (0 m/sec airflow) θ

(1.0 m/sec airflow)

JMA

6, 7

θ

2°C/W

JC

1

Per JEDEC JESD51-2 (heat sink soldered to PCB).

2

2S2P JEDEC test board.

3

Values of θJA are provided for package comparison and PCB design

considerations.

4

Per JEDEC JESD51-6 (heat sink soldered to PCB).

5

Airflow increases heat dissipation, effectively reducing θJA. Furthermore, the

more metal that is directly in contact with the package leads from metal traces, throughholes, ground, and power planes, the more θ

6

Per MIL-STD-883, Method 1012.1.

7

Values of θJC are provided for package comparison and PCB design

considerations when an external heat sink is required.

1, 2, 3

23°C/W, soldered heat sink

2, 3, 4, 5

17°C/W, soldered heat sink

1, 2, 3

30°C/W, unsoldered heat sink

2, 3, 4, 5

24°C/W, unsoldered heat sink

1, 2, 3

23°C/W, soldered heat sink

2, 3, 4, 5

17°C/W, soldered heat sink

is reduced.

JA

Rev. D | Page 7 of 24

AD6645

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CC

D13 (MSB)52DRY

49

50

51

44D645D746D847D948

D10

D11

D12

D441D542GND43DV

40

1

DV

CC

GND

VREF

GND

ENCODE

GND

AV

CC

AV

CC

GND

AIN

GND

NOTES

1. DNC = DO NOT CONNECT.

2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND.

PIN 1

2

IDENTIFIER

3

4

5

6

7

8

9

10

11

12

13

14

15

CC

GND

AV

16

CC

AV

AD6645

TOP VIEW

(Not to Scale)

17

18

CC

GND

AV

19

20C121

22

23

24C225

GND

CC

GND

AV

39

D3

38

D2

37

D1

36

D0 (LSB)

35

DMID

34

GND

33

DV

CC

32

OVR

31

DNC

30

AV

CC

29

GND

28

AV

CC

27

GND

26

CC

GND

AV

02647-003

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

Pin Number Mnemonic Description

1, 33, 43 DVCC 3.3 V Power Supply (Digital) Output Stage Only. 2, 4, 7, 10, 13, 15, 17, 19, 21, 23, 25,

GND Ground.

27, 29, 34, 42 3 VREF 2.4 V Reference. Bypass to ground with a 0.1 μF microwave chip capacitor. 5 ENCODE Encode Input. Conversion initiated on rising edge. 6

ENCODE

Complement of

ENCODE

, Differential Input. 8, 9, 14, 16, 18, 22, 26, 28, 30 AVCC 5 V Analog Power Supply. 11 AIN Analog Input. 12

AIN

Complement of AIN, Differential Analog Input.

20 C1 Internal Voltage Reference. Bypass to ground with a 0.1 μF chip capacitor. 24 C2 Internal Voltage Reference. Bypass to ground with a 0.1 μF chip capacitor. 31 DNC Do not connect this pin. 32 OVR Overrange Bit. A logic level high indicates analog input exceeds ±FS. 35 DMID Output Data Voltage Midpoint. Approximately equal to (DVCC)/2. 36 D0 (LSB) Digital Output Bit (Least Significant Bit); Twos Complement. 37 to 41, 44 to 50 D1 to D5, D6 to D12 Digital Output Bits in Twos Complement. 51 D13 (MSB) Digital Output Bit (Most Significant Bit); Twos Complement. 52 DRY Data-Ready Output. 53 (EPAD) Exposed Paddle (EPAD) Exposed Pad. Connect the exposed pad to GND.

Rev. D | Page 8 of 24

AD6645

TYPICAL PERFORMANCE CHARACTERISTICS

–10

–20

–30

–40

–50

–60

–70

–80

AMPLITUDE ( dBFS)

–90

–100

–110

–120

–130

0

3

2

5

6

4

50 10152025303540

FREQUENCY (MHz)

ENCODE = 80MSPS AIN = 2.2MHz @ –1d BFS SNR = 75.0dB SFDR = 93.0dBc

Figure 4. Single Tone @ 2.2 MHz

02647-010

–10

–20

–30

–40

–50

–60

–70

–80

AMPLITUDE ( dBFS)

–90

–100

–110

–120

–130

0

6

50 10152025303540

FREQUENCY (MHz)

ENCODE = 80MSPS AIN = 69.1MHz @ –1d BFS SNR = 73.5dB SFDR = 89.0dBc

2

5

Figure 7. Single Tone @ 69.1 MHz

3

4

02647-013

0

–10

–20

–30

–40

–50

–60

–70

–80

AMPLITUDE (dBFS)

–90

5

–100

–110

–120

–130

0

ENCODE = 80MSPS

–10

AIN = 29.5MHz @ –1d BFS SNR = 74.5dB

–20

SFDR = 93.0d Bc

–30

–40

–50

–60

–70

–80

AMPLITUDE (dBFS)

–90

–100

–110

–120

–130

50 10152025303540

ENCODE = 80MSPS AIN = 15.5MHz @ –1d BFS SNR = 75.0dB SFDR = 93.0d Bc

3

6

4

50 10152025303540

FREQUENCY (MHz)

2

Figure 5. Single Tone @ 15.5 MHz

3

5

FREQUENCY (MHz)

2

6

4

02647-012

Figure 6. Single Tone @ 29.5 MHz

0

–10

–20

–30

–40

–50

–60

–70

–80

AMPLITUDE ( dBFS)

–90

–100

–110

–120

–130

2647-011

50 10152025303540

FREQUENCY (MHz)

ENCODE = 80MSPS AIN = 150MHz @ –1dBF S SNR = 73.0dB SFDR = 70.0d Bc

2

3

5

4

6

02647-014

Figure 8. Single Tone @ 150 MHz

0

ENCODE = 80MSPS

–10

AIN = 200MHz @ –1dBFS SNR = 72.0dB

–20

SFDR = 64.0dBc

–30

–40

–50

–60

–70

2

–80

AMPLITUDE (dBFS)

–90

–100

–110

–120

–130

4

50 10152025303540

6

FREQUENCY (MHz)

3

5

02647-015

Figure 9. Single Tone @ 200 MHz

Rev. D | Page 9 of 24

AD6645

75.5

75.0

74.5

74.0

73.5

SNR (dB)

73.0

72.5

72.0 0 10203040506070

T = +85°C

ENCODE = 80MSPS @ AI N = –1dBFS TEMP = –40° C, +25°C, +85°C

FREQUENCY (MHz)

T = –40°C

T = +25°C

Figure 10. Signal-to-Noise Ratio (SNR) vs. Frequency

94

92

90

88

86

84

WORST-CASE HARMONIC (dBc)

82

ENCODE = 80MSPS @ AI N = –1dBFS TEMP = –40° C, +25°C, +85°C

80

0 10203040506070

ANALOG INPUT FREQUENCY (MHz)

T = –40°C, +85°C

Figure 11. Worst-Case Harmonics vs. Analog Input Frequency

T = +25°C

100

95

90

85

80

75

HARMONICS (dBc)

70

65

60

02647-016

(SECOND, THI RD)

ENCODE = 80MSPS @ AIN = –1dBFS TEMP = 25° C

0 20 40 60 80 100 120 140 160 180 20 0

WORST OTHER SPUR

HARMONICS

ANALOG FREQ UENCY (MHz)

02647-019

Figure 13. Harmonics vs. Analog Frequency (IF)

120

110

100

90

ENCODE = 80MSPS AIN = 30.5MHz

80

70

60

50

40

30

20

WORST-CASE SPURIOUS (d BFS AND dBc)

10

0

2647-017

–90 –80 –70 –60 –50 –40 –30 –20 –10 0

ANALOG INPUT POWER L EVEL (dBF S)

dBc

SFDR = 90dB REFERENCE LINE

dBFS

02647-020

Figure 14. Single-Tone SFDR @ 30.5 MHz

76

75

74

73

SNR (dB)

72

71

ENCODE = 80MSPS @ AI N = –1dBFS TEMP = 25° C

70

0 20 40 60 80 100 120 140 160 180 200

ANALOG FREQ UENCY (MHz)

Figure 12. Signal-to-Noise Ratio (SNR) vs. Analog Frequency (IF)

02647-018

Rev. D | Page 10 of 24

120

110

100

90

ENCODE = 80MSPS AIN = 69.1MHz

80

70

60

50

40

30

20

WORST CASE SPURIOUS (d BFS AND dBc)

10

0

–90 –80 –70 –60 –50 –40 –30 –20 –10 0

ANALOG INPUT POWER LEVEL (dBFS)

dBc

dBFS

SFDR = 90dB REFERENCE LINE

Figure 15. Single-Tone SFDR @ 69.1 MHz

2647-021

AD6645

0

ENCODE = 80MSPS

–10

AIN = 30.5MHz,

31.5MHz (–7d BFS)

–20

NO DITHER

–30

–40

–50

–60

–70

–80

AMPLITUDE (dBFS)

–90

–100

–110

–120

–130

F2 – F1

50 10152025303540

2F2 + F1

2F1 + F2

FREQUENCY (MHz)

F1 + F2

Figure 16. Two-Tone SFDR @ 30.5 MHz and 31.5 MHz

2F1 – F2

2F2 – F1

02647-022

0

ENCODE = 80MSPS

–10

AIN = 55.25MHz,

56.25MHz (–7dBFS)

–20

NO DIT HER

–30

–40

–50

–60

–70

–80

AMPLITUDE (dBFS)

–90

–100

–110

–120

–130

F2 – F1

2F2 + F1

2F1 + F2

50 10152025303540

FREQUENCY (MHz )

2F2 – F1

2F1 – F2

Figure 19. Two-Tone SFDR @ 55.25 MHz and 56.25 MHz

F1 + F2

02647-025

110

100

90

ENCODE = 80MSPS F1 = 30.5MHz

80

F2 = 31.5MHz

70

60

50

40

30

20

10

WORST-CAS E SPURIOUS ( dBFS AND dBc)

0

–77 –67 –57 –47 –37 –27 –17 –7

INPUT POWER LEVEL (F1 = F2 dBFS)

dBc

dBFS

SFDR = 90dB REFERENCE LINE

Figure 17. Two-Tone SFDR @ 30.5 MHz and 31.5 MHz

100

95

90

85

80

75

70

SNR, WORST -CASE SPURIO US (dB AND dBc)

65

15 30 45 60 75 90 105

WORST SPUR @ AI N = 2.2MHz

SNR @ AIN = 2.2MHz

ENCODE FREQUENCY (MHz)

Figure 18. SNR, Worst-Case Spurious vs. Encode @ 2.2 MHz

110

100

90

80

ENCODE = 80MSPS F1 = 55.25MHz F2 = 56.25MHz

70

60

50

40

30

20

10

WORST-CASE SPURIOUS ( dBFS AND dBc)

0

–77 –67 –57 –47 –37 –27 –17 –7

02647-023

INPUT POWER LEVEL (F1 = F2 dBFS)

dBc

dBFS

SFDR = 90dB REFERENCE LI NE

2647-026

Figure 20. Two-Tone SFDR @ 55.25 MHz and 56.25 MHz

95

90

85

80

75

70

SNR, WORST -CASE SPURIO US (dB AND dBc)

65

15 30 45 60 75 90 105

02647-024

WORST SP UR @ AIN = 69.1MHz

SNR @ AIN = 69.1MHz

ENCODE FREQUE NCY (MHz)

02647-027

Figure 21. SNR, Worst-Case Spurious vs. Encode @ 69.1 MHz

Rev. D | Page 11 of 24

AD6645

0

ENCODE = 80.0MSPS

–10

AIN = 30.5MHz @ –29.5dBFS NO DITHER

–20

–30

–40

–50

–60

–70

AMPLITUDE (dBFS)

–100

–110

–120

–130

–80

–90

3

5

50 10152025303540

2

6

FREQUENCY (MHz)

Figure 22. 1 M Sample FFT Without Dither

110

ENCODE = 80.0M SPS AIN = 30.5MHz

100

NO DITHER

90

80

70

60

50

40

30

WORST-CASE SPURIOUS (d Bc)

20

10

0

90 80 70 60 50 40 30 20 10 0

ANALOG INPUT LEVEL (dBFS)

SFDR = 90dB REFERENCE LINE

Figure 23. SFDR Without Dither

4

02647-028

02647-029

0

ENCODE = 80.0MSPS

–10

AIN = 30.5MHz @ –29. 5dBFS WITH DI THER @ –19.2 dBm

–20

–30

–40

–50

–60

–70

–80

AMPLITUDE ( dBFS)

–90

–100

–110

–120

–130

3

5

50 10152025303540

2

6

FREQUENCY (MHz )

Figure 25. 1 M Sample FFT with Dither

110

ENCODE = 80.0MSPS AIN = 30.5MHz

100

WITH DIT HER @ –19.2dBm

90

80

70

SFDR = 100dB

60

REFERENCE LINE

50

40

30

WORST-CASE SPURIOUS (dBc)

20

10

0 –90 –80 –70 –60 –50 –40 –30 –20 –10 0

ANALOG INPUT LEVEL ( dBFS)

SFDR = 90dB REFERENCE LI NE

Figure 26. SFDR with Dither

4

02647-031

02647-032

AMPLITUDE ( dBFS)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

0

2

50 10152025303540

FREQUENCY (MHz )

ENCODE = 76.8MSPS AIN = 69.1MHz @ –1d BFS SNR = 73.5dB SFDR = 89.0dBc

3

Figure 24. Single Tone @ 69.1 MHz, Encode = 76.8 MSPS

5

6

4

02647-030

0

–10

–20

–30

–40

–50

–60

–70

–80

AMPLITUDE ( dBFS)

–90

–100

–110

–120

–130

0 5 10 15 20 25 30 35 40

2 6 543

FREQUENCY (MHz)

ENCODE = 76. 8MSPS AIN = W-CDMA @ 69.1MHz

Figure 27. W-CDMA Tone @ 69.1 MHz, Encode = 76.8 MSPS

02647-033

Rev. D | Page 12 of 24

AD6645

AMPLITUDE (dBFS)

–100

–110

–120

–130

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

50 10152025303540

FREQUENCY (MHz )

ENCODE = 76.8MSPS AIN = 2W-CDMA @ 59.6MHz

Figure 28. Two W-CDMA Carriers @ 59.6 MHz, Encode = 76.8 MSPS

02647-034

AMPLITUDE ( dBFS)

–100

–110

–120

–130

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

54

6

50 10152025303540

FREQUENCY (MHz )

ENCODE = 76.8MSPS AIN = W-CDMA @ 140MHz

2 3

Figure 30. W-CDMA Tone @ 140 MHz, Encode = 76.8 MSPS

2647-036

0

–10

–20

–30

–40

–50

–60

–70

–80

AMPLITUDE ( dBFS)

–90

–100

–110

–120

–130

0 2.5 5.0 7. 5 10.0 12. 5 15.0 17. 5 20. 0 22.5 25. 0 27.5 30.0

FREQUENCY (MHz )

ENCODE = 61.44MS PS AIN = 4W-CDMA @ 46.08MHz

Figure 29. Four W-CDMA Carriers @ 46.08 MHz, Encode = 61.44 MSPS

0

–10

–20

–30

–40

–50

–60

–70

–80

AMPLITUDE ( dBFS)

–90

–100

–110

–120

–130

0 2.5 5.0 7.5 10.0 12.5 15.0 17. 5 20.0 22.5 25.0 27.5 30.0

02647-035

FREQUENCY (MHz )

ENCODE = 61.44MS PS AIN = W-CDMA @ 190MHz

23645

02647-037

Figure 31. W-CDMA Tone @ 190 MHz, Encode = 61.44 MSPS

Rev. D | Page 13 of 24

AD6645

V

EQUIVALENT CIRCUITS

AV

CC

CH

DV

CC

AIN

AV

V

CL

VCHAV

V

CL

500Ω

CC

500Ω

Figure 32. Analog Input Stage

AV

CC

10kΩ

Figure 33. Encode Inputs

AV

CC

BUF T/H

BUF

BUF T/H

LOADS

CURRENT

MIRROR

VREF

DV

CC

02647-004

AV

CC

AV

CC

10kΩ

ENCODEENCODE

10kΩ

CURRENT

MIRROR

V

REF

D0 TO D13, OVR, DRY

02647-007

Figure 35. Digital Output Stage

AV

CC

AV

02647-005

2.4V

100µA

CC

VREF

02647-008

REF

AV

CC

CURRENT

MIRROR

C1, C2

Figure 34. Compensation Pin, C1 or C2

AV

CC

2647-006

Figure 36. 2.4 V Reference

DV

10kΩ

CC

DMID

Figure 37. DMID Reference

02647-009

Rev. D | Page 14 of 24

AD6645

TERMINOLOGY

Analog Bandwidth

The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.

Aperture Delay

The delay between the 50% point of the rising edge of the encode command and the instant at which the analog input is sampled.

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance

The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer.

Differential Analog Input Voltage Range

The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. The peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180° out of phase. The peak-to-peak differential is computed by rotating the inputs’ phase 180°and taking the peak measurement again. The difference is then computed between both peak measurements.

Differential Nonlinearity

The deviation of any code width from an ideal 1 LSB step.

Encode Pulse Width/Duty Cycle

Pulse width high is the minimum amount of time that the encode pulse should be left in a high state to achieve rated performance; pulse width low is the minimum time that the encode pulse should be left in a low state. See timing implications of changing t these specifications define an acceptable encode duty cycle.

Full-Scale Input Power

The full-scale input power is expressed in dBm and can be calculated by using the following equation:

Power

−

ScaleFull

in Tabl e 4. At a given clock rate,

ENCH

2

⎡

V

−

⎢ ⎢

Z

⎢

=

log10

⎢ ⎢ ⎢

⎣

rmsScaleFull

Input

001.0

⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥

⎦

Harmonic Distortion, Second

The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc.

Harmonic Distortion, Third

The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc.

Integral Nonlinearity

The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least square curve fit.

Maximum Conversion Rate

The encode rate at which parametric testing is performed.

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.

Noise (for Any Range Within the ADC)

SignalSNRFS

⎛

NOISE

where:

Z is the input impedance.

FS is the full scale of the device for the frequency in question.

SNR is the value for the particular input level.

Signal is the signal level within the ADC reported in dB below

full scale. This value includes both thermal noise and quantization noise.

Output Propagation Delay

The delay between a differential crossing of ENCODE and ENCODE valid logic levels.

Power Supply Rejection Ratio (PSSR)

The ratio of a change in input offset voltage to a change in power supply voltage.

Power Supply Rise Time

The time from when the dc supply is initiated until the supply output reaches the minimum specified operating voltage for the ADC. The dc level is measured at the supply pin(s) of the ADC.

Signal-to-Noise-and-Distortion (SINAD)

The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc.

Signal-to-Noise Ratio (Without Harmonics)

The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.

ZV

and the time when all output data bits are within

10001.0

××=

⎜ ⎝

−−

10

⎞

dBFSdBcdBm

⎟ ⎠

Rev. D | Page 15 of 24

AD6645

Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (that is, degrades as signal level is lowered) or dBFS (always related back to converter full scale).

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product, reported in dBc.

Two -Tone SFDR

The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product, and may be reported in dBc (that is, degrades as signal level is lowered) or in dBFS (always related back to converter full scale).

Worst Other Spur

The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonics), reported in dBc.

Rev. D | Page 16 of 24

AD6645

V

THEORY OF OPERATION

The AD6645 ADC employs a three-stage subrange architecture. This design approach achieves the required accuracy and speed while maintaining low power and small die size.

As shown in the functional block diagram (see Figure 1), the AD6645 has complementary analog input pins, AIN and Each analog input is centered at 2.4 V and should swing ±0.55 V around this reference (see ). Because AIN and Figure 32 180° out of phase, the differential analog input signal is 2.2 V p-p.

Both analog inputs are buffered prior to the first track-and-hold, TH1. The high state of the encode pulse places TH1 in hold mode. The held value of TH1 is applied to the input of a 5-bit coarse ADC1. The digital output of ADC1 drives a 5-bit digitalto-analog converter, DAC1. DAC1 requires 14 bits of precision that is achieved through laser trimming. The output of DAC1 is subtracted from the delayed analog signal at the input of TH3 to generate a first residue signal. TH2 provides an analog pipeline delay to compensate for the digital delay of ADC1.

The first residual signal is applied to a second conversion stage consisting of a 5-bit ADC2, a 5-bit DAC2, and a pipeline TH4. The second DAC requires 10 bits of precision, which is met by the process with no trim. The input to TH5 is a second residual signal generated by subtracting the quantized output of DAC2 from the first residual signal held by TH4. TH5 drives a final 6-bit ADC3.

The digital outputs from ADC1, ADC2, and ADC3 are added together and corrected in the digital error correction logic to generate the final output data. The result is a 14-bit parallel digital CMOS-compatible word, coded as twos complement.

APPLYING THE AD6645

Encoding the AD6645

The AD6645 encode signal must be a high quality, extremely low phase noise source to prevent degradation of performance. Maintaining 14-bit accuracy places a premium on encode clock phase noise. SNR performance can easily degrade by 3 dB to 4 dB with 70 MHz analog input signals when using a high jitter clock source. See the AN-501 application note, Aperture Uncertainty and ADC System Performance, for complete details.

For optimum performance, the AD6645 must be clocked differentially. The encode signal is usually ac-coupled into the ENCODE and These pins are biased internally and require no additional bias.

Figure 38 shows one preferred method for clocking the AD6645. The clock source (low jitter) is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the transformer secondary limit excessive amplitude swings from the clock into the AD6645 to approximately 0.8 V p-p differential. This helps to prevent the large voltage swings of the clock from feeding through to other portions of the AD6645 and limits the noise presented to the encode inputs.

ENCODE

pins via a transformer or capacitors.

AIN

.

are

0.1µF

T1-4T

HSMS2812

DIODES

ENCODE

AD6645

ENCODE

02647-038

CLOCK

SOURCE

Figure 38. Crystal Clock Oscillator, Differential Encode

If a low jitter clock is available, another option is to ac-couple a differential ECL/PECL signal to the encode input pins, as shown in Figure 39. The MC100EL16 (or same family) from ON Semiconductor offers excellent jitter performance.

T

0.1µF

ENCODE

AD6645

ENCODE

02647-039

ECL/

PECL

VT

Figure 39. Differential ECL for Encode

Driving the Analog Inputs

As with most new high speed, high dynamic range ADCs, the analog input to the AD6645 is differential. Differential inputs improve on-chip performance as signals are processed through attenuation and gain stages. Most of the improvement is a result of differential analog stages having high rejection of even-order harmonics. There are also benefits at the PCB level. First, differential inputs have high common-mode rejection of stray signals, such as ground and power noise. Second, they provide good rejection of common-mode signals, such as local oscillator feedthrough.

The AD6645 analog input voltage range is offset from ground by 2.4 V. Each analog input connects through a 500 Ω resistor to the 2.4 V bias voltage and to the input of a differential buffer (see Figure 32). The resistor network on the input properly biases the followers for maximum linearity and range. Therefore, the analog source driving the AD6645 should be ac-coupled to the input pins. Because the differential input impedance of the AD6645 is 1 kΩ, the analog input power requirement is only −2 dBm, simplifying the driver amplifier in many cases. To take full advantage of this high input impedance, a 20:1 RF transformer is required. This is a large ratio and can result in unsatisfactory performance. In this case, a lower step-up ratio can be used. The recommended method for driving the differential analog input of the AD6645 is to use a 4:1 RF transformer. For example, if R

is set to 60.4 Ω and RS is set

T

to 25 Ω, along with a 4:1 impedance ratio transformer, the input would match to a 50 Ω source with a full-scale drive of 4.8 dBm. Series resistors (R

) on the secondary side of the transformer

S

should be used to isolate the transformer from the A/D.

Rev. D | Page 17 of 24

AD6645

ANA

V

This limits the amount of dynamic current from the A/D flowing back into the secondary of the transformer. The 50 Ω impedance matching can also be incorporated on the secondary side of the transformer, as shown in the evaluation board schematic (see Figure 43).

R

0.1µF

S

AIN

S

AD6645

AIN

02647-040

R

ADT4-1WT

T

LOG INPUT

SIGNAL

Figure 40. Transformer-Coupled Analog Input Circuit

In applications where dc coupling is required, a differential output op amp, such as the AD8138, can be used to drive the AD6645 (see Figure 41). The AD8138 op amp provides singleended-to-differential conversion, which reduces overall system cost and minimizes layout requirements.

C

F

5V

499Ω

IN

499Ω

V

OCM

AD8138

499Ω

C

F

Figure 41. DC-Coupled Analog Input Circuit

25Ω

AIN

AD6645

AIN

VREF

DIGIT AL OUTPUTS

Power Supplies

Care should be taken when selecting a power source. The use of linear dc supplies with rise times of <45 ms is highly recommended. Switching supplies tend to have radiated components that can be received by the AD6645. Decouple each of the power supply pins as close to the package as possible using 0.1 μF chip capacitors.

The AD6645 has separate digital and analog power supply pins. The analog supplies are AV DV

. Although analog and digital supplies can be tied together,

CC

and the digital supply pins are

CC

the best performance is achieved when the supplies are separate because the fast digital output swings can couple switching currents back into the analog supplies. Note that AV held within 5% of 5 V. The AD6645 is specified for DV

must be

CC

= 3.3 V, a

CC

common supply for digital ASICs.

Digital Outputs

Care must be taken when designing the data receivers for the AD6645. It is recommended that the digital outputs drive a series resistor followed by a gate, such as the 74LCX574.

02647-041

To minimize capacitive loading, there should be only one gate on each output pin. An example of this is shown in the evaluation board schematic of Figure 43. The digital outputs of the AD6645 have a constant output slew rate of 1 V/ns. A typical CMOS gate combined with a PCB trace have a load of approximately 10 pF. Therefore, as each bit switches, 10 mA (10 pF × 1 V ÷ 1 ns) of dynamic current per bit flow in or out of the device. A full-scale transition can cause up to 140 mA (14 bits × 10 mA/bit) of current to flow through the output stages. Place the series resistors as close to the AD6645 as possible to limit the amount of current that can flow into the output stage. These switching currents are confined between ground and DV

. Standard TTL gates should be avoided

CC

because they can add appreciably to the dynamic switching currents of the AD6645. Note that extra capacitive loading increases output timing and invalidates timing specifications. Digital output timing is guaranteed for output loads up to 10 pF. Digital output states for given analog input levels are shown in Tab l e 8.

Grounding

For optimum performance, it is highly recommended that a common ground be used between the analog and digital power planes. The primary concern with splitting grounds is that dynamic currents may be forced to travel significant distances in the system before recombining back at the common source ground. This can result in a large, undesirable ground loop. The most common place for this to occur is on the digital outputs of the ADC. Ground loops can contribute to digital noise being coupled back onto the ADC front end. This can manifest itself as either harmonic spurs, or very high-order spurious products that can cause excessive spikes on the noise floor. This noise coupling is less likely to occur at lower clock speeds because the digital noise has more time to settle between samples. In general, splitting the analog and digital grounds can frequently contribute to undesirable EMI-RFI and should, therefore, be avoided.

Conversely, if not properly implemented, common grounding can actually impose additional noise issues because the digital ground currents ride on top of the analog ground currents in close proximity to the ADC input. To further minimize the potential for noise coupling, it is highly recommended that multiple ground return traces/vias be placed such that the digital output currents do not flow back toward the analog front end but are routed quickly away from the ADC. This does not require a split in the ground plane and can be accomplished by simply placing substantial ground connections directly back to the supply at a point between the analog front end and the digital outputs. In addition, the judicious use of ceramic chip capacitors between the power supply and ground planes helps to suppress digital noise. The layout should incorporate enough bulk capacitance to supply the peak current requirements during switching periods.

Rev. D | Page 18 of 24

AD6645

−

=

LAYOUT INFORMATION

The schematic of the evaluation board (see Figure 43) represents a typical implementation of the AD6645. A multilayer board is recommended to achieve best results. It is highly recommended that high quality, ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. The pinout of the AD6645 facilitates ease of use in the implementation of high frequency, high resolution design practices. All of the digital outputs are segregated to two sides of the chip, with the inputs on the opposite side for isolation purposes.

Care should be taken when routing the digital output traces. To prevent coupling through the digital outputs into the analog portion of the AD6645, minimal capacitive loading should be placed on these outputs. It is recommended that a fanout of only one gate should be used for all AD6645 digital outputs.

The layout of the encode circuit is equally critical. Any noise received on this circuitry results in corruption in the digitization process and lower overall performance. The encode clock must be isolated from the digital outputs and the analog inputs.

Table 8. Twos Complement Output Coding

AIN Level

AIN

Level

VREF + 0.55 V VREF − 0.55 V Positive FS VREF VREF Midscale VREF − 0.55 V VREF + 0.55 V Negative FS

Output State Output Code

01 1111 1111 1111 00 … 0/11 … 1 10 0000 0000 0000

JITTER CONSIDERATIONS

The SNR for an ADC can be predicted. When normalized to ADC codes, the following equation accurately predicts the SNR based on three terms: jitter, average DNL error, and thermal noise. Each of these terms contributes to the noise within the converter.

SNR

where:

f

t

and internal encode circuitry).

ε is the average DNL of the ADC (typically 0.41 LSB).

n is the number of bits in the ADC.

V

analog input of the ADC (typically 0.9 LSB rms).

For a 14-bit ADC, such as the AD6645, aperture jitter can greatly affect the SNR performance as the analog frequency is increased. Figure 42 shows a family of curves that demonstrate the expected SNR performance of the AD6645 as jitter increases. The chart is derived from the preceding equation.

For a complete discussion of aperture jitter, see the AN-756 application note, Sampled Systems and the Effects of Clock Phase Noise and Jitter. The AN-756 application note can be found on www.analog.com.

76.1

2

⎡

()

2log20

⎢

ANALOG

⎣

is the analog input frequency.

ANALOG

is the rms jitter of the encode (rms sum of encode source

j rms

is the voltage rms thermal noise that refers to the

NOISE rms

80

tf

⎛

2

+××π

⎜

rmsj

⎝

⎛

+

ε1

⎞

⎜

+

⎟

n

⎜

2

⎠

⎝

V

22

××

n

2

⎤

⎞

rmsNOISE

⎟

⎥

⎟

⎥

⎠

⎦

2/1

75

70

AIN = 110MHz

65

SNR (dBFS)

60

55

AIN = 150MHz

AIN = 190MHz

0 0.1 0.2 0.3 0.4 0.5 0.6

JITTER (ps)

Figure 42. SNR vs. Jitter

AIN = 30MHz

AIN = 70MHz

02647-042

Rev. D | Page 19 of 24

AD6645

Table 9. AD6645/PCB Bill of Materials

Quantity 80 MSPS

1 1 PCB

4 4 C1, C2, C31, C38

8 8

9 9

0 0 (C5, C6)

10 10

0 0 (C27, C28)

1 1 CR1

1 1 E1

5 5 F1 to F5 EMI suppression ferrite chip, SMT 0805 Steward HZ0805E601R-00 1 1 J1 Header, 6-pin, pin strip, 5 mm pitch Wieland Z5.530.0625.0 1 1 J1 Pin strip, 6-pin, 5 mm pitch Wieland 25.602.2653.0 1 1 J2 Header, 40-pin, male, right angle Samtec TSW-120-08-T-D-RA 2 2 (J3)2, J4, J5

1 1 L1 Inductor, SMT, 1008-ct package, 4.7 nH Coilcraft 1008CT-040X-J 0 0 (R1)

0 0 (R2)

2 2

2 2 R6, R7

0 0 (R11)

0 0 (R12)

1 1 R15

1 1 R35

4 4 RN1 to RN4

2 2 T23, T3

1 0 U1 IC, 14-bit, 80 MSPS ADC Analog Devices AD6645ASQ/ASV-80 0 1 U1 IC, 14-bit, 105 MSPS ADC Analog Devices AD6645ASQ/ASV-105 2 2 U2, U7 IC, SOIC-20, Octal D-type flip-flop Fairchild 74LCX574WM 0 0 (U3)

2 2 U4, U6

Quantity 105 MSPS Reference ID Description Manufacturer Supplier Part No.

Printed circuit board, AD6645

PCSM 6645EE01D REV D

engineering evaluation board Capacitor, tantalum, SMT

Kemet T491C106K016AS

BCAPTAJC, 10 μF, 16 V, 10%

C3, C7 to C10, C16, C301, C32

C4, C15, C22 to C26, C29, (C33)

2, 3

(C34)

, C39

2, 3

,

Capacitor, ceramic, SMT 0508,

0.1 μF, 16 V, 10% Capacitor, ceramic, SMT 0805,

0.1 μF, 25 V, 10%

Capacitor, ceramic, SMT 0805,

Presidio Components 0508X7R104K16VP3

Panasonic ECJ-2VB1E104K

Panasonic ECJ-2YB1H103K

0.01 μF, 50 V, 10%

C11 to C14, C17 to C21, C40

2

Capacitor, ceramic, SMT 0508,

0.01 μF, 50 V, 0.2% Capacitor, ceramic, SMT 0805, limits

Presidio Components 0508X7R103M2P3

amp bandwidth as warranted

3

Diode, dual Schottky HSMS2812,

Panasonic MA716-(TX)

SOT-23, 30 V, 20 mA Install jumper wire (across OPT_LAT

and BUFLAT)

Connector, gold, female, coax., SMA,

Johnson Components 142-0701-201

vertical

2, 3

Resistor, thick film, SMT 0402, 100 Ω,

Panasonic ERJ-2RKF1000

1/16 W, 1%

2

Resistor, thick film, SMT 1206, 60.4 Ω,

Panasonic ERJ-8ENF60R4V

1/4 W, 1%

(R3 to R5) R9, R10

, (R8)

1, 2

,

Resistor, thick film, SMT 0805, 500 Ω, 1/8 W, 1%

Resistor, thick film, SMT 0805, 25.5 Ω,

Panasonic ERJ-6ENF4990V

Panasonic ERJ-6ENF25R5V

1, 2

1/8 W, 1%

2, 3

, (R13)

2, 3

Resistor, thick film, SMT 0805, 66.5 Ω,

Panasonic ERJ-6ENF66R5V

1/8 W, 1%

2, 3

, (R14)

2, 3

Resistor, thick film, SMT 0805, 100 Ω,

Panasonic ERJ-6ENF1000V

1/8W, 1%

1

Resistor, thick film, SMT 0402, 178 Ω,

Panasonic ERJ-2RKF1780X

1/16 W, 1% Resistor, thick film, SMT 0805, 49.9 Ω,

Panasonic ERJ-6ENF49R9V

1/8 W, 1% Resistor array, SMT 0402; 100 Ω;

Panasonic EXB2HV101JV

8 ISO RES.,1/4 W; 5%

1

Transformer, ADT4-1WT, CD542,

Mini-Circuits ADT4-1WT

2 MHz to 775 MHz

1, 2

IC, SOIC-8, low distortion differential

Analog Devices AD8138AR

ADC driver IC, SOT-23, tiny logic UHS 2 input

Fairchild NC7SZ32

OR gate

Rev. D | Page 20 of 24

AD6645

Quantity 80 MSPS

0 0 (U8) 1 0 Y1 Clock oscillator, 80 MHz CTS Reeves MXO45-80 4 4 Y1 Pin sockets, closed end AMP/Tyco Electronics 5-330808-3 4 4 Circuit board support Richco, Inc. CBSB-14-01

1

AC-coupled AIN is standard: R3, R4, R5, R8, and U3 are not installed. If dc-coupled AIN is required, C30, R15, and T3 are not installed.

2

Reference designators in parentheses are not installed on standard units.

3

AC-coupled encode is standard: C5, C6, C33, C34, R1, R11 to R14, and U8 are not installed. If PECL encode is required, CR1 and T2 are not installed.

Quantity 105 MSPS Reference ID Description Manufacturer Supplier Part No.

2, 3

IC, SOIC-8, differential receiver Motorola MC100LVEL16

Rev. D | Page 21 of 24

AD6645

D

C26

0.1U

+3P3VD

C25

OPT_LA T

4

DMID

ENC

U4

PREF

2

F4

12

GND

ENC

E1

BUFLAT

3

GND

NC7SZ32

R9

0.1U0.1U

C24

0.1U

C23

+3P3V

DNC

OVR

DVCC

AD6644/AD6645

GND

AVCC

+5VA

DR_OUT

DC-COUPLED AIN OPTION

500

2

4

10

11 12

13 14

15 16

9

B01

B02

B03

B04

RN4

1

+3P3VD

021

19

VCC

U2

74LCX574

OE

RN3

1

C32

VREF

+5VA

F3

12

0.1U

C29

14

VCC

OE

Y1

1

3

56

78

B00

141516

111213

23456789

O0O1O2O3O4O5O6

D0D1D2D3D4D6D7

23456789

C22

12

VCC'

OE'

3

7

65432

40414244

GN D

+3P3V

43U1

45464748495052

51

DR_OU T

0.1U

+3P3V

+3P3V_XTL

F5

12

0.1U

C15

0.1U

10

OUT'

GND'

GN D OUT

80MHz (AD6645)

66.66MHz (AD 6644)

78

5

21 22

23 24

25 26

27 28

B07

B08

B09

10111213141516

D5

7

8

65432

10111213141516

ENC

CR1

3

5

4

T2

3

C 4 0.1U

20

17 18

19

B05

B06

100

BUFLAT

12131415161718

11

O7

CP

GND

9

10

100

ENC

21

4:1

ADT4-1WT

IMPEDANCE RATIO

16

40

J2

37 38

39

HEADER40

4

NC7SZ32

5

U6

3

+V

+3P3V

GND

2

1

BUFLAT

+3P3VD

U7

R13

66.5

+5VA

DO NOT INSTA LL

+5VA

R11

DC-COUPLED ENCODE OPTION (SE E NOTE 3)

+5VA

C6

66.5

8

VCC

U8

0.01U

R1

100

30

29

31 32

33 34

35 36

B10

B11

B12

B13

RN2

1

23456789

021

19

O0O1O2O3O4O5O6

VCC

OE

D0D1D2D3D4D6D7

RN1

1

23456789

R14

100

C34

0.1U

C33

0.1U

100

R12

567

Q

VEE

OPTIONAL

MC100LVEL16

DDNC

VBB

321

4

C5

0.01U

E6

OVR

E2

10

100

BUFLAT

12131415161718

11

O7

CP

D5

39383736353433323130292827

D4

D5

D6

D7

D8

D9

74LCX574

GND

9

8

10

10111213141516

100

D0

D1

D2

D3

GN D

DVCC

D10

D11

D12

D13

DRY

VREF

DVCC

GND

1

23456789101112

INSTALL JUMPER

5

+V

+3P3VD

1

500

R10

+3P3V

C3

0.1U

0.01U

C14

0.01U

C13

0.01U

C12

0.01U

C11

0.1U

C10

0.1U

C9

+3P3V

C1

10U

F2

+3P3VIN

+5VA

GND

AVCC

AIN

GND

13

0.0

R4

500

C27

(SEE NOTE 2)

DO NOT INSTA LL

+5VA+5V

C16

F1

12345

J1

AVC C

2625

GN D

C2

24

GN D

232221

AVC C

GN D

C1

20

GN D

191817161514

AVC C

GN D

AVC C

GN D

AVC C

AIN

R7

25.5

VAL

VREF-5V

2

VOCM

V−

6

1

R8 500

U10.0U10.0

C21C20

0.01U0.01U

C19

C18

C38

C17

0.01U

0.1U

10U

C2

+3P3VIN

-5V

+5V A

C7

0.1U

+5V A

C8

0.1U

+5V A

AIN

R6

5

4

U3

7

NC

V+

AD8138ARM

8

10U

0.1U

C4 0 C39

0.01U

+3P3V_XTL

10U

C31

6

R15 IS INSTALLED FOR INPUT MATCHING ON THE SECONDARY OF T3, R2 IS NOT INSTALLED.

NOTES:

1. R2 IS INSTALLED FOR INPUT MATCHING ON THE PRIMARY OF T3. R1 5 IS NOT INSTALLED.

R15

178

(SEE NOTE 1)

25.5

0.0

5

R 5 500

3

C28

+5VA

500R3

4

T3

3

16

L1

4.7NH

02647-043

IF DC-COUPLED AIN IS REQUIRED, C30, R15 AND T3 ARE NOT INSTALLED.

IF PECL ENCODE IS REQUIRED, CR1 AND T2 ARE NOT INSTALLED.

2. AC-COUPLED AIN IS STANDARD, R3, R4, R5, R8 AND U3 ARE NOT INSTALLED.

3. AC-COUPLED ENCODE IS STANDARD. C5, C6, C33, C34, R1, R11−R14 AND U8 ARE NOT INSTALLED.

0.1U

C30

4:1

ADT4-1WT

IMPEDANCE RATIO

49.9

R35

ENC

J4

OPT_CLK

DO NOT INSTA LL

J3

60.4

R2

(SEE NOTE 1)

DO NOT INSTA LL

AIN

Figure 43. Evaluation Board Schematic

Rev. D | Page 22 of 24

AD6645

Figure 44. Top Signal Level

Figure 45. 5.0 V Plane Layer 3 and 3.3 V Plane Layer 4

02647-044

Figure 46. Ground Plane Layer 2 and Ground Plane Layer 5

02647-045

Figure 47. Bottom Signal Layer

02647-046

2647-047

Rev. D | Page 23 of 24

AD6645

OUTLINE DIMENSIONS

2.35

2.20 (4 PLCS)

2.05

EXPOSED

HEAT SINK

(CENTERED)

BOTTOM VIEW

(PINS UP)

EXPOSED

PAD

BOTTOM VIEW

(PINS UP)

0.65

BSC

1

6.05

5.90 SQ

5.75

10.20

10.00 SQ

9.80

13

14

FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONF IGURATIO N AND FUNCTION DES CRIPTIONS SECTION O F THIS DAT A SHEET.

52

1

6.50 BSC SQ

13

14

0.38

0.32 FOR PROPER CONNECTION O F

0.22

THE EXPOSED PAD, REFER TO THE PIN CONF IGURATIO N AND FUNCTION DES CRIPTIONS SECTION O F THIS DAT A SHEET.

082108-A

072408-A

1.45

1.40

1.35

ROTATED 90° CCW

1.05

1.00

0.95

0.15

0.05

VIEW A

ROTATED 90° CCW

0.15

0.05

SEATING PLANE

VIEW A

0° MIN

0.10 MAX COPLANARIT Y

0.75

0.60

0.45

SEATING

PLANE

0.20

0.09 7°

3.5° 0°

0.08 MAX COPLANARIT Y

.

0

.

0

.

0

0.20

0.08

1

A

X

M

5

7

0

6

5

4

1

13

7° 0°

E

I

V

COMPLIANT TO JEDEC STANDARDS MS-026-BCC-HD

14

A

W

12.20

12.00 SQ

11.8 0

N

1

I

P

TOP VIEW

(PINS DOWN)

0.65

BSC

LEAD PITCH

2.65

2.50 (4 PLCS)

2.35

4052 40 52

39

27

0.38

0.32

0.22

26

0

6

.

Figure 48. 52-Lead Low Profile Quad Flat Package, PowerQuad [LQFP_PQ4]

(SQ-52-1)

Dimensions shown in millimeters

1.20 MAX

13

12.00 BSC SQ

52

1

PIN 1

TOP VIEW

(PINS DOWN)

14

VIEW A

COMPLIANT TO JEDEC STANDARDS MS-026-ACC

40

39

10.00

BSC SQ

27

26

40

39

27

26

LEAD PITCH

Figure 49. 52-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

(SV-52-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD6645ASQ-80 −40°C to +85°C 52-Lead Low Profile Quad Flat Package, PowerQuad (LQFP_PQ4) SQ-52-1 AD6645ASQZ-80 AD6645ASVZ-80 AD6645ASQ-105 −10°C to +85°C 52-Lead Low Profile Quad Flat Package, PowerQuad (LQFP_PQ4) SQ-52-1 AD6645ASQZ-105 AD6645ASVZ-105 AD6645-80/PCBZ AD6645-105/PCBZ

1

Z = RoHS Compliant Part.

1

−40°C to +85°C 52-Lead Low Profile Quad Flat Package, PowerQuad (LQFP_PQ4) SQ-52-1

1

−40°C to +85°C 52-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-52-1

1

−10°C to +85°C 52-Lead Low Profile Quad Flat Package, PowerQuad (LQFP_PQ4) SQ-52-1

1

−10°C to +85°C 52-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-52-1

1

Evaluation Board

1

Evaluation Board

Rev. D | Page 24 of 24

Datasheet AD6645 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

DC SPECIFICATIONS

DIGITAL SPECIFICATIONS

AC SPECIFICATIONS

SWITCHING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

EXPLANATION OF TEST LEVELS

ESD CAUTION

THERMAL RESISTANCE

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

EQUIVALENT CIRCUITS

TERMINOLOGY

THEORY OF OPERATION

APPLYING THE AD6645

Encoding the AD6645

Driving the Analog Inputs

DIGIT AL OUTPUTS

Power Supplies

Grounding

LAYOUT INFORMATION

JITTER CONSIDERATIONS

OUTLINE DIMENSIONS

ORDERING GUIDE