ANALOG DEVICES AD6645 Service Manual

14-Bit, 80 MSPS/105 MSPS

FEATURES

SNR = 75 dB, fIN 15 MHz, up to 105 MSPS SNR = 72 dB, f SFDR = 89 dBc, f 100 dBFS multitone SFDR IF sampling to 200 MHz Sampling jitter: 0.1 ps

1.5 W power dissipation Differential analog inputs Pin compatible to AD6644 Twos complement digital output format

3.3 V CMOS compatible Data-ready for output latching

APPLICATIONS

Multichannel, multimode receivers Base station infrastructures AMPS, IS-136, CDMA, GSM, W-CDMA Single channel digital receivers Antenna array processing Communications instrumentation Radars, infrared imaging Instrumentation

GENERAL DESCRIPTION

The AD6645 is a high speed, high performance, monolithic 14-bit analog-to-digital converter (ADC). All necessary functions, including track-and-hold (T/H) and reference, are included on the chip to provide a complete conversion solution. The AD6645 provides CMOS-compatible digital outputs. It is the fourth

200 MHz, up to 105 MSPS

IN

70 MHz, up to 105 MSPS

IN

A/D Converter

AD6645

generation in a wideband ADC family, preceded by the AD9042 (12-bit, 41 MSPS), the AD6640 (12-bit, 65 MSPS, IF sampling), and the AD6644 (14-bit, 40 MSPS/65 MSPS).

Designed for multichannel, multimode receivers, the AD6645 is part of the Analog Devices, Inc., SoftCell® transceiver chipset. The AD6645 maintains 100 dB multitone, spurious-free dynamic range (SFDR) through the second Nyquist band. This breakthrough performance eases the burden placed on multimode digital receivers (software radios) that are typically limited by the ADC. Noise performance is exceptional; typical signal-to-noise ratio (SNR) is 74.5 dB through the first Nyquist band.

The AD6645 is built on the Analog Devices extra fast complementary bipolar (XFCB) process and uses an innovative, multipass circuit architecture. Units are available in thermally enhanced 52-lead PowerQuad 4 (LQFP_PQ4) and 52-lead exposed pad (TQFP_EP) packages specified from −40°C to +85°C at 80 MSPS and −10°C to +85°C at 105 MSPS.

PRODUCT HIGHLIGHTS

1. IF Sampling. The AD6645 maintains outstanding ac

performance up to input frequencies of 200 MHz, suitable for multicarrier 3G wideband cellular IF sampling receivers.

2. Pin Compatibility. The ADC has the same footprint and

pin layout as the AD6644 14-bit, 40 MSPS/65 MSPS ADC.

3. SFDR Performance and Oversampling. Multitone SFDR

performance of 100 dBFS can reduce the requirements of high end RF components and allows the use of receive signal processors, such as the AD6620, AD6624/AD6624A, or AD6636.

FUNCTIONAL BLOCK DIAGRAM

DV

AV

AIN

VREF

ENCODE

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

2.4V

INTERNAL

TIMING

GND DMID OVR DRY D13

CC

ADC1

TH2

DAC1

5

D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

MSB

TH1A1

AD6645

TH3A2

DAC2ADC2

5

DIGITAL ERROR CORRECTI ON LOGIC

Figure 1.

ADC3TH5TH4

6

LSB

02647-001

AD6645

REVISION HISTORY

10/08—Rev. C to Rev. D

Added TQFP_EP Package ............................................ Throughout

Renamed Thermal Characteristics Section Thermal Resistance

Section ................................................................................................ 7

Added Table 6; Renumbered Sequentially .................................... 7

Moved Equivalent Circuits Section .............................................. 14

Moved Terminology Section ......................................................... 15

Changes to Table 9 .......................................................................... 20

Updated Outline Dimensions ....................................................... 24

Changes to Ordering Guide .......................................................... 24

12/06—Rev. B to Rev. C

Updated Format .................................................................. Universal

Changes to Specifications ................................................................ 3

Changes to Jitter Considerations Section .................................... 19

Changes to Table 8, Bill of Materials ............................................ 20

Changes to Figure 43, Evaluation Board Schematic .................. 21

Changes to Figure 44 and Figure 46 ............................................. 22

Updated Outline Dimensions ....................................................... 23

Changes to Ordering Guide .......................................................... 23

Explanation of Test Levels ............................................................7

ESD Caution...................................................................................7

Pin Configuration and Function Descriptions ..............................8

Typical Performance Characteristics ..............................................9

Equivalent Circuits ......................................................................... 14

Terminology .................................................................................... 15

Theory of Operation ...................................................................... 17

Applying the AD6645 ................................................................ 17

Layout Information ........................................................................ 19

Jitter Considerations .................................................................. 19

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 24

7/03—Rev. A to Rev. B.

Changes to Title ................................................................................ 1

Changes to Features .......................................................................... 1

Changes to Product Description ..................................................... 1

Changes to Specifications ................................................................. 3

Changes to Absolute Maximum Ratings ........................................ 7

Changes to Ordering Guide .......................................................... 24

Updated Outline Dimensions ....................................................... 20

6/02—Rev. 0 to Rev. A.

Change to DC Specifications ........................................................... 3

Rev. D | Page 2 of 24

AD6645

SPECIFICATIONS

DC SPECIFICATIONS

AVCC = 5 V, DVCC = 3.3 V; T

Table 1.

AD6645ASQ-80/AD6645ASV-80 AD6645ASQ-105/AD6645ASV-105 Parameter Temp Test Level Min Typ Max Min Typ Max Unit

RESOLUTION 14 14 Bits ACCURACY

No Missing Codes Full II Guaranteed Guaranteed Offset Error Full II −10 +1.2 +10 −10 +1.2 +10 mV Gain Error Full II −10 0 +10 −10 0 +10 % FS Differential Nonlinearity (DNL) Full II −1.0 ±0.25 +1.5 −1.0 ±0.5 +1.5 LSB Integral Nonlinearity (INL) Full V ±0.5 ±1.5 LSB

TEMPERATURE DRIFT

Offset Error Full V 1.5 1.5 ppm/°C Gain Error Full V 48 48 ppm/°C

POWER SUPPLY REJECTION RATIO

(PSRR) REFERENCE OUT (VREF) ANALOG INPUTS (AIN, AIN)

Differential Input Voltage Range Full V 2.2 2.2 V p-p

Differential Input Resistance Full V 1 1 kΩ

Differential Input Capacitance 25°C 1.5 1.5 pF POWER SUPPLY

Supply Voltages

AVCC Full II 4.75 5.0 5.25 4.75 5.0 5.25 V DVCC Full II 3.0 3.3 3.6 3.0 3.3 3.6 V

Supply Current

IAVCC (AVCC = 5.0 V) Full II 275 320 275 320 mA IDVCC (DVCC = 3.3 V) Full II 32 45 32 45 mA

Rise Time

2

AVCC Full IV 250 5.0 250 ms

POWER CONSUMPTION Full II 1.5 1.75 1.5 1.75 W

1

VREF is provided for setting the common-mode offset of a differential amplifier, such as the AD8138, when a dc-coupled analog input is required. VREF should be

buffered if used to drive additional circuit functions.

2

Specified for dc supplies with linear rise time characteristics.

MIN

and T

at rated speed grade, unless otherwise noted.

MAX

25°C V ±1.0 ±1.0 mV/V

1

Full V 2.4 2.4 V

Rev. D | Page 3 of 24

AD6645

DIGITAL SPECIFICATIONS

AVCC = 5 V, DVCC = 3.3 V; T

Table 2.

Test AD6645ASQ-80/AD6645ASV-80 AD6645ASQ-105/AD6645ASV-105 Parameter Temp Level Min Typ Max Min Typ Max Unit

ENCODE INPUTS (ENCODE, ENCODE)

Differential Input Voltage Differential Input Resistance 25°C V 10 10 kΩ Differential Input Capacitance 25°C V 2.5 2.5 pF

LOGIC OUTPUTS (D13 to D0, DRY, OVR)

Logic Compatibility CMOS CMOS Logic 1 Voltage (DVCC = 3.3 V) Logic 0 Voltage (DVCC = 3.3 V) Output Coding Twos complement Twos complement DMID Full V DVCC/2 DVCC/2 V

1

All ac specifications tested by driving ENCODE and

2

Digital output logic levels: DVCC = 3.3 V, C

AC SPECIFICATIONS

All ac specifications tested by driving ENCODE and T

at rated speed grade, unless otherwise noted.

MAX

MIN

and T

at rated speed grade, unless otherwise noted.

MAX

1

2

Full II 0.2 0.5 0.2 0.5 V

Full IV 0.4 0.4 V p-p

Full II 2.85 DVCC − 2 2.85 DVCC − 2 V

ENCODE

= 10 pF. Capacitive loads >10 pF degrades performance.

LOAD

differentially.

ENCODE

differentially. AVCC = 5 V, DVCC = 3.3 V; ENCODE,

ENCODE

, T

MIN

and

Table 3.

AD6645ASQ-80/

Test

AD6645ASV-80

AD6645ASQ-105/

AD6645ASV-105

Parameter Temp Level Min Typ Max Min Typ Max Unit Conditions

SNR

Analog Input @ −1 dBFS 25°C V 75.0 75.0 dB At 15.5 MHz Full II 72.5 74.5 dB At 30.5 MHz 25°C I 72.5 74.5 dB At 37.7 MHz Full II 72.0 73.5 72.0 73.5 dB At 70.0 MHz 25°C V 73.0 73.0 dB At 150.0 MHz 25°C V 72.0 72.0 dB At 200.0 MHz SINAD

Analog Input @ −1 dBFS 25°C V 75.0 75.0 dB At 15.5 MHz Full II 72.5 74.5 dB At 30.5 MHz 25°C I 72.5 74.5 dB At 37.7 MHz Full V 73.0 73.0 dB At 70.0 MHz 25°C V 68.5 67.5 dB At 150.0 MHz 25°C V 62.5 62.5 dB At 200.0 MHz WORST HARMONIC (SECOND OR THIRD)

Analog Input @ −1 dBFS 25°C V 93.0 93.1 dBc At 15.5 MHz Full II 85.0 93.0 dBc At 30.5 MHz 25°C I 85.0 93.0 dBc At 37.7 MHz Full V 89.0 87.0 dBc At 70.0 MHz 25°C V 70.0 70.0 dBc At 150.0 MHz 25°C V 63.5 63.5 dBc At 200.0 MHz

Rev. D | Page 4 of 24

AD6645

AD6645ASQ-80/

Test

AD6645ASV-80

Parameter Temp Level Min Typ Max Min Typ Max Unit Conditions

WORST HARMONIC (FOURTH OR HIGHER)

Analog Input @ −1 dBFS 25°C V 96.0 96.0 dBc At 15.5 MHz Full II 85.0 95.0 dBc At 30.5 MHz 25°C I 86.0 95.0 dBc At 37.7 MHz Full V 90.0 90.0 dBc At 70.0 MHz 25°C V 90.0 90.0 dBc At 150.0 MHz 25°C V 88.0 88.0 dBc At 200.0 MHz TWO-TONE SFDR 25°C V 100 98.0 dBFS At 30.5 MHz 25°C V 100 98.0 dBFS At 55.0 MHz 25°C V 98.0 dBFS At 70.0 MHz

2, 3

TWO-TONE IMD REJECTION

F1, F2 @ −7 dBFS 25°C V 90 90 dBc ANALOG INPUT BANDWIDTH 25°C V 270 270 MHz

1

Analog input signal power swept from −10 dBFS to −100 dBFS.

2

F1 = 30.5 MHz, F2 = 31.5 MHz.

3

F1 = 55.25 MHz, F2 = 56.25 MHz.

4

F1 = 69.1 MHz, F2 = 71.1 MHz.

SWITCHING SPECIFICATIONS

AVCC = 5 V, DVCC = 3.3 V; ENCODE,

ENCODE

, T

MIN

and T

at rated speed grade, unless otherwise noted.

MAX

AD6645ASQ-105/

AD6645ASV-105

1, 2

1, 3

1, 4

Table 4.

AD6645ASQ-80/

Test

AD6645ASV-80

AD6645ASQ-105/

AD6645ASV-105

Parameter Symbol Temp Level Min Typ Max Min Typ Max Unit

ENCODE INPUT PARAMETERS

1

Maximum Conversion Rate Full II 80 105 MSPS

Minimum Conversion Rate Full IV 30 30 MSPS

ENCODE Pulse Width High, t

ENCH

2

Full IV 5.625 4.286 ns Full V 6.25 4.75 ns ENCODE Pulse Width Low, t

2

Full IV 5.625 4.286 ns

ENCL

Full V 6.25 4.75 ns ENCODE Period

1

t

Full V 12.5 9.5 ns

ENC

ENCODE/DATA-READY

ENCODE Rising to Data-Ready Falling tDR Full V 1.0 2.0 3.1 1.0 2.0 3.1 ns ENCODE Rising to Data-Ready Rising t

Full V t

E_DR

+ tDR t

ENCH

+ tDR ns

ENCH

50% Duty Cycle Full V 7.3 8.3 9.4 5.7 6.75 7.9 ns

ENCODE/DATA (D13:0), OVR

ENCODE to DATA Falling Low t ENCODE to DATA Rising Low

3

ENCODE to DATA Delay3 (Hold Time) t ENCODE to DATA Delay (Setup Time) t

Full V 2.4 4.7 7.0 2.4 4.7 7.0 ns

E_FL

t

Full V 1.4 3.0 4.7 1.4 3.0 4.7 ns

E_RL

Full V 1.4 3.0 4.7 1.4 3.0 4.7 ns

H_E

Full V

S_E

t

ENC

t

E_FL(max)

−

t

ENC

t

E_FL(typ)

−

t

ENC

t

E_FL(max)

−

t

ENC

t

E_FL(min)

ns

t

ENC

t

E_FL(typ)

−

ns

−

t

ENC

t

E_FL(min)

ns

50% Duty Cycle Full V 5.3 7.6 10.0 2.3 4.8 7.0 ns

Rev. D | Page 5 of 24

AD6645

AD6645ASQ-80/

Test

AD6645ASV-80

Parameter Symbol Temp Level Min Typ Max Min Typ Max Unit

DATA-READY (DRY4)/DATA(D13:0),, OVR

Data-Ready to DATA Delay (Hold Time) t

Full V Note 5

H_DR

5

Note 5

50% Duty Cycle Full V 6.6 7.2 7.9 5.1 5.7 6.4 ns

Data-Ready to DATA Delay (Setup Time) t

Full V Note 5

S_DR

5

Note 5

50% Duty Cycle Full V 2.1 3.6 5.1 0.6 2.1 3.5 ns APERTURE DELAY tA 25°C V −500 −500 ps APERTURE UNCERTAINTY (JITTER) tJ 25°C V 0.1 0.1 ps rms

1

Several timing parameters are a function of t

2

Several timing parameters are a function of t

3

ENCODE TO DATA Delay (Hold Time) is the absolute minimum propagation delay through the ADC, t

4

DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock will correspondingly change the duty cycle of DRY.

5

Data-ready to DATA Delay (t

H_DR

and t

S_DR

and t

ENCH

.

E_RL

ENC

ENCL

) is calculated relative to rated speed grade and is dependent on t

= t

.

H_E

and duty cycle.

ENC

t

A

N

N + 3

AD6645ASQ-105/

AD6645ASV-105

5

AIN

ENCODE, ENCODE

D[13:0], OV R

DRY

t

E_RL

t

ENC

t

E_FL

N + 1

t

ENCHtENCL

N – 2

N + 2

N + 4

N + 4N + 3N + 2N + 1N

t

E_DR

t

S_DR

t

DR

t

H_DR

t

S_E

t

H_E

NN – 1N – 3

2647-002

Figure 2. Timing Diagram

Rev. D | Page 6 of 24

AD6645

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Electrical

AV

Voltage 0 V to 7 V

CC

DV

Voltage 0 V to 7 V

CC

Analog Input Voltage 0 V to AVCC Analog Input Current 25 mA Digital Input Voltage 0 V to AVCC Digital Output Current 4 mA

Environmental

Operating Temperature Range (Ambient)

AD6645-80 −40°C to +85°C

AD6645-105 −10°C to +85°C Maximum Junction Temperature 150°C Lead Temperature (Soldering, 10 sec) 300°C Storage Temperature Range (Ambient) −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Val u es o f θJA are provided for package comparison and PCB design considerations. θ approximation of T

= TA + (θJA × PD)

T

J

can be used for a first-order

JA

by the equation

J

where:

T

is the ambient temperature (°C).

A

PD is the power dissipation (W).

EXPLANATION OF TEST LEVELS

I. 100% production tested.

II. 100% production tested at 25°C and guaranteed by design

and characterization at temperature extremes.

III. Sample tested only.

IV. Parameter is guaranteed by design and characterization

testing.

V. Parameter is a typical value only.

ESD CAUTION

THERMAL RESISTANCE

The heat sink of the AD6645ASVZ, 52-lead TQFP_EP (SV-52-1) package must be soldered to the PCB GND plane to meet thermal specifications.

Table 6. Thermal Characteristics

Package Type Rating

52-Lead TQFP_EP

θJA (0 m/sec airflow) θ

(1.0 m/sec airflow)

JMA

6, 7

θ

2°C/W, soldered heat sink

JC

52-Lead LQFP_PQ4

θJA (0 m/sec airflow) θ

(1.0 m/sec airflow)

JMA

θJA (0 m/sec airflow) θ

(1.0 m/sec airflow)

JMA

6, 7

θ

2°C/W

JC

1

Per JEDEC JESD51-2 (heat sink soldered to PCB).

2

2S2P JEDEC test board.

3

Values of θJA are provided for package comparison and PCB design

considerations.

4

Per JEDEC JESD51-6 (heat sink soldered to PCB).

5

Airflow increases heat dissipation, effectively reducing θJA. Furthermore, the

more metal that is directly in contact with the package leads from metal traces, throughholes, ground, and power planes, the more θ

6

Per MIL-STD-883, Method 1012.1.

7

Values of θJC are provided for package comparison and PCB design

considerations when an external heat sink is required.

1, 2, 3

23°C/W, soldered heat sink

2, 3, 4, 5

17°C/W, soldered heat sink

1, 2, 3

30°C/W, unsoldered heat sink

2, 3, 4, 5

24°C/W, unsoldered heat sink

1, 2, 3

23°C/W, soldered heat sink

2, 3, 4, 5

17°C/W, soldered heat sink

is reduced.

JA

Rev. D | Page 7 of 24

AD6645

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CC

D13 (MSB)52DRY

49

50

51

44D645D746D847D948

D10

D11

D12

D441D542GND43DV

40

1

DV

CC

GND

VREF

GND

ENCODE

GND

AV

CC

AV

CC

GND

AIN

GND

NOTES

1. DNC = DO NOT CONNECT.

2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND.

PIN 1

2

IDENTIFIER

3

4

5

6

7

8

9

10

11

12

13

14

15

CC

GND

AV

16

CC

AV

AD6645

TOP VIEW

(Not to Scale)

17

18

CC

GND

AV

19

20C121

22

23

24C225

GND

CC

GND

AV

39

D3

38

D2

37

D1

36

D0 (LSB)

35

DMID

34

GND

33

DV

CC

32

OVR

31

DNC

30

AV

CC

29

GND

28

AV

CC

27

GND

26

CC

GND

AV

02647-003

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

Pin Number Mnemonic Description

1, 33, 43 DVCC 3.3 V Power Supply (Digital) Output Stage Only. 2, 4, 7, 10, 13, 15, 17, 19, 21, 23, 25,

GND Ground.

27, 29, 34, 42 3 VREF 2.4 V Reference. Bypass to ground with a 0.1 μF microwave chip capacitor. 5 ENCODE Encode Input. Conversion initiated on rising edge. 6

ENCODE

Complement of

ENCODE

, Differential Input. 8, 9, 14, 16, 18, 22, 26, 28, 30 AVCC 5 V Analog Power Supply. 11 AIN Analog Input. 12

AIN

Complement of AIN, Differential Analog Input.

20 C1 Internal Voltage Reference. Bypass to ground with a 0.1 μF chip capacitor. 24 C2 Internal Voltage Reference. Bypass to ground with a 0.1 μF chip capacitor. 31 DNC Do not connect this pin. 32 OVR Overrange Bit. A logic level high indicates analog input exceeds ±FS. 35 DMID Output Data Voltage Midpoint. Approximately equal to (DVCC)/2. 36 D0 (LSB) Digital Output Bit (Least Significant Bit); Twos Complement. 37 to 41, 44 to 50 D1 to D5, D6 to D12 Digital Output Bits in Twos Complement. 51 D13 (MSB) Digital Output Bit (Most Significant Bit); Twos Complement. 52 DRY Data-Ready Output. 53 (EPAD) Exposed Paddle (EPAD) Exposed Pad. Connect the exposed pad to GND.

Rev. D | Page 8 of 24

ANALOG DEVICES AD6645 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

DC SPECIFICATIONS

DIGITAL SPECIFICATIONS

AC SPECIFICATIONS

SWITCHING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

EXPLANATION OF TEST LEVELS

ESD CAUTION

THERMAL RESISTANCE

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS