Analog Devices AD6458 Datasheet

a

GSM 3 V Receiver IF Subsystem

AD6458

FEATURES
Fully Compliant with Standard and Enhanced GSM

Specification

–12 dBm Input 1 dB Compression Point
–2 dBm Input Third Order Intercept
10 dB SSB Noise Figure (330 V)

DC–400 MHz RF and LO Bandwidths

Linear IF Amplifier

Linear-in-dB and Stable over Temperature Voltage
Gain Control
Quadrature Demodulator

Onboard Phase-Locked Quadrature Oscillator

Demodulates IFs from 5 MHz to 50 MHz
Low Power

9 mA at Midgain

1 mA Sleep Mode Operation

3.0 V to 3.6 V Operation

Interfaces to AD7013, AD7015 and AD6421 Baseband

Converters
20-Lead SSOP

GENERAL DESCRIPTION

The AD6458 is a 3 V, low power receiver IF subsystem for
operation at input frequencies as high as 400 MHz and IFs from
5 MHz up to 50 MHz. It is optimized for operation in GSM,
DCS1800 and PCS1900 receivers. It consists of a mixer, IF
amplifier, I and Q demodulators, a phase-locked quadrature
oscillator, precise AGC subsystem, and a biasing system with
external power-down.

The low noise, high intercept mixer of the AD6458 is a
doubly-balanced Gilbert cell type. It has a nominal –12 dBm
input-referred 1 dB compression point and a –2 dBm input­referred third-order intercept. The mixer section of the AD6458
also includes a local oscillator (LO) preamplifier, which lowers
the required LO drive to –16 dBm.

The gain control input accepts an external gain-control voltage
input from an external AGC detector or a DAC. It provides an
80 dB gain range with 27 mV/dB gain scaling.

The I and Q demodulators provide inphase and quadrature
baseband outputs to interface with Analog Devices’ AD7013
(IS54, TETRA, MSAT) and AD7015 and AD6421 (GSM,
DCS1800, PCS1900) baseband converters. An onboard

FUNCTIONAL BLOCK DIAGRAM

LO

I

RF

AGC

FREF

quadrature VCO which is externally phase-locked to the IF
signal drives the I and Q demodulators. This locked reference
signal is normally provided by an external VCTCXO under the
control of the radio’s digital processor. The AD6458 can also
provide demodulation of N-PSK and N-QAM in many non­TDMA systems when used with external analog carrier recovery
systems such as the Costas Loop. Finally, the VCO can be
phase-locked to a frequency which is deliberately offset from the
IF, as in the case of a Beat-Frequency Oscillator (BFO), result­ing in the product detection of CW or SSB.

The AD6458 uses supply voltages from 3.0 V to 3.6 V over the
temperature range of –40°C to +85°C. Operation is enabled by
a CMOS logical level; response time is typically <80 µs. When
disabled, the standby current is reduced to 1 µA.

The AD6458 comes in a 20-lead shrink small outline (SSOP)
surface-mount package.

BPF

AD6458

PLO

Q

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1997

AD6458–SPECIFICATIONS

(@ TA = +258C, VP = 3.0 V, GREF = 1.2 V, unless otherwise noted)

Parameter Conditions Min Typ Max Units

MIXER

Maximum RF and LO Frequency 400 MHz
AGC Conversion Gain Variation 0.2 V < V

< 2.25 V, ZS = 50 Ω, Z

G

= 330 Ω –8.5 to +9.5 dB

LOAD

Input RF Signal Range –95 –15 dBm
Input 1 dB Compression Point @ V
Input Third-Order Intercept @ V
SSB Noise Figure

1

Mixer Output Bandwidth at MXOP @ –3 dB, Z

= 0.2 V, ZS = 50 Ω, Z

G

= 0.2 V, ZS = 50 Ω, Z

G

= 330 Ω –11 dBm

LOAD

= 330 Ω –2 dBm

LOAD

@ ZS =1 kΩ, FRF = 83 MHz, FLO = 96 MHz at –16 dBm 9 dB

= 330 Ω 55 MHz

LOAD

IF AMPLIFIERS

AGC Gain Variation 0.2 V < V

< 2.25 V –9 to +48 dB

G

Input Referred Noise AC Short Circuit Input 3 nV/Hz
Input Resistance @ V

= 0.2 V 5 kΩ

G

Bandwidth @ –3 dB 50 MHz

I AND Q DEMODULATORS

Demodulation Gain 17 dB
Output Voltage Range IRXP, IRXN, QRXP, QRXN 0.3 V

– 0.2 V

P

Output Voltage Common-Mode Level (Not Power Supply Dependant) 1.5 V
Output Offset Voltage Differential –150 +150 mV
Output Offset Voltage Variation Differential, over Gain and Temperature Range
Output Offset Voltage Variation Differential, for 0.5 V < V

–25°C < T

< +85°C (See Note 2) 0.5 mV

A

< 2.4 V and

G

2

1mV

Error in Quadrature IF = 13 MHz 1.5 3.7 Degree
Amplitude Match 0.25 dB
I/Q Output Bandwidth C

= 10 pF 2 MHz

LOAD

Output Resistance Each Pin 4.7 kΩ

GAIN CONTROL

Total Gain Control Range Mixer + IF + Demod, 0.2 V < V

< 2.25 V 75 dB

G

Control Voltage Range at GAIN 0.2 2.4 V
Gain Scaling 23 27 32 mV/dB
Gain Law Conformance ±0.5 dB
Bias Current at GREF 0.5 µA
Input Resistance at GAIN 20 kΩ

PLL

Frequency Range 5 40 MHz
Phase Noise 0.5 Degree rms
Acquisition Time IF = 13 MHz, Using Ceramic Filter 80 µs
Input Drive Level (FREF) 100 VPOS mV

POWER-DOWN INTERFACE

Logical Threshold Power-Up On Logical High 1.5 V
Input Current for Logical High 75 µA
Turn On Response Time To Fully Meet Specifications 80 150 µs
Stand By Current (See Note 3) 1 8 µA

POWER SUPPLY

Supply Range 3.0 3.3 3.6 V
Worst Case Supply Current @ V
Supply Current @ V

= 0.2 V, TA = +85°C, VP = 3.6 V

GAIN

= 1.2 V 9 mA

GAIN

4

16.5 22 mA

OPERATING TEMPERATURE

T

to T

MIN

MAX

NOTES

1

Including IF noise and using 13 MHz ceramic filter, at V

2

Histograms of Demodulator Offset Voltage Variation in Gain and Temperature can be found in Figures 23 to 27.

3

Max value represent the value at six times the standard deviation, in the worst case condition (TA = +85°C). The value at three times the standard deviation is 5 µA.

4

Max value represent the value at six times the standard deviation. The value at three times the standard variation is 19 mA.

Specifications subject to change without notice.

GAIN

= 0.2 V.

–40 to +85 °C

–2–

REV. 0

AD6458

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

Supply Voltage VPS1, VPS2 to COM1, COM2 . . . . . +3.6 V

Internal Power Dissipation

2

. . . . . . . . . . . . . . . . . . . . 600 mW

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature, Soldering (60 sec) . . . . . . . . . . . +300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended rating conditions for extended periods may affect device
reliability.

2

Thermal Characteristics: 20-Lead SSOP Package: θJA = 126°C/W.

ORDERING GUIDE

1

PIN CONNECTION

20-Lead SSOP (RS-20)

1

FREF

2

COM1

3

PRUP

4

LOIP

5

AD6458

TOP VIEW

6

RFHI

(Not to Scale)

7

COM2

8

GREF

9

MXOP

NC IFIP

10

NC = NO CONNECT

20

VPS1

19

FLTR

18

VPS2

17

IRXP

16

IRXNRFLO

15

QRXP

14

QRXN
GAIN

13

IFIM

12
11

Temperature Package Package

Model Range Description Option

AD6458ARS –40°C to +85°C 20-Lead Shrink Small Outline RS-20

PIN FUNCTION DESCRIPTIONS

Pin Pin
Number Label Description Function

1 FREF Frequency Reference Input Demodulation LO Input. May be 3 V CMOS input or >100 mV ac coupled for

lowest stand by current.
2 COM1 Common 1 Ground.
3 PRUP Power-Up Input CMOS compatible power up control; 0 = OFF, 3 V = ON.
4 LOIP Local Oscillator Input AC coupled LO input. Only 50 mV drive needed, 500 mV max.
5 RFLO RF “Low” Input Usually connected to ac ground.
6 RFHI RF “High” Input AC coupled, –109 dBV to –29 dBV RF input from 1 kΩ filter for optimal operation.
7 COM2 Common 2 Ground.
8 GREF Gain Reference Input High impedance input, sets gain scaling, typically 1.2 V.
9 MXOP Mixer Output Output of the Mixer.
10 NC Not internally connected. Should be grounded.
11 IFIP IF Input “Plus” Differential Input of variable gain amplifier.
12 IFIM IF Input “Minus” Differential Input of variable gain amplifier.
13 GAIN Gain Control Input 0.2 V–2.4 V using 3 V supply. Max gain at 0.2 V.
14 QRXN Q Output “Negative” Differential Q Output.
15 QRXP Q Output “Positive” Differential Q Output.
16 IRXN I Output “Negative” Differential I Output.
17 IRXP I Output “Positive” Differential I Output.
18 VPS2 VPOS Supply 2 Supply Voltage.
19 FLTR PPL Loop Filter Series RC loop filter, connected to VPS2.
20 VPS1 VPOS Supply 1 Supply Voltage.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6458 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0

–3–

AD6458

R1

20kΩ

C12

C2

1nF

C3

1nF

OPEN

220pF

C4 1nF

R5

C6

1nF

FREF

1

COM1

2

PRUP

3

LOIP

4

AD6458

RFLO

5

RFHI

6

COM2

7

GREF

8

MXOP

9

10

FREF

R9

50Ω

PRUP

LOIP

RFHI

GREF

R2

50Ω

R3

50Ω

R10

301Ω

R4

54.9Ω

MXOP IFIP IFIM

VSP1

FLTR

VSP2

IRXP

IRXN

QRXP

QRXN

GAIN

IFIM

IFIP

VPOS

20

19

18

17

16

15

14

13

12

11

C10 1nF

C7

0.01µF

C1

0.1µF

R8 1kΩ

C8

0.01µF

R6

50ΩR750Ω

Figure1. Characterization Board

C11

0.1µF

C10

0.1µF
(BOTTOM)

VPOS

IRXP

IRXN

QRXP

QRXN

GAIN

VPOS

FREF

PRUP

LOIP

RFIP

GREF

MXOP

IFIN

FREF

PRUP

LOIP

CHARACTERIZATION

RFIP

GREF

MXOP IFIP IFIM

AD830

R1
100Ω

A=1

V

P

V

N

1

Gm

2

3

Gm

4

AD6458

BOARD

8

7

6

5

VPOS

C11

0.1pF

C10

0.1pF

IRXP

IRXN

QRXP

QRXN

GAIN

V

P

V

N

R6
50Ω

V

P

C6

8

0.1pF

7

6

5

C7

0.1pF

C4

8

0.1pF

7

6

5

C5

0.1pF

C9

8

0.1pF

7

6

5

C8

0.1pF

R4

50Ω

I

OUT

V

N

V

P

R3

50Ω

Q

OUT

V

N

GAIN

V

P

R5
50Ω

V

N

AD830

AD830

AD830

A=1

A=1

A=1

V

P

V

N

V

P

V

N

V

P

V

N

1

Gm

2

3

Gm

4

1

Gm

2

3

Gm

4

1

Gm

2

3

Gm

4

Figure 2. Characterization Test Set

–4–

REV. 0